kopia lustrzana https://github.com/espressif/esp-idf
soc: fix memory map for esp32 and esp32s2beta
Michael (XIAO Xufeng)
rodzic
df27a50866
commit
d7d5aebdee
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@ -44,9 +44,9 @@ const soc_memory_type_desc_t soc_memory_types[] = {
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// Type 1: DRAM used for startup stacks
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{ "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
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//Type 2: DRAM which has an alias on the I-port
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//(This DRAM is also the region used by ROM during startup)
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
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{ "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, false},
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//Type 3: IRAM
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//In ESP32S2beta, All IRAM region are available by D-port (D/IRAM).
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{ "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
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//Type 4: SPI SRAM data
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//TODO, in fact, part of them support EDMA, to be supported.
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@ -75,41 +75,41 @@ const soc_memory_region_t soc_memory_regions[] = {
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#endif
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#if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB
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#if CONFIG_ESP32S2_DATA_CACHE_0KB
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{ 0x3FFB2000, 0x2000, 0, 0x40022000}, //Block 1, can be use as I/D cache memory
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{ 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory
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{ 0x3FFB2000, 0x2000, 2, 0x40022000}, //Block 1, can be use as I/D cache memory
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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{ 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#else
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{ 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#endif
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#else
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#if CONFIG_ESP32S2_DATA_CACHE_0KB
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{ 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory
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{ 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#elif CONFIG_ESP32S2_DATA_CACHE_8KB
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{ 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory
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{ 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory
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#endif
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#endif
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{ 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
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{ 0x3FFBC000, 0x4000, 0, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
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{ 0x3FFC0000, 0x4000, 0, 0x40030000}, //Block 6, can be used as trace memory
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{ 0x3FFC4000, 0x4000, 0, 0x40034000}, //Block 7, can be used as trace memory
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{ 0x3FFC8000, 0x4000, 0, 0x40038000}, //Block 8, can be used as trace memory
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{ 0x3FFCC000, 0x4000, 0, 0x4003C000}, //Block 9, can be used as trace memory
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{ 0x3FFB8000, 0x4000, 2, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory
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{ 0x3FFBC000, 0x4000, 2, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory
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{ 0x3FFC0000, 0x4000, 2, 0x40030000}, //Block 6, can be used as trace memory
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{ 0x3FFC4000, 0x4000, 2, 0x40034000}, //Block 7, can be used as trace memory
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{ 0x3FFC8000, 0x4000, 2, 0x40038000}, //Block 8, can be used as trace memory
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{ 0x3FFCC000, 0x4000, 2, 0x4003C000}, //Block 9, can be used as trace memory
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{ 0x3FFD0000, 0x4000, 0, 0x40040000}, //Block 10, can be used as trace memory
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{ 0x3FFD4000, 0x4000, 0, 0x40044000}, //Block 11, can be used as trace memory
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{ 0x3FFD8000, 0x4000, 0, 0x40048000}, //Block 12, can be used as trace memory
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{ 0x3FFDC000, 0x4000, 0, 0x4004C000}, //Block 13, can be used as trace memory
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{ 0x3FFE0000, 0x4000, 0, 0x40050000}, //Block 14, can be used as trace memory
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{ 0x3FFE4000, 0x4000, 0, 0x40054000}, //Block 15, can be used as trace memory
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{ 0x3FFE8000, 0x4000, 0, 0x40058000}, //Block 16, can be used as trace memory
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{ 0x3FFEC000, 0x4000, 0, 0x4005C000}, //Block 17, can be used as trace memory
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{ 0x3FFF0000, 0x4000, 0, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF4000, 0x4000, 0, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF8000, 0x4000, 0, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
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{ 0x3FFD0000, 0x4000, 2, 0x40040000}, //Block 10, can be used as trace memory
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{ 0x3FFD4000, 0x4000, 2, 0x40044000}, //Block 11, can be used as trace memory
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{ 0x3FFD8000, 0x4000, 2, 0x40048000}, //Block 12, can be used as trace memory
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{ 0x3FFDC000, 0x4000, 2, 0x4004C000}, //Block 13, can be used as trace memory
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{ 0x3FFE0000, 0x4000, 2, 0x40050000}, //Block 14, can be used as trace memory
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{ 0x3FFE4000, 0x4000, 2, 0x40054000}, //Block 15, can be used as trace memory
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{ 0x3FFE8000, 0x4000, 2, 0x40058000}, //Block 16, can be used as trace memory
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{ 0x3FFEC000, 0x4000, 2, 0x4005C000}, //Block 17, can be used as trace memory
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{ 0x3FFF0000, 0x4000, 2, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF4000, 0x4000, 2, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory
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{ 0x3FFF8000, 0x4000, 2, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory
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{ 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack
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};
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@ -15,6 +15,7 @@
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#include <string.h>
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#include "esp_log.h"
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#include "soc/soc_memory_layout.h"
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#include "sdkconfig.h"
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static const char *TAG = "memory_layout";
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@ -69,8 +70,19 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
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/* Add the EXTRA_RESERVED_REGIONS at the beginning */
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reserved[0].start = (intptr_t)&_data_start; /* DRAM used by data+bss */
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reserved[0].end = (intptr_t)&_static_data_end;
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#if CONFIG_IDF_TARGET_ESP32
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//ESP32 has a IRAM-only region 0x4008_0000 - 0x4009_FFFF, protect the used part
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reserved[1].start = (intptr_t)&_iram_start; /* IRAM used by code */
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reserved[1].end = (intptr_t)&_iram_end;
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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//ESP32S2 has a big D/IRAM region, the part used by code is reserved
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//The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address
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const uint32_t i_d_offset = SOC_IRAM_LOW - SOC_DRAM_LOW;
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reserved[1].start = (intptr_t)&_iram_start - i_d_offset; /* IRAM used by code */
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reserved[1].end = (intptr_t)&_iram_end - i_d_offset;
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#else
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# error chip not implemented!
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#endif
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/* Sort by starting address */
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qsort(reserved, count, sizeof(soc_reserved_region_t), s_compare_reserved_regions);
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@ -127,15 +139,14 @@ size_t soc_get_available_memory_regions(soc_memory_region_t *regions)
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bool move_to_next = true;
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for (size_t i = 0; i < num_reserved; i++) {
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if (reserved[i].start >= SOC_DRAM_HIGH && in_end < SOC_DRAM_HIGH && in.iram_address != 0) {
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reserved[i].start = reserved[i].start - (in.iram_address - in.start);
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reserved[i].end = reserved[i].end - (in.iram_address - in.start);
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}
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if (reserved[i].end <= in_start || reserved[i].start >= in_end) {
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/* reserved region ends before 'in' starts or reserved region starts after 'in' ends */
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if (reserved[i].end <= in_start) {
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/* reserved region ends before 'in' starts */
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continue;
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}
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else if (reserved[i].start >= in_end) {
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/* reserved region starts after 'in' ends */
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break;
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}
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else if (reserved[i].start <= in_start &&
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reserved[i].end >= in_end) { /* reserved covers all of 'in' */
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ESP_EARLY_LOGV(TAG, "Region 0x%08x - 0x%08x inside of reserved 0x%08x - 0x%08x",
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