From 0fd3824f91e73ddcb52087d39cdf76dd017f38fc Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Fri, 14 Oct 2022 15:33:53 +0800 Subject: [PATCH] bugfix: esprv_intc_int_set_type should not use bitmap parameter --- components/esp_hw_support/port/esp32c3/esp_memprot.c | 2 +- components/esp_system/port/soc/esp32c3/cache_err_int.c | 2 +- components/esp_system/port/soc/esp32h2/cache_err_int.c | 2 +- components/hal/esp32c3/include/hal/interrupt_controller_ll.h | 2 +- components/hal/esp32h2/include/hal/interrupt_controller_ll.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_hw_support/port/esp32c3/esp_memprot.c b/components/esp_hw_support/port/esp32c3/esp_memprot.c index bbda57d2b2..41af6532c4 100644 --- a/components/esp_hw_support/port/esp32c3/esp_memprot.c +++ b/components/esp_hw_support/port/esp32c3/esp_memprot.c @@ -629,7 +629,7 @@ static esp_err_t esp_mprot_set_intr_matrix(const esp_mprot_mem_t mem_type) } /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(BIT(ETS_MEMPROT_ERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_type(ETS_MEMPROT_ERR_INUM, INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_MEMPROT_ERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_INTR_ENABLE(ETS_MEMPROT_ERR_INUM); diff --git a/components/esp_system/port/soc/esp32c3/cache_err_int.c b/components/esp_system/port/soc/esp32c3/cache_err_int.c index 20cf2be2a2..81747139a2 100644 --- a/components/esp_system/port/soc/esp32c3/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c3/cache_err_int.c @@ -58,7 +58,7 @@ void esp_cache_err_int_init(void) intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); /* On the hardware side, stat by clearing all the bits reponsible for diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c index cf70e63f71..e6c3967b72 100644 --- a/components/esp_system/port/soc/esp32h2/cache_err_int.c +++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c @@ -58,7 +58,7 @@ void esp_cache_err_int_init(void) intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM); /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL); + esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); /* On the hardware side, stat by clearing all the bits reponsible for diff --git a/components/hal/esp32c3/include/hal/interrupt_controller_ll.h b/components/hal/esp32c3/include/hal/interrupt_controller_ll.h index 70afe314cf..cf32d23fa1 100644 --- a/components/hal/esp32c3/include/hal/interrupt_controller_ll.h +++ b/components/hal/esp32c3/include/hal/interrupt_controller_ll.h @@ -124,7 +124,7 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level) */ static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) { - esprv_intc_int_set_type(BIT(intr), type); + esprv_intc_int_set_type(intr, type); } #ifdef __cplusplus diff --git a/components/hal/esp32h2/include/hal/interrupt_controller_ll.h b/components/hal/esp32h2/include/hal/interrupt_controller_ll.h index 70afe314cf..cf32d23fa1 100644 --- a/components/hal/esp32h2/include/hal/interrupt_controller_ll.h +++ b/components/hal/esp32h2/include/hal/interrupt_controller_ll.h @@ -124,7 +124,7 @@ static inline void intr_cntrl_ll_set_int_level(int intr, int level) */ static inline void intr_cntrl_ll_set_int_type(int intr, int_type_t type) { - esprv_intc_int_set_type(BIT(intr), type); + esprv_intc_int_set_type(intr, type); } #ifdef __cplusplus