diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
index c1f6352311..a0a48312e0 100644
--- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -18,6 +18,7 @@
 
 #if SOC_KEY_MANAGER_SUPPORTED
 #include "hal/key_mgr_hal.h"
+#include "hal/mspi_timing_tuning_ll.h"
 #include "soc/keymng_reg.h"
 #endif
 
@@ -217,8 +218,15 @@ static esp_err_t check_and_generate_encryption_keys(void)
     }
 
 #if SOC_KEY_MANAGER_SUPPORTED
+#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
+    // TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
+    REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+    REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+    REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
+#endif
     // Force Key Manager to use eFuse key for XTS-AES operation
     key_mgr_hal_set_key_usage(ESP_KEY_MGR_XTS_AES_128_KEY, ESP_KEY_MGR_USE_EFUSE_KEY);
+    _mspi_timing_ll_reset_mspi();
 #endif
 
     return ESP_OK;
@@ -263,13 +271,6 @@ esp_err_t esp_flash_encrypt_contents(void)
     esp_partition_info_t partition_table[ESP_PARTITION_TABLE_MAX_ENTRIES];
     int num_partitions;
 
-#if CONFIG_IDF_TARGET_ESP32C5 && SOC_KEY_MANAGER_SUPPORTED
-    // TODO: [ESP32C5] IDF-8622 find a more proper place for these codes
-    REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
-    REG_SET_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
-    REG_CLR_BIT(PCR_MSPI_CLK_CONF_REG, PCR_MSPI_AXI_RST_EN);
-#endif
-
 #ifdef CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK
     REG_WRITE(SENSITIVE_XTS_AES_KEY_UPDATE_REG, 1);
 #endif
diff --git a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h
index 9f2e152698..6b84ef3c26 100644
--- a/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h
+++ b/components/hal/esp32p4/include/hal/mspi_timing_tuning_ll.h
@@ -18,6 +18,7 @@
 #include "soc/soc.h"
 #include "soc/iomux_mspi_pin_reg.h"
 #include "soc/iomux_mspi_pin_struct.h"
+#include "soc/hp_sys_clkrst_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -71,6 +72,20 @@ typedef enum {
     MSPI_LL_PIN_MAX,
 } mspi_ll_pin_t;
 
+/**
+ * Reset the MSPI clock
+ */
+__attribute__((always_inline))
+static inline void _mspi_timing_ll_reset_mspi(void)
+{
+   REG_SET_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
+   REG_CLR_BIT(HP_SYS_CLKRST_HP_RST_EN0_REG, HP_SYS_CLKRST_REG_RST_EN_MSPI_AXI);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define mspi_timing_ll_reset_mspi(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _mspi_timing_ll_reset_mspi(__VA_ARGS__)
+
 /**
  * Set all MSPI DQS phase
  *