Merge branch 'feature/support_esp32c2_test_pm_v5.0' into 'release/v5.0'

gpio, ledc, pm: several MR updates backport to v5.0

See merge request espressif/esp-idf!19706
pull/9723/head
morris 2022-08-23 13:48:33 +08:00
commit d609f5fb35
13 zmienionych plików z 137 dodań i 21 usunięć

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@ -450,8 +450,14 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
#endif // SOC_TIMER_GROUP_SUPPORT_APB #endif // SOC_TIMER_GROUP_SUPPORT_APB
#if SOC_TIMER_GROUP_SUPPORT_PLL_F40M #if SOC_TIMER_GROUP_SUPPORT_PLL_F40M
case GPTIMER_CLK_SRC_PLL_F40M: case GPTIMER_CLK_SRC_PLL_F40M:
// TODO: decide which kind of PM lock we should use for such clock
counter_src_hz = 40 * 1000 * 1000; counter_src_hz = 40 * 1000 * 1000;
#if CONFIG_PM_ENABLE
sprintf(timer->pm_lock_name, "gptimer_%d_%d", timer->group->group_id, timer_id); // e.g. gptimer_0_0
// PLL_F40M will be turned off when DFS switches CPU clock source to XTAL
ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, timer->pm_lock_name, &timer->pm_lock);
ESP_RETURN_ON_ERROR(ret, TAG, "create APB_FREQ_MAX lock failed");
ESP_LOGD(TAG, "install APB_FREQ_MAX lock for timer (%d,%d)", timer->group->group_id, timer_id);
#endif
break; break;
#endif // SOC_TIMER_GROUP_SUPPORT_PLL_F40M #endif // SOC_TIMER_GROUP_SUPPORT_PLL_F40M
#if SOC_TIMER_GROUP_SUPPORT_AHB #if SOC_TIMER_GROUP_SUPPORT_AHB

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@ -276,7 +276,6 @@ esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
ledc_hal_timer_rst(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); ledc_hal_timer_rst(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel);
ledc_ls_timer_update(speed_mode, timer_sel);
portEXIT_CRITICAL(&ledc_spinlock); portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK; return ESP_OK;
} }
@ -288,7 +287,6 @@ esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
ledc_hal_timer_pause(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); ledc_hal_timer_pause(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel);
ledc_ls_timer_update(speed_mode, timer_sel);
portEXIT_CRITICAL(&ledc_spinlock); portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK; return ESP_OK;
} }
@ -300,7 +298,6 @@ esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, ledc_timer_t timer_sel)
LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE); LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
portENTER_CRITICAL(&ledc_spinlock); portENTER_CRITICAL(&ledc_spinlock);
ledc_hal_timer_resume(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel); ledc_hal_timer_resume(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel);
ledc_ls_timer_update(speed_mode, timer_sel);
portEXIT_CRITICAL(&ledc_spinlock); portEXIT_CRITICAL(&ledc_spinlock);
return ESP_OK; return ESP_OK;
} }
@ -581,9 +578,6 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n
/* The divisor is correct, we can write in the hardware. */ /* The divisor is correct, we can write in the hardware. */
ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src); ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src);
/* Reset the timer. */
ledc_timer_rst(speed_mode, timer_num);
return ESP_OK; return ESP_OK;
error: error:
@ -618,7 +612,12 @@ esp_err_t ledc_timer_config(const ledc_timer_config_t *timer_conf)
ledc_hal_init(&(p_ledc_obj[speed_mode]->ledc_hal), speed_mode); ledc_hal_init(&(p_ledc_obj[speed_mode]->ledc_hal), speed_mode);
} }
return ledc_set_timer_div(speed_mode, timer_num, timer_conf->clk_cfg, freq_hz, duty_resolution); esp_err_t ret = ledc_set_timer_div(speed_mode, timer_num, timer_conf->clk_cfg, freq_hz, duty_resolution);
if (ret == ESP_OK) {
/* Reset the timer. */
ledc_timer_rst(speed_mode, timer_num);
}
return ret;
} }
esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel) esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc_channel)

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@ -611,6 +611,7 @@ TEST_CASE("LEDC timer pause and resume", "[ledc]")
printf("reset ledc timer\n"); printf("reset ledc timer\n");
TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0)); TEST_ESP_OK(ledc_timer_rst(test_speed_mode, LEDC_TIMER_0));
vTaskDelay(100 / portTICK_PERIOD_MS); vTaskDelay(100 / portTICK_PERIOD_MS);
count = wave_count(1000);
TEST_ASSERT_UINT32_WITHIN(5, count, 5000); TEST_ASSERT_UINT32_WITHIN(5, count, 5000);
tear_testbench(); tear_testbench();
} }

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@ -8,6 +8,7 @@
#include <stdbool.h> #include <stdbool.h>
#include "esp_log.h" #include "esp_log.h"
#include "hal/usb_serial_jtag_ll.h" #include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_phy_ll.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/semphr.h" #include "freertos/semphr.h"
#include "freertos/ringbuf.h" #include "freertos/ringbuf.h"
@ -112,6 +113,9 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
goto _exit; goto _exit;
} }
// Configure PHY
usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY| usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|
USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT); USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY| usb_serial_jtag_ll_ena_intr_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|

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@ -39,8 +39,6 @@ TEST_CASE("Can dump power management lock stats", "[pm]")
#ifdef CONFIG_PM_ENABLE #ifdef CONFIG_PM_ENABLE
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
//IDF-5053
static void switch_freq(int mhz) static void switch_freq(int mhz)
{ {
int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ; int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ;
@ -69,8 +67,13 @@ static void switch_freq(int mhz)
} }
} }
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 #if CONFIG_IDF_TARGET_ESP32C3
static const int test_freqs[] = {40, 160, 80, 40, 80, 10, 80, 20, 40}; static const int test_freqs[] = {40, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, 40, 80, 10, 80, 20, 40};
#elif CONFIG_IDF_TARGET_ESP32C2
static const int test_freqs[] = {CONFIG_XTAL_FREQ, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 80, CONFIG_XTAL_FREQ, 80,
CONFIG_XTAL_FREQ / 2, CONFIG_XTAL_FREQ}; // C2 xtal has 40/26MHz option
#elif CONFIG_IDF_TARGET_ESP32H2
static const int test_freqs[] = {32, CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, 32} // TODO: IDF-3786
#else #else
static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40}; static const int test_freqs[] = {240, 40, 160, 240, 80, 40, 240, 40, 80, 10, 80, 20, 40};
#endif #endif
@ -86,7 +89,6 @@ TEST_CASE("Can switch frequency using esp_pm_configure", "[pm]")
switch_freq(orig_freq_mhz); switch_freq(orig_freq_mhz);
} }
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
#if CONFIG_FREERTOS_USE_TICKLESS_IDLE #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
@ -138,8 +140,6 @@ static void light_sleep_disable(void)
ESP_ERROR_CHECK( esp_pm_configure(&pm_config) ); ESP_ERROR_CHECK( esp_pm_configure(&pm_config) );
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
//IDF-5053
TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]") TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
{ {
gptimer_handle_t gptimer = NULL; gptimer_handle_t gptimer = NULL;
@ -159,7 +159,9 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
// so we manually release the lock here // so we manually release the lock here
esp_pm_lock_handle_t gptimer_pm_lock; esp_pm_lock_handle_t gptimer_pm_lock;
TEST_ESP_OK(gptimer_get_pm_lock(gptimer, &gptimer_pm_lock)); TEST_ESP_OK(gptimer_get_pm_lock(gptimer, &gptimer_pm_lock));
TEST_ESP_OK(esp_pm_lock_release(gptimer_pm_lock)); if (gptimer_pm_lock) {
TEST_ESP_OK(esp_pm_lock_release(gptimer_pm_lock));
}
light_sleep_enable(); light_sleep_enable();
@ -185,17 +187,16 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
} }
light_sleep_disable(); light_sleep_disable();
TEST_ESP_OK(esp_pm_lock_acquire(gptimer_pm_lock)); if (gptimer_pm_lock) {
TEST_ESP_OK(esp_pm_lock_acquire(gptimer_pm_lock));
}
TEST_ESP_OK(gptimer_stop(gptimer)); TEST_ESP_OK(gptimer_stop(gptimer));
TEST_ESP_OK(gptimer_disable(gptimer)); TEST_ESP_OK(gptimer_disable(gptimer));
TEST_ESP_OK(gptimer_del_timer(gptimer)); TEST_ESP_OK(gptimer_del_timer(gptimer));
} }
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
#if CONFIG_ULP_COPROC_TYPE_FSM #if CONFIG_ULP_COPROC_TYPE_FSM
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
#if !DISABLED_FOR_TARGETS(ESP32C3)
// No ULP on C3
// Fix failure on ESP32 when running alone; passes when the previous test is run before this one // Fix failure on ESP32 when running alone; passes when the previous test is run before this one
TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]") TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
@ -264,7 +265,6 @@ TEST_CASE("Can wake up from automatic light sleep by GPIO", "[pm][ignore]")
light_sleep_disable(); light_sleep_disable();
} }
#endif //!DISABLED_FOR_TARGETS(ESP32C3)
#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3) #endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
#endif //CONFIG_ULP_COPROC_TYPE_FSM #endif //CONFIG_ULP_COPROC_TYPE_FSM

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@ -51,6 +51,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/ */
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{ {
// The pull-up value of the USB pins are controlled by the pins pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
if (gpio_num == USB_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
} }

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@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configures the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
}
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,34 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configures the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
}
#ifdef __cplusplus
}
#endif

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@ -51,6 +51,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/ */
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{ {
// The pull-up value of the USB pins are controlled by the pins pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
if (gpio_num == USB_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
} }

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@ -51,6 +51,12 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/ */
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{ {
// The pull-up value of the USB pins are controlled by the pins pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
if (gpio_num == USB_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
} }

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@ -52,6 +52,14 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, uint32_t gpio_num)
*/ */
static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num) static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, uint32_t gpio_num)
{ {
// The pull-up value of the USB pins are controlled by the pins pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
if (gpio_num == USB_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU); REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
} }

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@ -17,6 +17,8 @@
#include "soc/rtc_io_struct.h" #include "soc/rtc_io_struct.h"
#include "hal/rtc_io_types.h" #include "hal/rtc_io_types.h"
#include "hal/gpio_types.h" #include "hal/gpio_types.h"
#include "soc/io_mux_reg.h"
#include "soc/usb_serial_jtag_reg.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -181,6 +183,14 @@ static inline void rtcio_ll_pullup_enable(int rtcio_num)
*/ */
static inline void rtcio_ll_pullup_disable(int rtcio_num) static inline void rtcio_ll_pullup_disable(int rtcio_num)
{ {
// The pull-up value of the USB pins are controlled by the pins pull-up value together with USB pull-up value
// USB DP pin is default to PU enabled
// Note that from esp32s3 ECO1, USB_EXCHG_PINS feature has been supported. If this efuse is burnt, the gpio pin
// which should be checked is USB_DM_GPIO_NUM instead.
if (rtcio_num == USB_DP_GPIO_NUM) {
SET_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_PAD_PULL_OVERRIDE);
CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_DP_PULLUP);
}
if (rtc_io_desc[rtcio_num].pullup) { if (rtc_io_desc[rtcio_num].pullup) {
CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup); CLEAR_PERI_REG_MASK(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].pullup);
} }

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@ -59,6 +59,8 @@ static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
hw->conf0.phy_sel = 0; hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1) // Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0; hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function // Enable USB pad function
hw->conf0.usb_pad_enable = 1; hw->conf0.usb_pad_enable = 1;
// phy_sel is controlled by the following register value // phy_sel is controlled by the following register value