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Merge branch 'bugfix/further_fix_for_mspi_current_leakage' into 'master' 

system/sleep: further fix spi flash/ram current leakage

Closes IDF-4720

See merge request espressif/esp-idf!18566
pull/9446/head
Jiang Jiang Jian 2022-07-21 19:14:26 +08:00
rodzic 097e64f8c7 66395a5c00
commit cf5b097c88
15 zmienionych plików z 242 dodań i 77 usunięć
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11
components/bootloader_support/include/bootloader_common.h
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@ -13,7 +13,7 @@
extern "C" {
#endif
/// Type of hold a GPIO in low state
// Type of hold a GPIO in low state
typedef enum {
GPIO_LONG_HOLD = 1, /*!< The long hold GPIO */
GPIO_SHORT_HOLD = -1, /*!< The short hold GPIO */
@ -106,15 +106,6 @@ bool bootloader_common_label_search(const char *list, char *label);
*/
void bootloader_configure_spi_pins(int drv);
/**
* @brief Get flash CS IO
*
* Can be determined by eFuse values, or the default value
*
* @return Flash CS IO
*/
uint8_t bootloader_flash_get_cs_io(void);
/**
* @brief Calculates a sha-256 for a given partition or returns a appended digest.
*

18
components/bootloader_support/src/bootloader_common.c
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@ -13,7 +13,6 @@
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "esp_rom_efuse.h"
#include "esp_flash_partitions.h"
#include "bootloader_flash_priv.h"
#include "bootloader_common.h"
@ -21,7 +20,6 @@
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_reg.h"
#include "soc/soc_caps.h"
#include "hal/gpio_ll.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
@ -188,19 +186,3 @@ void bootloader_common_vddsdio_configure(void)
}
#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
}
uint8_t bootloader_flash_get_cs_io(void)
{
#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
uint8_t cs_io;
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
cs_io = SPI_CS0_GPIO_NUM;
} else {
cs_io = (spiconfig >> 18) & 0x3f;
}
return cs_io;
#else
return SPI_CS0_GPIO_NUM;
#endif
}

21
components/esp_hw_support/Kconfig
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@ -24,13 +24,15 @@ menu "Hardware Settings"
config ESP_SLEEP_POWER_DOWN_FLASH
bool "Power down flash in light sleep when there is no SPIRAM"
depends on !SPIRAM
default y
default n
help
If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
more time when chip wakes up. Can only be enabled if there is no SPIRAM configured.
This option will in fact consider VDD_SDIO auto power value (ESP_PD_OPTION_AUTO) as OFF. Also, it is
possible to force a power domain to stay ON during light sleep by using esp_sleep_pd_config()
function.
This option will power down flash under a strict but relatively safe condition. Also, it is possible to
power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO
to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer
`ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.
config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
bool
@ -58,6 +60,7 @@ menu "Hardware Settings"
config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
bool "PSRAM leakage current workaround in light sleep"
depends on SPIRAM
default y
help
When the CS pin of SPIRAM is not pulled up, the sleep current will
increase during light sleep. If the CS pin of SPIRAM has an external
@ -66,12 +69,22 @@ menu "Hardware Settings"
config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
bool "Flash leakage current workaround in light sleep"
default y
help
When the CS pin of Flash is not pulled up, the sleep current will
increase during light sleep. If the CS pin of Flash has an external
pull-up, you do not need to select this option, otherwise, you
should enable this option.
config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
bool "All pins of mspi need pull up"
depends on ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
help
To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin
during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up
all pins. It depends on the SPI Flash/RAM chip used.
config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY
int "Extra delay in deep sleep wake stub (in us)"
depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3

37
components/esp_hw_support/sleep_gpio.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -19,11 +19,7 @@
#include "driver/gpio.h"
#include "esp_private/gpio.h"
#include "esp_private/sleep_gpio.h"
#include "bootloader_common.h"
#if CONFIG_SPIRAM
#include "esp_private/esp_psram_io.h"
#endif
#include "esp_private/spi_flash_os.h"
static const char *TAG = "sleep";
@ -51,24 +47,41 @@ IRAM_ATTR void gpio_sleep_mode_config_unapply(void)
void esp_sleep_config_gpio_isolate(void)
{
ESP_LOGI(TAG, "Configure to isolate all GPIO pins in sleep state");
ESP_EARLY_LOGI(TAG, "Configure to isolate all GPIO pins in sleep state");
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
if (GPIO_IS_VALID_GPIO(gpio_num)) {
gpio_sleep_set_direction(gpio_num, GPIO_MODE_DISABLE);
gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
}
}
#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
gpio_sleep_set_pull_mode(esp_psram_io_get_cs_io(), GPIO_PULLUP_ONLY);
#endif
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CS1), GPIO_PULLUP_ONLY);
#endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
gpio_sleep_set_pull_mode(bootloader_flash_get_cs_io(), GPIO_PULLUP_ONLY);
#endif
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CS0), GPIO_PULLUP_ONLY);
#endif // CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
#if CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CLK), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_Q), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_HD), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_WP), GPIO_PULLUP_ONLY);
#if CONFIG_SPIRAM_MODE_OCT || CONFIG_ESPTOOLPY_FLASHMODE_OPI
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_DQS), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D4), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D5), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D6), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D7), GPIO_PULLUP_ONLY);
#endif // CONFIG_SPIRAM_MODE_OCT || CONFIG_ESPTOOLPY_FLASHMODE_OPI
#endif // CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU
}
void esp_sleep_enable_gpio_switch(bool enable)
{
ESP_LOGI(TAG, "%s automatic switching of GPIO sleep configuration", enable ? "Enable" : "Disable");
ESP_EARLY_LOGI(TAG, "%s automatic switching of GPIO sleep configuration", enable ? "Enable" : "Disable");
for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
if (GPIO_IS_VALID_GPIO(gpio_num)) {
if (enable) {

4
components/esp_rom/CMakeLists.txt
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@ -11,6 +11,7 @@ if(target STREQUAL "linux")
"${target}/esp_rom_crc.c"
"${target}/esp_rom_md5.c"
"${target}/esp_rom_efuse.c")
list(APPEND include_dirs "${IDF_PATH}/tools/mocks/soc/include")
else()
list(APPEND include_dirs "${target}")
list(APPEND sources "patches/esp_rom_crc.c"
@ -18,7 +19,8 @@ else()
"patches/esp_rom_uart.c"
"patches/esp_rom_spiflash.c"
"patches/esp_rom_tjpgd.c"
"patches/esp_rom_regi2c.c")
"patches/esp_rom_regi2c.c"
"patches/esp_rom_efuse.c")
list(APPEND private_required_comp soc hal)
endif()

1
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
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@ -16,6 +16,7 @@ PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
PROVIDE ( esp_rom_efuse_mac_address_crc8 = esp_crc8 );
PROVIDE ( esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig );
PROVIDE ( esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad );
PROVIDE ( esp_rom_efuse_get_opiconfig = ets_efuse_get_opiconfig );
PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
PROVIDE ( esp_rom_uart_flush_tx = uart_tx_flush );

31
components/esp_rom/include/esp_rom_efuse.h
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@ -1,16 +1,8 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@ -20,6 +12,7 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI (0)
#define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1)
@ -56,6 +49,18 @@ uint32_t esp_rom_efuse_get_flash_gpio_info(void);
*/
uint32_t esp_rom_efuse_get_flash_wp_gpio(void);
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
/**
* @brief Read opi flash pads configuration from Efuse
*
* @return
* - 0 for default SPI pins.
* - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
* DQS, D4, D5, D6, D7 accordingly.
*/
uint32_t esp_rom_efuse_get_opiconfig(void);
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
/**
* @brief Read eFuse to check whether secure boot has been enabled or not
*

25
components/esp_rom/linux/esp_rom_efuse.c
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@ -1,16 +1,8 @@
// Copyright 2021 Espressif Systems (Shanghai) CO LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_rom_efuse.h"
@ -49,6 +41,13 @@ uint32_t esp_rom_efuse_get_flash_wp_gpio(void)
return 0;
}
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
uint32_t esp_rom_efuse_get_opiconfig(void)
{
return 0;
}
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
bool esp_rom_efuse_is_secure_boot_enabled(void)
{
return false;

31
components/esp_rom/patches/esp_rom_efuse.c 100644
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@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/efuse_reg.h"
#if CONFIG_IDF_TARGET_ESP32S3
/**
* Since rom of esp32s3 does not export function ets_efuse_get_opiconfig,
* patch this function here.
*/
uint32_t esp_rom_efuse_get_opiconfig(void)
{
uint64_t spiconfig1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_2_REG, EFUSE_SPI_PAD_CONF_1);
uint64_t spiconfig2 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_SPI_PAD_CONF_2);
uint64_t opiconfig = (spiconfig2 << 12) | (spiconfig1 >> 20);
if (opiconfig == 0 || opiconfig == 0x3fffffffllu) {
return 0;
}
// （MSB）EFUSE_SPI_PAD_CONF_2(18bit) + EFUSE_SPI_PAD_CONF_1(32bit) + EFUSE_SPI_PAD_CONF_0(16bit) (LSB)
// [36:41] -- DQS
// [42:47] -- D4
// [48:53] -- D5
// [54:59] -- D6
// [60:65] -- D7
return opiconfig & 0x3fffffff;
}
#endif

91
components/spi_flash/flash_ops.c
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@ -15,6 +15,7 @@
#include <freertos/semphr.h>
#include <soc/soc.h>
#include <soc/soc_memory_layout.h>
#include "soc/io_mux_reg.h"
#include "sdkconfig.h"
#include "esp_attr.h"
#include "spi_flash_mmap.h"
@ -45,7 +46,12 @@
#include "esp_flash.h"
#include "esp_attr.h"
#include "bootloader_flash.h"
#include "bootloader_flash_config.h"
#include "esp_compiler.h"
#include "esp_rom_efuse.h"
#if CONFIG_SPIRAM
#include "esp_private/esp_psram_io.h"
#endif
/* bytes erased by SPIEraseBlock() ROM function */
#define BLOCK_ERASE_SIZE 65536
@ -223,3 +229,88 @@ void IRAM_ATTR spi_flash_set_vendor_required_regs(void)
#endif // CONFIG_ESPTOOLPY_OCT_FLASH
}
#endif
static const uint8_t s_mspi_io_num_default[] = {
SPI_CLK_GPIO_NUM,
SPI_Q_GPIO_NUM,
SPI_D_GPIO_NUM,
SPI_CS0_GPIO_NUM,
SPI_HD_GPIO_NUM,
SPI_WP_GPIO_NUM,
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
SPI_DQS_GPIO_NUM,
SPI_D4_GPIO_NUM,
SPI_D5_GPIO_NUM,
SPI_D6_GPIO_NUM,
SPI_D7_GPIO_NUM
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
};
uint8_t esp_mspi_get_io(esp_mspi_io_t io)
{
#if CONFIG_SPIRAM
if (io == ESP_MSPI_IO_CS1) {
return esp_psram_io_get_cs_io();
}
#endif
assert(io >= ESP_MSPI_IO_CLK);
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
assert(io <= ESP_MSPI_IO_D7);
#else
assert(io <= ESP_MSPI_IO_WP);
#endif
#if SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
uint8_t mspi_io = 0;
uint32_t spiconfig = 0;
if (io == ESP_MSPI_IO_WP) {
/**
* wp pad is a bit special:
* 1. since 32's efuse does not have enough bits for wp pad, so wp pad config put in flash bin header
* 2. rom code take 0x3f as invalid wp pad num, but take 0 as other invalid mspi pads num
*/
#if CONFIG_IDF_TARGET_ESP32
return bootloader_flash_get_wp_pin();
#else
spiconfig = esp_rom_efuse_get_flash_wp_gpio();
return (spiconfig == 0x3f) ? s_mspi_io_num_default[io] : spiconfig & 0x3f;
#endif
}
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
spiconfig = (io < ESP_MSPI_IO_WP) ? esp_rom_efuse_get_flash_gpio_info() : esp_rom_efuse_get_opiconfig();
#else
spiconfig = esp_rom_efuse_get_flash_gpio_info();
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
mspi_io = s_mspi_io_num_default[io];
} else if (io < ESP_MSPI_IO_WP) {
/**
* [0 : 5] -- CLK
* [6 :11] -- Q(D1)
* [12:17] -- D(D0)
* [18:23] -- CS
* [24:29] -- HD(D3)
*/
mspi_io = (spiconfig >> io * 6) & 0x3f;
}
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
else {
/**
* [0 : 5] -- DQS
* [6 :11] -- D4
* [12:17] -- D5
* [18:23] -- D6
* [24:29] -- D7
*/
mspi_io = (spiconfig >> (io - ESP_MSPI_IO_DQS) * 6) & 0x3f;
}
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
return mspi_io;
#else // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
return s_mspi_io_num_default[io];
#endif // SOC_SPI_MEM_SUPPORT_CONFIG_GPIO_BY_EFUSE
}

30
components/spi_flash/include/esp_private/spi_flash_os.h
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@ -27,11 +27,32 @@
#include "esp_flash.h"
#include "hal/spi_flash_hal.h"
#include "spi_flash_override.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
// Type of MSPI IO
typedef enum {
ESP_MSPI_IO_CLK = 0,
ESP_MSPI_IO_Q,
ESP_MSPI_IO_D,
ESP_MSPI_IO_CS0, /* cs for spi flash */
ESP_MSPI_IO_HD,
ESP_MSPI_IO_WP,
#if SOC_SPI_MEM_SUPPORT_OPI_MODE
ESP_MSPI_IO_DQS,
ESP_MSPI_IO_D4,
ESP_MSPI_IO_D5,
ESP_MSPI_IO_D6,
ESP_MSPI_IO_D7,
#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
#if CONFIG_SPIRAM
ESP_MSPI_IO_CS1 /* cs for spi ram */
#endif
} esp_mspi_io_t;
/**
* @brief To setup Flash chip
*/
@ -73,6 +94,15 @@ void spi_timing_psram_tuning(void);
*/
void esp_mspi_pin_init(void);
/**
* @brief Get the number of the GPIO corresponding to the given MSPI io
*
* @param[in] io MSPI io
*
* @return MSPI IO number
*/
uint8_t esp_mspi_get_io(esp_mspi_io_t io);
/**
* @brief Set SPI1 registers to make ROM functions work
* @note This function is used for setting SPI1 registers to the state that ROM SPI functions work

1
components/spi_flash/sim/Makefile.files
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@ -6,6 +6,7 @@ SOURCE_FILES := \
partition.c \
../spi_flash/partition_target.c \
flash_ops.c \
../esp_rom/linux/esp_rom_efuse.c \
) \
INCLUDE_DIRS := \

8
docs/en/api-reference/system/sleep_modes.rst
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@ -171,7 +171,7 @@ By default, :cpp:func:`esp_deep_sleep_start` and :cpp:func:`esp_light_sleep_star
Power-down of Flash
-------------------
By default, to avoid potential issues, :cpp:func:`esp_deep_sleep_start` and :cpp:func:`esp_light_sleep_start` functions will **not** power down flash. To be more specific, it takes time to power down the flash and during this period the system may be woken up, which then actually powers up the flash before this flash could be powered down completely. As a result, there is a chance that the flash may not work properly.
By default, to avoid potential issues, :cpp:func:`esp_light_sleep_start` function will **not** power down flash. To be more specific, it takes time to power down the flash and during this period the system may be woken up, which then actually powers up the flash before this flash could be powered down completely. As a result, there is a chance that the flash may not work properly.
So, in theory, it's ok if you only wake up the system after the flash is completely powered down. However, in reality, the flash power-down period can be hard to predict (for example, this period can be much longer when you add filter capacitors to the flash's power supply circuit) and uncontrollable (for example, the asynchronous wake-up signals make the actual sleep time uncontrollable).
@ -192,7 +192,11 @@ However, for those who have fully understood the risk and are still willing to p
- Calling ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` powers down flash when the RTC timer is not enabled as a wakeup source **or** the sleep time is longer than the flash power-down period.
.. note::
ESP-IDF does not provide any mechanism that can power down the flash in all conditions.
.. list::
- ESP-IDF does not provide any mechanism that can power down the flash in all conditions when light sleep.
- :cpp:func:`esp_deep_sleep_start` function will force power down flash regardless of user configuration.
Entering Light-sleep
--------------------

8
docs/zh_CN/api-reference/system/sleep_modes.rst
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@ -171,7 +171,7 @@ RTC 外设和内存断电
Flash 断电
----------
默认情况下，调用函数 :cpp:func:`esp_deep_sleep_start` 和 :cpp:func:`esp_light_sleep_start` 后， **不会** 断电 flash。在 sleep 过程中断电 flash 存在风险。因为 flash 断电需要时间，但是在此期间，系统有可能被唤醒。此时 flash 重新被上电，断电尚未完成又重新上电的硬件行为有概率导致 flash 不能正常工作。如果用户为 flash 供电电路添加了滤波电容，断电所需时间可能会更长。此外，即使可以预知 flash 彻底断电所需的时间，有时也不能通过设置足够长的睡眠时间来确保 flash 断电的安全（比如，突发的异步唤醒源会使得实际的睡眠时间不可控）。
默认情况下，调用函数 :cpp:func:`esp_light_sleep_start` 后， **不会** 断电 flash。在 sleep 过程中断电 flash 存在风险。因为 flash 断电需要时间，但是在此期间，系统有可能被唤醒。此时 flash 重新被上电，断电尚未完成又重新上电的硬件行为有概率导致 flash 不能正常工作。如果用户为 flash 供电电路添加了滤波电容，断电所需时间可能会更长。此外，即使可以预知 flash 彻底断电所需的时间，有时也不能通过设置足够长的睡眠时间来确保 flash 断电的安全（比如，突发的异步唤醒源会使得实际的睡眠时间不可控）。
.. warning::
如果在 flash 的供电电路上添加了滤波电容，那么应当尽一切可能避免 flash 断电。
@ -190,7 +190,11 @@ Flash 断电
- 调用函数 ``esp_sleep_pd_config(ESP_PD_DOMAIN_VDDSDIO, ESP_PD_OPTION_OFF)`` 将使 ESP-IDF 以一个宽松的条件来断电 flash。宽松的条件具体指的是 RTC timer 唤醒源未被使能 **或** 睡眠时间比 flash 彻底断电所需时间更长。
.. note::
ESP-IDF 并未提供保证 flash 一定会被断电的机制。
.. list::
- Light sleep 时，ESP-IDF 并未提供保证 flash 一定会被断电的机制。
- 不管用户的配置如何，函数 :cpp:func:`esp_deep_sleep_start` 都会强制断电 flash。
进入 Light-sleep 模式
-------------------------

2
tools/ci/check_copyright_ignore.txt
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@ -619,12 +619,10 @@ components/esp_rom/include/esp32s3/rom/usb/usb_dfu.h
components/esp_rom/include/esp32s3/rom/usb/usb_os_glue.h
components/esp_rom/include/esp32s3/rom/usb/usb_persist.h
components/esp_rom/include/esp_rom_crc.h
components/esp_rom/include/esp_rom_efuse.h
components/esp_rom/include/esp_rom_gpio.h
components/esp_rom/include/esp_rom_uart.h
components/esp_rom/include/linux/soc/reset_reasons.h
components/esp_rom/linux/esp_rom_crc.c
components/esp_rom/linux/esp_rom_efuse.c
components/esp_rom/linux/esp_rom_md5.c
components/esp_rom/linux/esp_rom_sys.c
components/esp_rom/patches/esp_rom_crc.c