From ce351790a8a4eb86fa82ce847bd4eac328613955 Mon Sep 17 00:00:00 2001 From: Darian Leung Date: Tue, 14 Nov 2023 20:42:25 +0800 Subject: [PATCH] refactor(hal/usb_dwc): Add DWC OTG configuration values This commit adds a subset of the DWC OTG configuration values to the 'usb_dwc_ll.h' file. Only relevant configuration values have been added. Some DWC OTG releated constants have also been moved from 'usb_dwc_hal.h' to 'usb_dwc_ll.h' and renamed. --- components/hal/include/hal/usb_dwc_hal.h | 18 +++++++------- components/hal/include/hal/usb_dwc_ll.h | 30 +++++++++++++++++++++++- components/hal/usb_dwc_hal.c | 10 ++++---- components/usb/hcd_dwc.c | 10 ++++---- 4 files changed, 47 insertions(+), 21 deletions(-) diff --git a/components/hal/include/hal/usb_dwc_hal.h b/components/hal/include/hal/usb_dwc_hal.h index d52e882cb9..4369ff3ac0 100644 --- a/components/hal/include/hal/usb_dwc_hal.h +++ b/components/hal/include/hal/usb_dwc_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,15 +22,11 @@ NOTE: Thread safety is the responsibility fo the HAL user. All USB Host HAL #include "hal/usb_types_private.h" #include "hal/assert.h" +#if SOC_USB_OTG_SUPPORTED + // ------------------------------------------------ Macros and Types --------------------------------------------------- -// ------------------ Constants/Configs -------------------- - -#define USB_DWC_HAL_DMA_MEM_ALIGN 512 -#define USB_DWC_HAL_FRAME_LIST_MEM_ALIGN 512 //The frame list needs to be 512 bytes aligned (contrary to the databook) -#define USB_DWC_HAL_NUM_CHAN 8 -#define USB_DWC_HAL_XFER_DESC_SIZE (sizeof(usb_dwc_ll_dma_qtd_t)) -#define USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES 200 //Although we have a 256 lines, only 200 lines are usuable due to EPINFO_CTL +// ----------------------- Configs ------------------------- /** * @brief FIFO size configuration structure @@ -168,7 +164,7 @@ typedef struct { struct { int num_allocd; /**< Number of channels currently allocated */ uint32_t chan_pend_intrs_msk; /**< Bit mask of channels with pending interrupts */ - usb_dwc_hal_chan_t *hdls[USB_DWC_HAL_NUM_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ + usb_dwc_hal_chan_t *hdls[USB_DWC_NUM_HOST_CHAN]; /**< Handles of each channel. Set to NULL if channel has not been allocated */ } channels; } usb_dwc_hal_context_t; @@ -229,7 +225,7 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal); * may be situations where this function may need to be called again to resize the FIFOs. If resizing FIFOs dynamically, * it is the user's responsibility to ensure there are no active channels when this function is called. * - * @note The totol size of all the FIFOs must be less than or equal to USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES + * @note The totol size of all the FIFOs must be less than or equal to USB_DWC_FIFO_TOTAL_USABLE_LINES * @note After a port reset, the FIFO size registers will reset to their default values, so this function must be called * again post reset. * @@ -785,6 +781,8 @@ usb_dwc_hal_chan_t *usb_dwc_hal_get_chan_pending_intr(usb_dwc_hal_context_t *hal */ usb_dwc_hal_chan_event_t usb_dwc_hal_chan_decode_intr(usb_dwc_hal_chan_t *chan_obj); +#endif // SOC_USB_OTG_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/usb_dwc_ll.h b/components/hal/include/hal/usb_dwc_ll.h index 3bbaeca4c2..385e93f444 100644 --- a/components/hal/include/hal/usb_dwc_ll.h +++ b/components/hal/include/hal/usb_dwc_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,6 +17,34 @@ extern "C" { #include "hal/misc.h" +/* ----------------------------------------------------------------------------- +--------------------------------- DWC Constants -------------------------------- +----------------------------------------------------------------------------- */ + +#define USB_DWC_QTD_LIST_MEM_ALIGN 512 +#define USB_DWC_FRAME_LIST_MEM_ALIGN 512 // The frame list needs to be 512 bytes aligned (contrary to the databook) +/* +Although we have a 256 lines, only 200 lines are useable due to EPINFO_CTL. +Todo: Check sizes again and express this macro in terms of DWC config options (IDF-7384) +*/ +#define USB_DWC_FIFO_TOTAL_USABLE_LINES 200 + +/* ----------------------------------------------------------------------------- +------------------------------ DWC Configuration ------------------------------- +----------------------------------------------------------------------------- */ + +/* + * List of relevant DWC configurations. See DWC OTG databook Chapter 3 for more + * details. + */ +#define USB_DWC_FSPHY_INTERFACE 1 +#define USB_DWC_NUM_EPS 6 +#define USB_DWC_NUM_IN_EPS 5 // Todo: Add check for when number of IN channels exceeds limit (IDF-8556) +#define USB_DWC_NUM_HOST_CHAN 8 +#define USB_DWC_DFIFO_DEPTH 256 +#define USB_DWC_RX_DFIFO_DEPTH 256 +#define USB_DWC_TX_DFIFO_DEPTH 256 // Same value applies to HNPERIO, NPERIO, HPERIO, and DINEP + /* ----------------------------------------------------------------------------- ------------------------------- Global Registers ------------------------------- ----------------------------------------------------------------------------- */ diff --git a/components/hal/usb_dwc_hal.c b/components/hal/usb_dwc_hal.c index 58fc66f443..31a2695c5d 100644 --- a/components/hal/usb_dwc_hal.c +++ b/components/hal/usb_dwc_hal.c @@ -159,14 +159,14 @@ void usb_dwc_hal_core_soft_reset(usb_dwc_hal_context_t *hal) hal->flags.val = 0; hal->channels.num_allocd = 0; hal->channels.chan_pend_intrs_msk = 0; - memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_HAL_NUM_CHAN); + memset(hal->channels.hdls, 0, sizeof(usb_dwc_hal_chan_t *) * USB_DWC_NUM_HOST_CHAN); } void usb_dwc_hal_set_fifo_size(usb_dwc_hal_context_t *hal, const usb_dwc_hal_fifo_config_t *fifo_config) { - HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES); + HAL_ASSERT((fifo_config->rx_fifo_lines + fifo_config->nptx_fifo_lines + fifo_config->ptx_fifo_lines) <= USB_DWC_FIFO_TOTAL_USABLE_LINES); //Check that none of the channels are active - for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { + for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) { if (hal->channels.hdls[i] != NULL) { HAL_ASSERT(!hal->channels.hdls[i]->flags.active); } @@ -208,11 +208,11 @@ bool usb_dwc_hal_chan_alloc(usb_dwc_hal_context_t *hal, usb_dwc_hal_chan_t *chan { HAL_ASSERT(hal->flags.fifo_sizes_set); //FIFO sizes should be set befor attempting to allocate a channel //Attempt to allocate channel - if (hal->channels.num_allocd == USB_DWC_HAL_NUM_CHAN) { + if (hal->channels.num_allocd == USB_DWC_NUM_HOST_CHAN) { return false; //Out of free channels } int chan_idx = -1; - for (int i = 0; i < USB_DWC_HAL_NUM_CHAN; i++) { + for (int i = 0; i < USB_DWC_NUM_HOST_CHAN; i++) { if (hal->channels.hdls[i] == NULL) { hal->channels.hdls[i] = chan_obj; chan_idx = i; diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index d38d775fc4..86e785eb57 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -53,7 +53,7 @@ typedef struct { * * RXFIFO * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 48 - 48 = 104 * - Worst case can accommodate two packets of 204 bytes, or one packet of 408 * NPTXFIFO * - Recommended: (LPS/4) * 2 @@ -81,7 +81,7 @@ const fifo_mps_limits_t mps_limits_default = { * * RXFIFO * - Recommended: ((LPS/4) * 2) + 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 32 - 16 = 152 * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes * NPTXFIFO * - Recommended: (LPS/4) * 2 @@ -117,7 +117,7 @@ const fifo_mps_limits_t mps_limits_bias_rx = { * - Worst case can accommodate one packet of 64 bytes * PTXFIFO * - Recommended: (LPS/4) * 2 - * - Actual: Whatever leftover size: USB_DWC_HAL_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 + * - Actual: Whatever leftover size: USB_DWC_FIFO_TOTAL_USABLE_LINES(200) - 34 - 16 = 150 * - Worst case can accommodate two packets of 300 bytes or one packet of 600 bytes */ const usb_dwc_hal_fifo_config_t fifo_config_bias_ptx = { @@ -963,7 +963,7 @@ static port_t *port_obj_alloc(void) { port_t *port = calloc(1, sizeof(port_t)); usb_dwc_hal_context_t *hal = malloc(sizeof(usb_dwc_hal_context_t)); - void *frame_list = heap_caps_aligned_calloc(USB_DWC_HAL_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN, sizeof(uint32_t), MALLOC_CAP_DMA); + void *frame_list = heap_caps_aligned_calloc(USB_DWC_FRAME_LIST_MEM_ALIGN, FRAME_LIST_LEN, sizeof(uint32_t), MALLOC_CAP_DMA); SemaphoreHandle_t port_mux = xSemaphoreCreateMutex(); if (port == NULL || hal == NULL || frame_list == NULL || port_mux == NULL) { free(port); @@ -1594,7 +1594,7 @@ static dma_buffer_block_t *buffer_block_alloc(usb_transfer_type_t type) break; } dma_buffer_block_t *buffer = calloc(1, sizeof(dma_buffer_block_t)); - void *xfer_desc_list = heap_caps_aligned_calloc(USB_DWC_HAL_DMA_MEM_ALIGN, desc_list_len, sizeof(usb_dwc_ll_dma_qtd_t), MALLOC_CAP_DMA); + void *xfer_desc_list = heap_caps_aligned_calloc(USB_DWC_QTD_LIST_MEM_ALIGN, desc_list_len, sizeof(usb_dwc_ll_dma_qtd_t), MALLOC_CAP_DMA); if (buffer == NULL || xfer_desc_list == NULL) { free(buffer); heap_caps_free(xfer_desc_list);