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light sleep: add i/d-cache tagmem retention support for esp32s3

pull/10408/head
Li Shuai 2021-08-20 20:33:33 +08:00
rodzic 03746de96f
commit ccf1a9a1fc
7 zmienionych plików z 312 dodań i 9 usunięć
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142
components/esp_hw_support/sleep_retention.c
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@ -12,12 +12,20 @@
#include "esp_attr.h"
#include "esp_sleep.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_heap_caps.h"
#include "soc/soc_caps.h"
#include "hal/rtc_hal.h"
#include "esp_private/sleep_retention.h"
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#endif
static __attribute__((unused)) const char *TAG = "sleep";
/**
* Internal structure which holds all requested light sleep memory retention parameters
*/
@ -27,6 +35,126 @@ typedef struct {
static DRAM_ATTR sleep_retention_t s_retention;
#if SOC_PM_SUPPORT_TAGMEM_PD
#define TAGMEM_PD_MEM_TYPE_CAPS (MALLOC_CAP_DMA | MALLOC_CAP_DEFAULT)
#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
static int cache_tagmem_retention_setup(uint32_t code_seg_vaddr, uint32_t code_seg_size, uint32_t data_seg_vaddr, uint32_t data_seg_size)
{
int sets; /* i/d-cache total set counts */
int index; /* virtual address mapping i/d-cache row offset */
int waysgrp;
int icache_tagmem_blk_gs, dcache_tagmem_blk_gs;
struct cache_mode imode = { .icache = 1 };
struct cache_mode dmode = { .icache = 0 };
/* calculate/prepare i-cache tag memory retention parameters */
Cache_Get_Mode(&imode);
sets = imode.cache_size / imode.cache_ways / imode.cache_line_size;
index = (code_seg_vaddr / imode.cache_line_size) % sets;
waysgrp = imode.cache_ways >> 2;
code_seg_size = ALIGNUP(imode.cache_line_size, code_seg_size);
s_retention.retent.tagmem.icache.start_point = index;
s_retention.retent.tagmem.icache.size = (sets * waysgrp) & 0xff;
s_retention.retent.tagmem.icache.vld_size = s_retention.retent.tagmem.icache.size;
if (code_seg_size < imode.cache_size / imode.cache_ways) {
s_retention.retent.tagmem.icache.vld_size = (code_seg_size / imode.cache_line_size) * waysgrp;
}
s_retention.retent.tagmem.icache.enable = (code_seg_size != 0) ? 1 : 0;
icache_tagmem_blk_gs = s_retention.retent.tagmem.icache.vld_size ? s_retention.retent.tagmem.icache.vld_size : sets * waysgrp;
icache_tagmem_blk_gs = ALIGNUP(4, icache_tagmem_blk_gs);
ESP_LOGD(TAG, "I-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (imode.cache_size>>10),
imode.cache_line_size, imode.cache_ways, sets, index, icache_tagmem_blk_gs);
/* calculate/prepare d-cache tag memory retention parameters */
Cache_Get_Mode(&dmode);
sets = dmode.cache_size / dmode.cache_ways / dmode.cache_line_size;
index = (data_seg_vaddr / dmode.cache_line_size) % sets;
waysgrp = dmode.cache_ways >> 2;
data_seg_size = ALIGNUP(dmode.cache_line_size, data_seg_size);
s_retention.retent.tagmem.dcache.start_point = index;
s_retention.retent.tagmem.dcache.size = (sets * waysgrp) & 0x1ff;
s_retention.retent.tagmem.dcache.vld_size = s_retention.retent.tagmem.dcache.size;
#ifndef CONFIG_ESP32S3_DATA_CACHE_16KB
if (data_seg_size < dmode.cache_size / dmode.cache_ways) {
s_retention.retent.tagmem.dcache.vld_size = (data_seg_size / dmode.cache_line_size) * waysgrp;
}
s_retention.retent.tagmem.dcache.enable = (data_seg_size != 0) ? 1 : 0;
#else
s_retention.retent.tagmem.dcache.enable = 1;
#endif
dcache_tagmem_blk_gs = s_retention.retent.tagmem.dcache.vld_size ? s_retention.retent.tagmem.dcache.vld_size : sets * waysgrp;
dcache_tagmem_blk_gs = ALIGNUP(4, dcache_tagmem_blk_gs);
ESP_LOGD(TAG, "D-cache size:%d KiB, line size:%d B, ways:%d, sets:%d, index:%d, tag block groups:%d", (dmode.cache_size>>10),
dmode.cache_line_size, dmode.cache_ways, sets, index, dcache_tagmem_blk_gs);
/* For I or D cache tagmem retention, backup and restore are performed through
* RTC DMA (its bus width is 128 bits), For I/D Cache tagmem blocks (i-cache
* tagmem blocks = 92 bits, d-cache tagmem blocks = 88 bits), RTC DMA automatically
* aligns its bit width to 96 bits, therefore, 3 times RTC DMA can transfer 4
* i/d-cache tagmem blocks (128 bits * 3 = 96 bits * 4) */
return (((icache_tagmem_blk_gs + dcache_tagmem_blk_gs) << 2) * 3);
}
#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
static esp_err_t esp_sleep_tagmem_pd_low_init(bool enable)
{
if (enable) {
#if CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
if (s_retention.retent.tagmem.link_addr == NULL) {
extern char _stext[], _etext[];
uint32_t code_start = (uint32_t)_stext;
uint32_t code_size = (uint32_t)(_etext - _stext);
#if !CONFIG_ESP32S3_SPIRAM_SUPPORT
extern char _rodata_start[], _rodata_reserved_end[];
uint32_t data_start = (uint32_t)_rodata_start;
uint32_t data_size = (uint32_t)(_rodata_reserved_end - _rodata_start);
#else
uint32_t data_start = SOC_DROM_LOW;
uint32_t data_size = (SOC_EXTRAM_DATA_HIGH-SOC_EXTRAM_DATA_LOW) + (SOC_DROM_HIGH-SOC_DROM_LOW);
#endif
ESP_LOGI(TAG, "Code start at %08x, total %.2f KiB, data start at %08x, total %.2f KiB",
code_start, (float)code_size/1024, data_start, (float)data_size/1024);
int tagmem_sz = cache_tagmem_retention_setup(code_start, code_size, data_start, data_size);
void *buf = heap_caps_aligned_alloc(SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN,
tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE,
TAGMEM_PD_MEM_TYPE_CAPS);
if (buf) {
memset(buf, 0, tagmem_sz + RTC_HAL_DMA_LINK_NODE_SIZE);
s_retention.retent.tagmem.link_addr = rtc_cntl_hal_dma_link_init(buf,
buf + RTC_HAL_DMA_LINK_NODE_SIZE, tagmem_sz, NULL);
} else {
s_retention.retent.tagmem.icache.enable = 0;
s_retention.retent.tagmem.dcache.enable = 0;
s_retention.retent.tagmem.link_addr = NULL;
return ESP_ERR_NO_MEM;
}
}
#else // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
s_retention.retent.tagmem.icache.enable = 0;
s_retention.retent.tagmem.dcache.enable = 0;
s_retention.retent.tagmem.link_addr = NULL;
#endif // CONFIG_PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
} else {
#if SOC_PM_SUPPORT_TAGMEM_PD
if (s_retention.retent.tagmem.link_addr) {
heap_caps_free(s_retention.retent.tagmem.link_addr);
s_retention.retent.tagmem.icache.enable = 0;
s_retention.retent.tagmem.dcache.enable = 0;
s_retention.retent.tagmem.link_addr = NULL;
}
#endif
}
return ESP_OK;
}
#endif // SOC_PM_SUPPORT_TAGMEM_PD
#if SOC_PM_SUPPORT_CPU_PD
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
@ -56,6 +184,14 @@ esp_err_t esp_sleep_cpu_pd_low_init(bool enable)
s_retention.retent.cpu_pd_mem = NULL;
}
}
#if SOC_PM_SUPPORT_TAGMEM_PD
if (esp_sleep_tagmem_pd_low_init(enable) != ESP_OK) {
#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
esp_sleep_cpu_pd_low_init(false);
return ESP_ERR_NO_MEM;
#endif
}
#endif
return ESP_OK;
}
@ -73,6 +209,9 @@ void sleep_enable_memory_retention(void)
#if SOC_PM_SUPPORT_CPU_PD
rtc_cntl_hal_enable_cpu_retention(&s_retention.retent);
#endif
#if SOC_PM_SUPPORT_TAGMEM_PD
rtc_cntl_hal_enable_tagmem_retention(&s_retention.retent);
#endif
}
void IRAM_ATTR sleep_disable_memory_retention(void)
@ -80,6 +219,9 @@ void IRAM_ATTR sleep_disable_memory_retention(void)
#if SOC_PM_SUPPORT_CPU_PD
rtc_cntl_hal_disable_cpu_retention(&s_retention.retent);
#endif
#if SOC_PM_SUPPORT_TAGMEM_PD
rtc_cntl_hal_disable_tagmem_retention(&s_retention.retent);
#endif
}
#endif // SOC_PM_SUPPORT_CPU_PD || SOC_PM_SUPPORT_TAGMEM_PD

9
components/esp_pm/Kconfig
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@ -97,6 +97,7 @@ menu "Power Management"
config PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
bool "Power down CPU in light sleep"
depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
select PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP if ESP32S3_DATA_CACHE_16KB
default y
help
If enabled, the CPU will be powered down in light sleep. On esp32c3 soc, enabling this
@ -104,4 +105,12 @@ menu "Power Management"
by about 100 uA. On esp32s3 soc, enabling this option will consume 8.58 KB of internal
RAM and will reduce sleep current consumption by about 650 uA.
config PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP
bool "Power down I/D-cache tag memory in light sleep"
depends on IDF_TARGET_ESP32S3 && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP
default y
help
If enabled, the I/D-cache tag memory will be retained in light sleep. Depending on the the
cache configuration, if this option is enabled, it will consume up to 9 KB of internal RAM.
endmenu # "Power Management"

2
components/esp_pm/linker.lf
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@ -77,3 +77,5 @@ entries:
gpio_hal_workaround:gpio_hal_fun_pupd_restore (noflash)
if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_CPU_IN_LIGHT_SLEEP = y:
rtc_cntl_hal:rtc_cntl_hal_enable_cpu_retention (noflash)
if PM_SLP_IRAM_OPT = y && PM_POWER_DOWN_TAGMEM_IN_LIGHT_SLEEP = y:
rtc_cntl_hal:rtc_cntl_hal_enable_tagmem_retention (noflash)

62
components/hal/esp32s3/include/hal/rtc_cntl_ll.h
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@ -23,6 +23,9 @@
extern "C" {
#endif
#define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0))
#define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1))
static inline void rtc_cntl_ll_set_wakeup_timer(uint64_t t)
{
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
@ -54,6 +57,51 @@ static inline void rtc_cntl_ll_ulp_wakeup_enable(void)
SET_PERI_REG_BITS(RTC_CNTL_STATE0_REG, RTC_CNTL_WAKEUP_ENA_V, 0x800, RTC_CNTL_WAKEUP_ENA_S);
}
static inline void rtc_cntl_ll_set_tagmem_retention_link_addr(uint32_t link_addr)
{
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL1_REG, APB_CTRL_RETENTION_TAG_LINK_ADDR, link_addr);
}
static inline void rtc_cntl_ll_enable_tagmem_retention(void)
{
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
}
static inline void rtc_cntl_ll_enable_icache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
{
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_START_POINT, start_point);
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_VLD_SIZE, vld_size);
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_SIZE, size);
REG_SET_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE);
}
static inline void rtc_cntl_ll_enable_dcache_tagmem_retention(uint32_t start_point, uint32_t vld_size, uint32_t size)
{
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_START_POINT, start_point);
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_VLD_SIZE, vld_size);
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_SIZE, size);
REG_SET_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE);
}
static inline void rtc_cntl_ll_disable_tagmem_retention(void)
{
/* Enable i/d-cache tagmem retenttion. cpu: 1, tagmem: 2, cpu + tagmem: 3 */
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target & ~RTC_CNTL_LL_RETENTION_TARGET_TAGMEM));
}
static inline void rtc_cntl_ll_disable_icache_tagmem_retention(void)
{
REG_CLR_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE);
}
static inline void rtc_cntl_ll_disable_dcache_tagmem_retention(void)
{
REG_CLR_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE);
}
static inline void rtc_cntl_ll_set_cpu_retention_link_addr(uint32_t link_addr)
{
REG_SET_FIELD(APB_CTRL_RETENTION_CTRL_REG, APB_CTRL_RETENTION_CPU_LINK_ADDR, link_addr);
@ -68,16 +116,18 @@ static inline void rtc_cntl_ll_enable_cpu_retention(void)
{
uint32_t target = REG_GET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET);
/* TODO: I/d-Cache tagmem retention has not been implementted yet,
* so i/d-cache tagmem retention is explicitly disabled */
REG_CLR_BIT(APB_CTRL_RETENTION_CTRL2_REG, APB_CTRL_RET_ICACHE_ENABLE);
REG_CLR_BIT(APB_CTRL_RETENTION_CTRL3_REG, APB_CTRL_RET_DCACHE_ENABLE);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | 0x1));
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_TARGET, (target | RTC_CNTL_LL_RETENTION_TARGET_CPU));
/* Enable retention when cpu sleep enable */
REG_SET_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);
}
static inline void rtc_cntl_ll_config_cpu_retention_timing(int wait, int clkoff_wait, int done_wait)
{
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_WAIT, wait);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_CLKOFF_WAIT, clkoff_wait);
REG_SET_FIELD(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_DONE_WAIT, done_wait);
}
static inline void rtc_cntl_ll_disable_cpu_retention(void)
{
REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN);

71
components/hal/esp32s3/rtc_cntl_hal.c
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@ -41,6 +41,10 @@ void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next)
#if SOC_PM_SUPPORT_CPU_PD
#define DEFAULT_RETENTION_WAIT_CYCLES (0x7f)
#define DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES (0xf)
#define DEFAULT_RETENTION_DONE_WAIT_CYCLES (0x7)
void rtc_cntl_hal_enable_cpu_retention(void *addr)
{
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
@ -57,6 +61,11 @@ void rtc_cntl_hal_enable_cpu_retention(void *addr)
pbuf->cfg[3] = 0xfffe0000;
rtc_cntl_ll_set_cpu_retention_link_addr((uint32_t)plink);
rtc_cntl_ll_config_cpu_retention_timing(
DEFAULT_RETENTION_WAIT_CYCLES,
DEFAULT_RETENTION_CLKOFF_WAIT_CYCLES,
DEFAULT_RETENTION_DONE_WAIT_CYCLES
);
rtc_cntl_ll_enable_cpu_retention_clock();
rtc_cntl_ll_enable_cpu_retention();
}
@ -69,14 +78,70 @@ void IRAM_ATTR rtc_cntl_hal_disable_cpu_retention(void *addr)
if (addr) {
if (retent->cpu_pd_mem) {
/* TODO: I/d-cache tagmem retention has not been implemented yet,
* so after the system wakes up, all the contents of i/d-cache need
* to be invalidated. */
/* I/d-cache tagmem retention has not been included or not
* been enabled, after the system wakes up, all the contents
* of i/d-cache need to be invalidated. */
#if SOC_PM_SUPPORT_TAGMEM_PD
if (!retent->tagmem.icache.enable) {
Cache_Invalidate_ICache_All();
}
if (!retent->tagmem.dcache.enable) {
Cache_Invalidate_DCache_All();
}
#else
Cache_Invalidate_ICache_All();
Cache_Invalidate_DCache_All();
#endif // SOC_PM_SUPPORT_TAGMEM_PD
rtc_cntl_ll_disable_cpu_retention();
}
}
}
#endif // SOC_PM_SUPPORT_CPU_PD
#if SOC_PM_SUPPORT_TAGMEM_PD
void rtc_cntl_hal_enable_tagmem_retention(void *addr)
{
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
if (addr) {
if (retent->tagmem.link_addr) {
rtc_cntl_ll_set_tagmem_retention_link_addr((uint32_t)(retent->tagmem.link_addr));
rtc_cntl_ll_enable_tagmem_retention();
if (retent->tagmem.icache.enable) {
rtc_cntl_ll_enable_icache_tagmem_retention(
retent->tagmem.icache.start_point,
retent->tagmem.icache.vld_size,
retent->tagmem.icache.size
);
}
if (retent->tagmem.dcache.enable) {
rtc_cntl_ll_enable_dcache_tagmem_retention(
retent->tagmem.dcache.start_point,
retent->tagmem.dcache.vld_size,
retent->tagmem.dcache.size
);
}
}
}
}
void IRAM_ATTR rtc_cntl_hal_disable_tagmem_retention(void *addr)
{
rtc_cntl_sleep_retent_t *retent = (rtc_cntl_sleep_retent_t *)addr;
if (addr) {
if (retent->tagmem.link_addr) {
rtc_cntl_ll_disable_tagmem_retention();
if (retent->tagmem.icache.enable) {
rtc_cntl_ll_disable_icache_tagmem_retention();
}
if (retent->tagmem.dcache.enable) {
rtc_cntl_ll_disable_dcache_tagmem_retention();
}
}
}
}
#endif // SOC_PM_SUPPORT_TAGMEM_PD

29
components/hal/include/hal/rtc_hal.h
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@ -25,6 +25,23 @@ typedef struct rtc_cntl_sleep_retent {
#if SOC_PM_SUPPORT_CPU_PD
void *cpu_pd_mem; /* Internal ram address for cpu retention */
#endif // SOC_PM_SUPPORT_CPU_PD
#if SOC_PM_SUPPORT_TAGMEM_PD
struct {
void *link_addr; /* Internal ram address for tagmem retention */
struct {
uint32_t start_point: 8, /* the row of start for i-cache tag memory */
vld_size: 8, /* valid size of i-cache tag memory, unit: 4 i-cache tagmem blocks */
size: 8, /* i-cache tag memory size, unit: 4 i-cache tagmem blocks */
enable: 1; /* enable or disable i-cache tagmem retention */
} icache;
struct {
uint32_t start_point: 9, /* the row of start for d-cache tag memory */
vld_size: 9, /* valid size of d-cache tag memory, unit: 4 d-cache tagmem blocks */
size: 9, /* d-cache tag memory size, unit: 4 d-cache tagmem blocks */
enable: 1; /* enable or disable d-cache tagmem retention */
} dcache;
} tagmem;
#endif // SOC_PM_SUPPORT_TAGMEM_PD
} rtc_cntl_sleep_retent_t;
#define RTC_HAL_DMA_LINK_NODE_SIZE (16)
@ -53,10 +70,22 @@ typedef struct rtc_cntl_sleep_retent {
void * rtc_cntl_hal_dma_link_init(void *elem, void *buff, int size, void *next);
#if SOC_PM_SUPPORT_CPU_PD
void rtc_cntl_hal_enable_cpu_retention(void *addr);
void rtc_cntl_hal_disable_cpu_retention(void *addr);
#endif
#if SOC_PM_SUPPORT_TAGMEM_PD
void rtc_cntl_hal_enable_tagmem_retention(void *addr);
void rtc_cntl_hal_disable_tagmem_retention(void *addr);
#endif
/*
* Enable wakeup from ULP coprocessor.
*/

6
components/soc/esp32s3/include/soc/soc_caps.h
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@ -126,6 +126,10 @@
#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
/* I/D Cache tag memory retention hardware parameters */
#define SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH (128)
#define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3)
/*-------------------------- RTCIO CAPS --------------------------------------*/
#include "rtc_io_caps.h"
@ -220,6 +224,8 @@
#define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_TAGMEM_PD (1)
/*-------------------------- Flash Encryption CAPS----------------------------*/
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)