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fix(esp_driver_gpio): manage lp_io module clock by driver 

Closes https://github.com/espressif/esp-idf/issues/13683
pull/14033/head
wuzhenghui 2024-05-20 20:18:25 +08:00
rodzic 78c40fd19a
commit cca222948a
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ID klucza GPG: 3EFEDECDEBA39BB9
14 zmienionych plików z 153 dodań i 80 usunięć
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36
components/esp_driver_gpio/src/gpio.c
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@ -22,13 +22,7 @@
#include "hal/gpio_hal.h"
#include "esp_rom_gpio.h"
#include "esp_private/esp_gpio_reserve.h"
#include "esp_private/periph_ctrl.h"
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT
#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
#define RTCIO_RCC_ATOMIC()
#endif
#include "esp_private/io_mux.h"
#if (SOC_RTCIO_PIN_COUNT > 0)
#include "hal/rtc_io_hal.h"
@ -66,9 +60,6 @@ typedef struct {
gpio_isr_func_t *gpio_isr_func;
gpio_isr_handle_t gpio_isr_handle;
uint64_t isr_clr_on_entry_mask; // for edge-triggered interrupts, interrupt status bits should be cleared before entering per-pin handlers
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_LP_IO_CLOCK_IS_INDEPENDENT
uint32_t gpio_wakeup_mask;
#endif
} gpio_context_t;
static gpio_hal_context_t _gpio_hal = {
@ -81,9 +72,6 @@ static gpio_context_t gpio_context = {
.isr_core_id = GPIO_ISR_CORE_ID_UNINIT,
.gpio_isr_func = NULL,
.isr_clr_on_entry_mask = 0,
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP && SOC_LP_IO_CLOCK_IS_INDEPENDENT
.gpio_wakeup_mask = 0,
#endif
};
esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
@ -639,6 +627,11 @@ esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
if ((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
#if SOC_RTCIO_WAKE_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
// LP_IO Wake-up function does not depend on LP_IO Matrix, but uses its clock to
// sample the wake-up signal, we need to enable the LP_IO clock here.
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
ret = rtc_gpio_wakeup_enable(gpio_num, intr_type);
}
#endif
@ -664,6 +657,9 @@ esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
#if SOC_RTCIO_WAKE_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
ret = rtc_gpio_wakeup_disable(gpio_num);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, false);
#endif
}
#endif
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
@ -992,12 +988,7 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int
}
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
if (gpio_context.gpio_wakeup_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(true);
}
}
gpio_context.gpio_wakeup_mask |= (1ULL << gpio_num);
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
gpio_hal_deepsleep_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type);
#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO
@ -1019,12 +1010,7 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num)
gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num);
#endif
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
gpio_context.gpio_wakeup_mask &= ~(1ULL << gpio_num);
if (gpio_context.gpio_wakeup_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
}
}
io_mux_enable_lp_io_clock(gpio_num, false);
#endif
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
return ESP_OK;

22
components/esp_driver_gpio/src/rtc_io.c
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@ -9,6 +9,7 @@
#include "esp_err.h"
#include "esp_check.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/io_mux.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/timers.h"
@ -18,16 +19,6 @@
#include "soc/rtc_io_periph.h"
#include "soc/soc_caps.h"
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT
// For `rtcio_hal_function_select` using, clock reg option is inlined in it,
// so remove the declaration check of __DECLARE_RCC_RC_ATOMIC_ENV
#define RTCIO_RCC_ATOMIC() \
for (int i = 1; i ? (periph_rcc_enter(), 1) : 0; \
periph_rcc_exit(), i--)
#else
#define RTCIO_RCC_ATOMIC()
#endif
static const char __attribute__((__unused__)) *RTCIO_TAG = "RTCIO";
extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
@ -56,9 +47,10 @@ esp_err_t rtc_gpio_init(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
RTCIO_RCC_ATOMIC() {
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, true);
#endif
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_RTC);
}
RTCIO_EXIT_CRITICAL();
return ESP_OK;
@ -68,10 +60,12 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
RTCIO_RCC_ATOMIC() {
// Select Gpio as Digital Gpio
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL);
}
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(gpio_num, false);
#endif
RTCIO_EXIT_CRITICAL();
return ESP_OK;

20
components/esp_hw_support/include/esp_private/io_mux.h
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@ -1,13 +1,17 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include "esp_err.h"
#include "soc/clk_tree_defs.h"
#include "soc/gpio_num.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
@ -26,6 +30,20 @@ extern "C" {
*/
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
typedef struct {
uint8_t rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM];
uint32_t rtc_io_using_mask;
} rtc_io_status_t;
/**
* Enable/Disable LP_IO peripheral clock.
* @param gpio_num GPIO number
* @param enable true to enable the clock / false to disable the clock
*/
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable);
#endif
#ifdef __cplusplus
}
#endif

39
components/esp_hw_support/port/esp32c6/io_mux.c
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@ -1,16 +1,29 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "freertos/FreeRTOS.h"
#include "esp_private/io_mux.h"
#include "esp_private/periph_ctrl.h"
#include "hal/gpio_ll.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
#if CONFIG_ULP_COPROC_ENABLED
RTC_DATA_ATTR
#endif
static rtc_io_status_t s_rtc_io_status = {
.rtc_io_enabled_cnt = { 0 },
.rtc_io_using_mask = 0
};
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
bool clk_conflict = false;
@ -31,3 +44,27 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
return ESP_OK;
}
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_status.rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}

32
components/esp_hw_support/port/esp32h2/io_mux.c
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@ -1,15 +1,21 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "freertos/FreeRTOS.h"
#include "esp_private/io_mux.h"
#include "esp_private/periph_ctrl.h"
#include "hal/gpio_ll.h"
#include "hal/rtc_io_ll.h"
#define RTCIO_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
static portMUX_TYPE s_io_mux_spinlock = portMUX_INITIALIZER_UNLOCKED;
static soc_module_clk_t s_io_mux_clk_src = 0; // by default, the clock source is not set explicitly by any consumer (e.g. SDM, Filter)
static uint8_t s_rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM] = { 0 };
static uint32_t s_rtc_io_using_mask = 0;
esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
{
@ -31,3 +37,27 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
return ESP_OK;
}
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
portENTER_CRITICAL(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask |= (1ULL << gpio_num);
}
s_rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_using_mask &= ~(1ULL << gpio_num);
}
}
RTCIO_RCC_ATOMIC() {
if (s_rtc_io_using_mask == 0) {
rtcio_ll_enable_io_clock(false);
} else {
rtcio_ll_enable_io_clock(true);
}
}
portEXIT_CRITICAL(&s_io_mux_spinlock);
}

24
components/esp_hw_support/sleep_modes.c
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@ -15,10 +15,10 @@
#include "esp_sleep.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/esp_timer_private.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/rtc_clk.h"
#include "esp_private/sleep_event.h"
#include "esp_private/system_internal.h"
#include "esp_private/io_mux.h"
#include "esp_log.h"
#include "esp_newlib.h"
#include "esp_timer.h"
@ -119,16 +119,6 @@
#include "esp_private/sleep_retention.h"
#endif
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !SOC_RTCIO_RCC_IS_INDEPENDENT
// For `rtcio_hal_function_select` using, clock reg option is inlined in it,
// so remove the declaration check of __DECLARE_RCC_RC_ATOMIC_ENV
#define RTCIO_RCC_ATOMIC() \
for (int i = 1; i ? (periph_rcc_enter(), 1) : 0; \
periph_rcc_exit(), i--)
#else
#define RTCIO_RCC_ATOMIC()
#endif
// If light sleep time is less than that, don't power down flash
#define FLASH_PD_MIN_SLEEP_TIME_US 2000
@ -1694,10 +1684,11 @@ esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
static void ext0_wakeup_prepare(void)
{
int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(rtc_gpio_num, true);
#endif
rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
RTCIO_RCC_ATOMIC() {
rtcio_hal_function_select(rtc_gpio_num, RTCIO_LL_FUNC_RTC);
}
rtcio_hal_input_enable(rtc_gpio_num);
}
@ -1826,11 +1817,12 @@ static void ext1_wakeup_prepare(void)
if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
continue;
}
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_enable_lp_io_clock(rtc_pin, true);
#endif
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// Route pad to RTC
RTCIO_RCC_ATOMIC() {
rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_RTC);
}
// set input enable in sleep mode
rtcio_hal_input_enable(rtc_pin);
#if SOC_PM_SUPPORT_RTC_PERIPH_PD
@ -1845,9 +1837,7 @@ static void ext1_wakeup_prepare(void)
* a pathway to EXT1. */
// Route pad to DIGITAL
RTCIO_RCC_ATOMIC() {
rtcio_hal_function_select(rtc_pin, RTCIO_LL_FUNC_DIGITAL);
}
// set input enable
gpio_ll_input_enable(&GPIO, gpio);
// hold rtc_pin to use it during sleep state

11
components/hal/esp32c6/include/hal/rtc_io_ll.h
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@ -68,11 +68,14 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func)
/**
* @brief Enable/Disable LP_IO peripheral clock.
*
* @param enable true to enable the clock / false to enable the clock
* @param enable true to enable the clock / false to disable the clock
*/
static inline void _rtcio_ll_enable_io_clock(bool enable)
{
LPPERI.clk_en.lp_io_ck_en = enable;
while (LPPERI.clk_en.lp_io_ck_en != enable) {
;
}
}
#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__)
@ -92,9 +95,6 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
_rtcio_ll_enable_io_clock(true);
}
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
//0:RTC FUNCTION 1,2,3:Reserved
@ -104,9 +104,6 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
_rtcio_ll_enable_io_clock(false);
}
}
}

11
components/hal/esp32h2/include/hal/rtc_io_ll.h
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@ -34,11 +34,14 @@ typedef enum {
/**
* @brief Enable/Disable LP_IO peripheral clock.
*
* @param enable true to enable the clock / false to enable the clock
* @param enable true to enable the clock / false to disable the clock
*/
static inline void _rtcio_ll_enable_io_clock(bool enable)
{
LPPERI.clk_en.lp_io_ck_en = enable;
while (LPPERI.clk_en.lp_io_ck_en != enable) {
;
}
}
#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__)
@ -56,9 +59,6 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
if (func == RTCIO_LL_FUNC_RTC) {
// 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
_rtcio_ll_enable_io_clock(true);
}
sel_mask |= BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
} else if (func == RTCIO_LL_FUNC_DIGITAL) {
@ -66,9 +66,6 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
sel_mask &= ~BIT(rtcio_num);
HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
if((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
_rtcio_ll_enable_io_clock(false);
}
}
}

10
components/hal/include/hal/rtc_io_hal.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -31,6 +31,14 @@ extern "C" {
#endif
#if SOC_RTCIO_PIN_COUNT > 0
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
/**
* Enable rtcio module clock.
*/
#define rtcio_hal_enable_io_clock(enable) rtcio_ll_output_enable(enable)
#endif
/**
* Select the rtcio function.
*

4
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@ -495,6 +495,10 @@ config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
default y
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_GPIO_IN_RANGE_MAX
int
default 27

3
components/soc/esp32h2/include/soc/soc_caps.h
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@ -198,6 +198,9 @@
// However, there is no way to control pullup/down/capability for IOs under LP function since there is no LP_IOMUX registers
#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
// GPIO7~14 on ESP32H2 can support chip deep sleep wakeup through EXT1 wake up
#define SOC_GPIO_VALID_GPIO_MASK ((1U << SOC_GPIO_PIN_COUNT) - 1)

2
components/soc/include/soc/rtc_io_periph.h
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@ -14,6 +14,8 @@
#include "soc/rtc_io_channel.h"
#endif
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C"
{

5
components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h
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@ -49,11 +49,16 @@ typedef enum {
/**
* @brief Initialize a rtcio pin
* @note If IO is used in LP application, `rtc_gpio_init` must be called at least once
* for the using IO before loading LP core firmware in HP Code.
*
* @param lp_io_num The rtc io pin to initialize
*/
static inline void ulp_lp_core_gpio_init(lp_io_num_t lp_io_num)
{
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
_rtcio_ll_enable_io_clock(true);
#endif
rtcio_ll_function_select(lp_io_num, RTCIO_LL_FUNC_RTC);
}

2
components/ulp/test_apps/lp_core/main/test_lp_core.c
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@ -8,6 +8,7 @@
#include <inttypes.h>
#include <sys/time.h>
#include "soc/soc_caps.h"
#include "soc/gpio_num.h"
#include "esp_rom_caps.h"
#include "lp_core_test_app.h"
#include "lp_core_test_app_counter.h"
@ -328,6 +329,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
.lp_timer_sleep_duration_us = LP_TIMER_TEST_SLEEP_DURATION_US,
};
rtc_gpio_init(GPIO_NUM_0);
load_and_start_lp_core_firmware(&cfg, lp_core_main_gpio_bin_start, lp_core_main_gpio_bin_end);
while (!ulp_gpio_test_finished) {