kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/use_api_to_enable_modem_on_esp32h2_v5.1' into 'release/v5.1'
ble: use modem_clock api to set clocks on ESP32-H2 See merge request espressif/esp-idf!23806pull/11519/head
commit
cc7c851cb2
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@ -583,32 +583,6 @@ void controller_sleep_deinit(void)
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#endif //CONFIG_PM_ENABLE
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}
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#define REG_MODEM_SYSCON_BASE 0x600A5400
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#define REG_MODEM_LPCON_BASE 0x600AD000
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#define DR_REG_MODEM_SYSCON_BASE REG_MODEM_SYSCON_BASE
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#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
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#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
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#define MODEM_LPCON_CLK_CONF_REG (REG_MODEM_LPCON_BASE + 0x0008)
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#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (REG_MODEM_LPCON_BASE + 0x000C)
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#include "hal/clk_tree_ll.h"
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static void enable_chip_clk(void)
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{
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WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF_REG,0xFFFFFFFF);
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WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF1_REG,0xFFFFFFFF);
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WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
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// SET BIT for BLE RTC clk
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SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG,PMU_HP_SLEEP_XPD_XTAL32K);
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// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_SEL_XTAL32K,1);
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// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_BLETIMER_DIV_NUM,0);
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/* For chip */
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WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
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WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_FORCE_ON_REG ,0xFFFFFFFF);
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}
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esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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{
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uint8_t mac[6];
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@ -633,8 +607,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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return ret;
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}
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enable_chip_clk();
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/* Initialize the function pointers for OS porting */
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npl_freertos_funcs_init();
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struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
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@ -674,9 +646,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
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#endif // CONFIG_BT_NIMBLE_ENABLED
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/* Enable BT-related clocks */
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// modem_clock_module_enable(PERIPH_BT_MODULE);
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// modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
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// esp_phy_modem_init();
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modem_clock_module_enable(PERIPH_BT_MODULE);
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modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
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esp_phy_enable();
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esp_btbb_enable();
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s_ble_active = true;
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@ -718,9 +689,8 @@ free_controller:
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ble_controller_deinit();
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esp_btbb_disable();
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esp_phy_disable();
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// esp_phy_modem_deinit();
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// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
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// modem_clock_module_disable(PERIPH_BT_MODULE);
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modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
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modem_clock_module_disable(PERIPH_BT_MODULE);
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#if CONFIG_BT_NIMBLE_ENABLED
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ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
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#endif // CONFIG_BT_NIMBLE_ENABLED
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@ -749,9 +719,8 @@ esp_err_t esp_bt_controller_deinit(void)
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esp_phy_disable();
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s_ble_active = false;
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}
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// esp_phy_modem_deinit();
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// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
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// modem_clock_module_disable(PERIPH_BT_MODULE);
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modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
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modem_clock_module_disable(PERIPH_BT_MODULE);
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ble_controller_deinit();
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