kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/keep_rtc8m_in_lightsleep' into 'master'
pm: fixed RTC8M domain power down issue when used as RTC source See merge request espressif/esp-idf!17612pull/8968/head
commit
cc37f63e14
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@ -847,6 +847,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
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@ -180,14 +180,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
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if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == RTC_SLOW_FREQ_8MD256) {
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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} else {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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}
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//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
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if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
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if (!cfg.int_8m_pd_en) {
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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} else {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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@ -386,6 +386,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
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@ -85,9 +85,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
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}
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//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
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if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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} else {
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@ -509,6 +509,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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static bool rtc_clk_set_bbpll_always_on(void)
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{
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/* We just keep the rtc bbpll clock on just under the case that
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@ -113,9 +113,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
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}
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//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
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if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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} else {
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@ -405,6 +405,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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uint32_t read_spll_freq(void)
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{
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return REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SPLL_FREQ);
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@ -217,6 +217,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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}
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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}
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/* enable VDDSDIO control by state machine */
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REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
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REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
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@ -572,6 +572,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
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@ -111,9 +111,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP);
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}
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//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
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if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
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if (!cfg.int_8m_pd_en) {
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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} else {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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@ -555,6 +555,11 @@ void rtc_dig_clk8m_disable(void)
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esp_rom_delay_us(DELAY_RTC_CLK_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
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}
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static bool rtc_clk_set_bbpll_always_on(void)
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{
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/* We just keep the rtc bbpll clock on just under the case that
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@ -122,9 +122,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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/* mem pd */
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
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//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
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if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
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if (!cfg.int_8m_pd_en) {
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REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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} else {
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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@ -385,6 +385,20 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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suspend_uarts();
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}
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#if SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
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//Keep the RTC8M_CLK on if RTC clock is 8MD256.
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bool rtc_using_8md256 = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_8MD256);
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#else
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bool rtc_using_8md256 = false;
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#endif
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//Keep the RTC8M_CLK on if the ledc low-speed channel is clocked by RTC8M_CLK in lightsleep mode
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bool dig_8m_enabled = !deep_sleep && rtc_dig_8m_enabled();
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//Override user-configured power modes.
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if (rtc_using_8md256 || dig_8m_enabled) {
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pd_flags &= ~RTC_SLEEP_PD_INT_8M;
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}
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// Save current frequency and switch to XTAL
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rtc_cpu_freq_config_t cpu_freq_config;
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rtc_clk_cpu_freq_get_config(&cpu_freq_config);
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@ -437,6 +451,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
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}
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}
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#endif
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uint32_t reject_triggers = 0;
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if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
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/* Light sleep, enable sleep reject for faster return from this function,
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@ -558,7 +573,7 @@ void IRAM_ATTR esp_deep_sleep_start(void)
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// Correct the sleep time
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s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
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uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO;
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uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL;
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#if SOC_PM_SUPPORT_WIFI_PD
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force_pd_flags |= RTC_SLEEP_PD_WIFI;
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@ -171,6 +171,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
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int
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default 12
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config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
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bool
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default y
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config SOC_SHARED_IDCACHE_SUPPORTED
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bool
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default y
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@ -485,6 +485,11 @@ void rtc_dig_clk8m_enable(void);
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*/
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void rtc_dig_clk8m_disable(void);
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/**
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* @brief Get whether the rtc digital 8M clock is enabled
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*/
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bool rtc_dig_8m_enabled(void);
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/**
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* @brief Calculate the real clock value after the clock calibration
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*
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@ -534,7 +539,7 @@ typedef struct rtc_sleep_config_s {
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.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
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.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
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.wifi_pd_en = 0, \
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.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.rom_mem_pd_en = 0, \
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.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
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.wdt_flashboot_mod_en = 0, \
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@ -120,6 +120,7 @@
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (9)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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@ -123,6 +123,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
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int
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default 12
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config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
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bool
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default y
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config SOC_BROWNOUT_RESET_SUPPORTED
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bool
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default y
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@ -504,6 +504,11 @@ void rtc_dig_clk8m_enable(void);
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*/
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void rtc_dig_clk8m_disable(void);
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/**
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* @brief Get whether the rtc digital 8M clock is enabled
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*/
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bool rtc_dig_8m_enabled(void);
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/**
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* @brief Calculate the real clock value after the clock calibration
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*
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@ -571,7 +576,7 @@ typedef struct {
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#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
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#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
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.lslp_mem_inf_fpu = 1, \
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.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
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.wdt_flashboot_mod_en = 0, \
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.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
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@ -583,7 +588,7 @@ typedef struct {
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: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
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: RTC_CNTL_DBIAS_SLP, \
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.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
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.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
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.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
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.deep_slp_reject = 1, \
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.light_slp_reject = 1 \
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};
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@ -65,6 +65,7 @@
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/*!< RTC */
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#define SOC_ADC_RTC_MIN_BITWIDTH (12)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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@ -439,6 +439,10 @@ config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
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int
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default 108
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config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
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bool
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default y
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config SOC_RTCIO_PIN_COUNT
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int
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default 0
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@ -564,6 +564,11 @@ void rtc_dig_clk8m_enable(void);
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*/
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void rtc_dig_clk8m_disable(void);
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/**
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* @brief Get whether the rtc digital 8M clock is enabled
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*/
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bool rtc_dig_8m_enabled(void);
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/**
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* @brief Calculate the real clock value after the clock calibration
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*
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@ -648,7 +653,7 @@ typedef struct {
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.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
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.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
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.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
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.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
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.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
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.wdt_flashboot_mod_en = 0, \
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@ -661,7 +666,7 @@ typedef struct {
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: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
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: RTC_CNTL_DBIAS_SLP, \
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.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
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.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
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.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
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.deep_slp_reject = 1, \
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.light_slp_reject = 1 \
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};
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@ -209,6 +209,8 @@
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#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
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#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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@ -580,6 +580,11 @@ void rtc_dig_clk8m_enable(void);
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*/
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void rtc_dig_clk8m_disable(void);
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/**
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* @brief Get whether the rtc digital 8M clock is enabled
|
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*/
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bool rtc_dig_8m_enabled(void);
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/**
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||||
* @brief Calculate the real clock value after the clock calibration
|
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*
|
||||
|
@ -664,7 +669,7 @@ typedef struct {
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|||
.dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \
|
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.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
|
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.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
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.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
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||||
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
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||||
.wdt_flashboot_mod_en = 0, \
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||||
|
@ -677,7 +682,7 @@ typedef struct {
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|||
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
|
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: RTC_CNTL_DBIAS_SLP, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
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||||
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.deep_slp_reject = 1, \
|
||||
.light_slp_reject = 1 \
|
||||
};
|
||||
|
|
|
@ -191,6 +191,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
|
|||
int
|
||||
default 13
|
||||
|
||||
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_CALIBRATION_V1_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
|
|
@ -628,6 +628,11 @@ void rtc_dig_clk8m_enable(void);
|
|||
*/
|
||||
void rtc_dig_clk8m_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Get whether the rtc digital 8M clock is enabled
|
||||
*/
|
||||
bool rtc_dig_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Calculate the real clock value after the clock calibration
|
||||
*
|
||||
|
@ -703,7 +708,7 @@ typedef struct {
|
|||
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
|
||||
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
|
||||
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
|
||||
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
|
||||
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
|
||||
.wdt_flashboot_mod_en = 0, \
|
||||
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
|
||||
|
@ -717,7 +722,7 @@ typedef struct {
|
|||
: !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 \
|
||||
: RTC_CNTL_DBIAS_1V00, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.deep_slp_reject = 1, \
|
||||
.light_slp_reject = 1 \
|
||||
};
|
||||
|
|
|
@ -96,6 +96,7 @@
|
|||
/*!< RTC */
|
||||
#define SOC_ADC_RTC_MIN_BITWIDTH (13)
|
||||
#define SOC_ADC_RTC_MAX_BITWIDTH (13)
|
||||
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
|
||||
|
||||
/*!< Calibration */
|
||||
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
|
||||
|
|
|
@ -275,6 +275,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
|
|||
int
|
||||
default 12
|
||||
|
||||
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ADC_CALIBRATION_V1_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
|
|
@ -571,6 +571,11 @@ void rtc_dig_clk8m_enable(void);
|
|||
*/
|
||||
void rtc_dig_clk8m_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Get whether the rtc digital 8M clock is enabled
|
||||
*/
|
||||
bool rtc_dig_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Calculate the real clock value after the clock calibration
|
||||
*
|
||||
|
@ -655,7 +660,7 @@ typedef struct {
|
|||
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
|
||||
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
|
||||
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
|
||||
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
|
||||
.int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
|
||||
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
|
||||
.wdt_flashboot_mod_en = 0, \
|
||||
|
@ -668,7 +673,7 @@ typedef struct {
|
|||
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
|
||||
: RTC_CNTL_DBIAS_SLP, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
.deep_slp_reject = 1, \
|
||||
.light_slp_reject = 1 \
|
||||
};
|
||||
|
|
|
@ -90,6 +90,7 @@
|
|||
/*!< RTC */
|
||||
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
|
||||
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
|
||||
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
|
||||
|
||||
/*!< Calibration */
|
||||
#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
|
||||
|
|
Ładowanie…
Reference in New Issue