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Merge branch 'feature/support_efuse_for_esp32c6' into 'master' 

efuse: Updates efuse table for esp32c6

See merge request espressif/esp-idf!22400
pull/8835/merge
morris 2023-03-06 15:33:11 +08:00
rodzic d7a390049d a0408f7324
commit cc2068684f
10 zmienionych plików z 1259 dodań i 898 usunięć
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5
.gitlab/ci/host-test.yml
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@ -230,6 +230,11 @@ test_efuse_table_on_host_esp32h2:
variables:
IDF_TARGET: esp32h2
test_efuse_table_on_host_esp32c6:
extends: .test_efuse_table_on_host_template
variables:
IDF_TARGET: esp32c6
test_efuse_table_on_host_esp32h4:
extends: .test_efuse_table_on_host_template
variables:

59
components/efuse/esp32c6/esp_efuse_rtc_calib.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -17,59 +17,20 @@ int esp_efuse_rtc_calib_get_ver(void)
uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
{
assert(version == 1);
// Currently calibration is not supported on ESP32-C6, IDF-5236
(void) version;
(void) adc_unit;
const esp_efuse_desc_t** init_code_efuse;
assert(atten < 4);
if (atten == 0) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0;
} else if (atten == 1) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1;
} else if (atten == 2) {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2;
} else {
init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3;
}
int init_code_size = esp_efuse_get_field_size(init_code_efuse);
assert(init_code_size == 10);
uint32_t init_code = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size));
return init_code + 1000; // version 1 logic
(void) atten;
return 0;
}
esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv)
{
const esp_efuse_desc_t** cal_vol_efuse;
uint32_t calib_vol_expected_mv;
if (version != 1) {
return ESP_ERR_INVALID_ARG;
}
if (atten >= 4) {
return ESP_ERR_INVALID_ARG;
}
if (atten == 0) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0;
calib_vol_expected_mv = 400;
} else if (atten == 1) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1;
calib_vol_expected_mv = 550;
} else if (atten == 2) {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2;
calib_vol_expected_mv = 750;
} else {
cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3;
calib_vol_expected_mv = 1370;
}
assert(cal_vol_efuse[0]->bit_count == 10);
uint32_t cal_vol = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count));
*out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol);
*out_vol_mv = calib_vol_expected_mv;
// Currently calibration is not supported on ESP32-C6, IDF-5236
(void) version;
(void) atten;
(void) out_digi;
(void) out_vol_mv;
return ESP_OK;
}

975
components/efuse/esp32c6/esp_efuse_table.c
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Plik diff jest za duży Load Diff

301
components/efuse/esp32c6/esp_efuse_table.csv
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@ -1,163 +1,152 @@
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
# | ... | | | #
# | EFUSE_BLK10)| | | #
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
# | EFUSE_BLK1 | | | #
# | ...) | | | #
##########################################################################
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
# !!!!!!!!!!! #
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
# After editing this file, run the command manually "idf.py efuse-common-table"
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# EFUSE_RD_REPEAT_DATA BLOCK #
##############################
# EFUSE_RD_WR_DIS_REG #
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 1, 1, Write protection for SWAP_UART_SDIO_EN
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_USB_JTAG DIS_DOWNLOAD_ICACHE DIS_USB_SERIAL_JTAG DIS_FORCE_DOWNLOAD DIS_TWAI DIS_JTAG_SEL_ENABLE SOFT_DIS_JTAG DIS_PADJTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, Write protection for SEC_DPA_LEVEL
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_DIRECT_BOOT DIS_USB_PRINT DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROLFLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE,EFUSE_BLK0, 19, 1, Write protection for SECURE_BOOT_DISABLE_FAST_WAKE
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
# This file was generated by regtools.py based on the efuses.yaml file with the version: 1e4bcfa6a8578358a827410c1c8c243e
# EFUSE_RD_REPEAT_DATA0_REG #
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, Swap pad of uart and sdio.
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, Disable USB_SERIAL_JTAG
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_SPI_DOWNLOAD_MSPI, EFUSE_BLK0, 45, 1, Represents whether the SPI0 controller is disabled in boot_mode_download
DIS_TWAI, EFUSE_BLK0, 46, 1, Disable TWAI function
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, Set these bits to soft disable JTAG (odd number 1 means disable). JTAG can be enabled in HMAC module.
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Hard disable JTAG. JTAG is disabled permanently.
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes.
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio
# EFUSE_RD_REPEAT_DATA1_REG #
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
# EFUSE_RD_REPEAT_DATA2_REG #
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, Configures the clock random divide mode to determine the DPA security level
CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, Represents whether defense against DPA attack is enabled
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
# EFUSE_RD_REPEAT_DATA3_REG #
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, Disable direct boot mode
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, Represents whether print from USB-Serial-JTAG during ROM boot is disabled
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Represents whether the USB-Serial-JTAG download func- tion is disabled
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable secure download mode
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SYS_VERSION BLOCK #
#######################
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
MAC_EXT, EFUSE_BLK1, 48, 8, Extend MAC addr [0]
, EFUSE_BLK1, 56, 8, Extend MAC addr [1]
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# SYS_DATA_PART1 BLOCK# - System configuration (TODO: IDF-6483) #
#######################
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
# RD_SYS_PART1_DATA4
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
# RD_SYS_PART1_DATA5
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3
################
USER_DATA, EFUSE_BLK3, 0, 256, User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
################
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
# AUTO CONFIG DIG&RTC DBIAS (TODO: IDF-6483)#
################
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO
V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20
V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20
DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt
THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 1, 1, [] wr_dis of CRYPT_DPA_ENABLE
WR_DIS.SWAP_UART_SDIO_EN, EFUSE_BLK0, 2, 1, [] wr_dis of SWAP_UART_SDIO_EN
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_SERIAL_JTAG
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [WR_DIS.DPA_SEC_LEVEL] wr_dis of SEC_DPA_LEVEL
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 17, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
SWAP_UART_SDIO_EN, EFUSE_BLK0, 39, 1, [] Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 43, 1, [] Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [DPA_SEC_LEVEL] Represents the spa secure level by configuring the clock random divide mode
CRYPT_DPA_ENABLE, EFUSE_BLK0, 114, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [DIS_USB_PRINT] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Represents the version used by ESP-IDF anti-rollback feature
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 158, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
MAC_EXT, EFUSE_BLK1, 48, 16, [] Stores the extended bits of MAC address
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, []
WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, []
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR of BLOCK2
BLK_VERSION_MAJOR, EFUSE_BLK1, 123, 2, [] BLK_VERSION_MAJOR of BLOCK2
PKG_VERSION, EFUSE_BLK1, 125, 3, [] Package version
FLASH_CAP, EFUSE_BLK1, 128, 3, []
FLASH_TEMP, EFUSE_BLK1, 131, 2, []
FLASH_VENDOR, EFUSE_BLK1, 133, 3, []
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

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162
components/efuse/esp32c6/include/esp_efuse_table.h
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 19131923372be226ce98d85f5a13f16a
// md5_digest_table 995934abe6c7e7366404f837e547bb3f
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -19,50 +19,113 @@ extern "C" {
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SWAP_UART_SDIO_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
#define ESP_EFUSE_WR_DIS_DPA_SEC_LEVEL ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
#define ESP_EFUSE_WR_DIS_DIS_USB_PRINT ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_SWAP_UART_SDIO_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_SPI_DOWNLOAD_MSPI[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
@ -75,12 +138,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
#define ESP_EFUSE_DPA_SEC_LEVEL ESP_EFUSE_SEC_DPA_LEVEL
extern const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
@ -88,6 +158,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
#define ESP_EFUSE_DIS_USB_PRINT ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
@ -96,38 +167,37 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[];
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
#ifdef __cplusplus
}

4
components/hal/esp32c6/efuse_hal.c
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -29,7 +29,7 @@ uint32_t efuse_hal_get_minor_chip_version(void)
void efuse_hal_set_timing(uint32_t apb_freq_hz)
{
(void) apb_freq_hz;
efuse_ll_set_pwr_off_num(0x190);
// keep the default values, no need to change it
}
void efuse_hal_read(void)

14
components/hal/esp32c6/include/hal/efuse_ll.h
Wyświetl plik

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -45,22 +45,16 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
return EFUSE.rd_repeat_data2.secure_boot_en;
}
// TODO: IDF-5341
// __attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void)
// {
// return EFUSE.rd_repeat_data3.err_rst_enable;
// }
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
return EFUSE.rd_mac_spi_sys_3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
return EFUSE.rd_mac_spi_sys_3.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
@ -70,7 +64,7 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_ver
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
return EFUSE.rd_mac_spi_sys_3.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)

17
components/soc/esp32c6/include/soc/efuse_defs.h 100644
Wyświetl plik

@ -0,0 +1,17 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#ifdef __cplusplus
}
#endif

231
components/soc/esp32c6/include/soc/efuse_reg.h
Wyświetl plik

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,6 +7,7 @@
#include <stdint.h>
#include "soc/soc.h"
#include "efuse_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -222,13 +223,13 @@ extern "C" {
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S)
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U
#define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13
/** EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0;
/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
#define EFUSE_DIS_CAN (BIT(14))
#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S)
#define EFUSE_DIS_CAN_V 0x00000001U
#define EFUSE_DIS_CAN_S 14
#define EFUSE_DIS_TWAI (BIT(14))
#define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
#define EFUSE_DIS_TWAI_V 0x00000001U
#define EFUSE_DIS_TWAI_S 14
/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
@ -411,27 +412,27 @@ extern "C" {
#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
#define EFUSE_KEY_PURPOSE_5_V 0x0000000FU
#define EFUSE_KEY_PURPOSE_5_S 12
/** EFUSE_DPA_SEC_LEVEL : RO; bitpos: [17:16]; default: 0;
/** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0;
* Represents the spa secure level by configuring the clock random divide mode.
*/
#define EFUSE_DPA_SEC_LEVEL 0x00000003U
#define EFUSE_DPA_SEC_LEVEL_M (EFUSE_DPA_SEC_LEVEL_V << EFUSE_DPA_SEC_LEVEL_S)
#define EFUSE_DPA_SEC_LEVEL_V 0x00000003U
#define EFUSE_DPA_SEC_LEVEL_S 16
/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [18]; default: 0;
* Reserved.
*/
#define EFUSE_RPT4_RESERVED2_1 (BIT(18))
#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U
#define EFUSE_RPT4_RESERVED2_1_S 18
/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1;
#define EFUSE_SEC_DPA_LEVEL 0x00000003U
#define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S)
#define EFUSE_SEC_DPA_LEVEL_V 0x00000003U
#define EFUSE_SEC_DPA_LEVEL_S 16
/** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [18]; default: 0;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
#define EFUSE_CRYPT_DPA_ENABLE (BIT(19))
#define EFUSE_CRYPT_DPA_ENABLE (BIT(18))
#define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S)
#define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U
#define EFUSE_CRYPT_DPA_ENABLE_S 19
#define EFUSE_CRYPT_DPA_ENABLE_S 18
/** EFUSE_RPT4_RESERVED2_1 : RO; bitpos: [19]; default: 1;
* Reserved.
*/
#define EFUSE_RPT4_RESERVED2_1 (BIT(19))
#define EFUSE_RPT4_RESERVED2_1_M (EFUSE_RPT4_RESERVED2_1_V << EFUSE_RPT4_RESERVED2_1_S)
#define EFUSE_RPT4_RESERVED2_1_V 0x00000001U
#define EFUSE_RPT4_RESERVED2_1_S 19
/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
* Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
*/
@ -482,14 +483,14 @@ extern "C" {
#define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S)
#define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U
#define EFUSE_DIS_DIRECT_BOOT_S 1
/** EFUSE_DIS_USB_PRINT : RO; bitpos: [2]; default: 0;
/** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
*/
#define EFUSE_DIS_USB_PRINT (BIT(2))
#define EFUSE_DIS_USB_PRINT_M (EFUSE_DIS_USB_PRINT_V << EFUSE_DIS_USB_PRINT_S)
#define EFUSE_DIS_USB_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_PRINT_S 2
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2))
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S)
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U
#define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2
/** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@ -585,13 +586,27 @@ extern "C" {
* BLOCK0 data register 5.
*/
#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
/** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:0]; default: 0;
* Reserved.
/** EFUSE_DISABLE_WAFER_VERSION_MAJOR : R; bitpos: [0]; default: 0;
* Disables check of wafer version major
*/
#define EFUSE_RPT4_RESERVED4_1 0x00FFFFFFU
#define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S)
#define EFUSE_RPT4_RESERVED4_1_V 0x00FFFFFFU
#define EFUSE_RPT4_RESERVED4_1_S 0
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(0))
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S)
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 0
/** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [1]; default: 0;
* Disables check of blk version major
*/
#define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(1))
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S)
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U
#define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 1
/** EFUSE_RESERVED_0_162 : R; bitpos: [23:2]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_0_162 0x003FFFFFU
#define EFUSE_RESERVED_0_162_M (EFUSE_RESERVED_0_162_V << EFUSE_RESERVED_0_162_S)
#define EFUSE_RESERVED_0_162_V 0x003FFFFFU
#define EFUSE_RESERVED_0_162_S 2
/** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0;
* Reserved.
*/
@ -661,25 +676,64 @@ extern "C" {
#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFFU
#define EFUSE_SPI_PAD_CONF_2_S 0
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
* Stores the first 14 bits of the zeroth part of system data.
/** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [21:18]; default: 0; */
#define EFUSE_WAFER_VERSION_MINOR 0x0000000FU
#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S)
#define EFUSE_WAFER_VERSION_MINOR_V 0x0000000FU
#define EFUSE_WAFER_VERSION_MINOR_S 18
/** EFUSE_WAFER_VERSION_MAJOR : R; bitpos: [23:22]; default: 0; */
#define EFUSE_WAFER_VERSION_MAJOR 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S)
#define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U
#define EFUSE_WAFER_VERSION_MAJOR_S 22
/** EFUSE_BLK_VERSION_MINOR : R; bitpos: [26:24]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_BLK_VERSION_MINOR 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S)
#define EFUSE_BLK_VERSION_MINOR_V 0x00000007U
#define EFUSE_BLK_VERSION_MINOR_S 24
/** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [28:27]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
#define EFUSE_BLK_VERSION_MAJOR 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S)
#define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U
#define EFUSE_BLK_VERSION_MAJOR_S 27
/** EFUSE_PKG_VERSION : R; bitpos: [31:29]; default: 0;
* Package version
*/
#define EFUSE_PKG_VERSION 0x00000007U
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
#define EFUSE_PKG_VERSION_V 0x00000007U
#define EFUSE_PKG_VERSION_S 29
/** EFUSE_RD_MAC_SPI_SYS_4_REG register
* BLOCK1 data register $n.
*/
#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the zeroth part of system data.
/** EFUSE_FLASH_CAP : R; bitpos: [2:0]; default: 0; */
#define EFUSE_FLASH_CAP 0x00000007U
#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S)
#define EFUSE_FLASH_CAP_V 0x00000007U
#define EFUSE_FLASH_CAP_S 0
/** EFUSE_FLASH_TEMP : R; bitpos: [4:3]; default: 0; */
#define EFUSE_FLASH_TEMP 0x00000003U
#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S)
#define EFUSE_FLASH_TEMP_V 0x00000003U
#define EFUSE_FLASH_TEMP_S 3
/** EFUSE_FLASH_VENDOR : R; bitpos: [7:5]; default: 0; */
#define EFUSE_FLASH_VENDOR 0x00000007U
#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S)
#define EFUSE_FLASH_VENDOR_V 0x00000007U
#define EFUSE_FLASH_VENDOR_S 5
/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_RESERVED_1_136 0x00FFFFFFU
#define EFUSE_RESERVED_1_136_M (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S)
#define EFUSE_RESERVED_1_136_V 0x00FFFFFFU
#define EFUSE_RESERVED_1_136_S 8
/** EFUSE_RD_MAC_SPI_SYS_5_REG register
* BLOCK1 data register $n.
@ -697,49 +751,49 @@ extern "C" {
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_0_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_S 0
/** EFUSE_RD_SYS_PART1_DATA1_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_1_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0
/** EFUSE_RD_SYS_PART1_DATA2_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_2_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0
/** EFUSE_RD_SYS_PART1_DATA3_REG register
* Register $n of BLOCK2 (system).
*/
#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_3_S 0
#define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S)
#define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU
#define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0
/** EFUSE_RD_SYS_PART1_DATA4_REG register
* Register $n of BLOCK2 (system).
@ -865,25 +919,39 @@ extern "C" {
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
#define EFUSE_USR_DATA6 0xFFFFFFFFU
#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
#define EFUSE_USR_DATA6_V 0xFFFFFFFFU
#define EFUSE_USR_DATA6_S 0
#define EFUSE_RESERVED_3_192 0x000000FFU
#define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S)
#define EFUSE_RESERVED_3_192_V 0x000000FFU
#define EFUSE_RESERVED_3_192_S 0
/** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
#define EFUSE_CUSTOM_MAC 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S)
#define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_S 8
/** EFUSE_RD_USR_DATA7_REG register
* Register $n of BLOCK3 (user).
*/
#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
#define EFUSE_USR_DATA7 0xFFFFFFFFU
#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
#define EFUSE_USR_DATA7_V 0xFFFFFFFFU
#define EFUSE_USR_DATA7_S 0
#define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S)
#define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU
#define EFUSE_CUSTOM_MAC_1_S 0
/** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_3_248 0x000000FFU
#define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S)
#define EFUSE_RESERVED_3_248_V 0x000000FFU
#define EFUSE_RESERVED_3_248_S 24
/** EFUSE_RD_KEY0_DATA0_REG register
* Register $n of BLOCK4 (KEY0).
@ -2172,9 +2240,6 @@ extern "C" {
#define EFUSE_OP_CODE_V 0x0000FFFFU
#define EFUSE_OP_CODE_S 0
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
/** EFUSE_STATUS_REG register
* eFuse status register.
*/

389
components/soc/esp32c6/include/soc/efuse_struct.h
Wyświetl plik

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -155,7 +155,7 @@ typedef union {
} efuse_pgm_check_value2_reg_t;
/** Group: ******** Registers */
/** Group: Read Data Register */
/** Type of rd_wr_dis register
* BLOCK0 data register 0.
*/
@ -213,10 +213,10 @@ typedef union {
* enabled. 1: disabled. 0: enabled.
*/
uint32_t spi_download_mspi_dis:1;
/** dis_can : RO; bitpos: [14]; default: 0;
/** dis_twai : RO; bitpos: [14]; default: 0;
* Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_can:1;
uint32_t dis_twai:1;
/** jtag_sel_enable : RO; bitpos: [15]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
@ -338,18 +338,18 @@ typedef union {
* Represents the purpose of Key5.
*/
uint32_t key_purpose_5:4;
/** dpa_sec_level : RO; bitpos: [17:16]; default: 0;
/** sec_dpa_level : RO; bitpos: [17:16]; default: 0;
* Represents the spa secure level by configuring the clock random divide mode.
*/
uint32_t dpa_sec_level:2;
/** rpt4_reserved2_1 : RO; bitpos: [18]; default: 0;
* Reserved.
*/
uint32_t rpt4_reserved2_1:1;
/** crypt_dpa_enable : RO; bitpos: [19]; default: 1;
uint32_t sec_dpa_level:2;
/** crypt_dpa_enable : RO; bitpos: [18]; default: 0;
* Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled.
*/
uint32_t crypt_dpa_enable:1;
/** rpt4_reserved2_1 : RO; bitpos: [19]; default: 1;
* Reserved.
*/
uint32_t rpt4_reserved2_1:1;
/** secure_boot_en : RO; bitpos: [20]; default: 0;
* Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled.
*/
@ -386,11 +386,11 @@ typedef union {
* Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled.
*/
uint32_t dis_direct_boot:1;
/** dis_usb_print : RO; bitpos: [2]; default: 0;
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled.
* 0: enabled.
*/
uint32_t dis_usb_print:1;
uint32_t dis_usb_serial_jtag_rom_print:1;
/** rpt4_reserved3_5 : RO; bitpos: [3]; default: 0;
* Reserved.
*/
@ -454,10 +454,22 @@ typedef union {
*/
typedef union {
struct {
/** disable_wafer_version_major : R; bitpos: [0]; default: 0;
* Disables check of wafer version major
*/
uint32_t disable_wafer_version_major:1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22; /*Reserved.*/
uint32_t reserved24:8; /*Reserved.*/
/** disable_blk_version_major : R; bitpos: [1]; default: 0;
* Disables check of blk version major
*/
uint32_t disable_blk_version_major:1;
/** reserved_0_162 : R; bitpos: [23:2]; default: 0;
* reserved
*/
uint32_t reserved_0_162:22;
/** rpt4_reserved4_0 : RO; bitpos: [31:24]; default: 0;
* Reserved.
*/
uint32_t rpt4_reserved4_0:8;
};
uint32_t val;
} efuse_rd_repeat_data4_reg_t;
@ -484,10 +496,10 @@ typedef union {
* Stores the high 16 bits of MAC address.
*/
uint32_t mac_1:16;
/** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0;
* Stores the zeroth part of SPI_PAD_CONF.
/** mac_ext : RO; bitpos: [31:16]; default: 0;
* Stores the extended bits of MAC address.
*/
uint32_t spi_pad_conf_0:16;
uint32_t mac_ext:16;
};
uint32_t val;
} efuse_rd_mac_spi_sys_1_reg_t;
@ -497,7 +509,14 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved:32;
/** mac_spi_reserved : RO; bitpos: [13:0]; default: 0;
* Reserved.
*/
uint32_t mac_spi_reserved:14;
/** spi_pad_conf_1 : RO; bitpos: [31:14]; default: 0;
* Stores the first part of SPI_PAD_CONF.
*/
uint32_t spi_pad_conf_1:18;
};
uint32_t val;
} efuse_rd_mac_spi_sys_2_reg_t;
@ -511,13 +530,22 @@ typedef union {
* Stores the second part of SPI_PAD_CONF.
*/
uint32_t spi_pad_conf_2:18;
uint32_t wafer_version_minor_low:3;
uint32_t pkg_version:3;
uint32_t blk_version_minor:3;
/** sys_data_part0_0 : RO; bitpos: [31:27]; default: 0;
* Stores the first 5 bits of the zeroth part of system data.
/** wafer_version_minor : R; bitpos: [21:18]; default: 0; */
uint32_t wafer_version_minor:4;
/** wafer_version_major : R; bitpos: [23:22]; default: 0; */
uint32_t wafer_version_major:2;
/** blk_version_minor : R; bitpos: [26:24]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
uint32_t sys_data_part0_0:5;
uint32_t blk_version_minor:3;
/** blk_version_major : R; bitpos: [28:27]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
uint32_t blk_version_major:2;
/** pkg_version : R; bitpos: [31:29]; default: 0;
* Package version
*/
uint32_t pkg_version:3;
};
uint32_t val;
} efuse_rd_mac_spi_sys_3_reg_t;
@ -527,7 +555,16 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved:32;
/** flash_cap : R; bitpos: [2:0]; default: 0; */
uint32_t flash_cap:3;
/** flash_temp : R; bitpos: [4:3]; default: 0; */
uint32_t flash_temp:2;
/** flash_vendor : R; bitpos: [7:5]; default: 0; */
uint32_t flash_vendor:3;
/** reserved_1_136 : R; bitpos: [31:8]; default: 0;
* reserved
*/
uint32_t reserved_1_136:24;
};
uint32_t val;
} efuse_rd_mac_spi_sys_4_reg_t;
@ -537,10 +574,10 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved1:23;
uint32_t wafer_version_minor_high:1;
uint32_t wafer_version_major:2;
uint32_t reserved2:6;
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the zeroth part of system data.
*/
uint32_t sys_data_part0_2:32;
};
uint32_t val;
} efuse_rd_mac_spi_sys_5_reg_t;
@ -550,10 +587,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
* Stores the zeroth 32 bits of the first part of system data.
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_0:32;
uint32_t optional_unique_id:32;
};
uint32_t val;
} efuse_rd_sys_part1_data0_reg_t;
@ -563,10 +600,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
* Stores the first 32 bits of the first part of system data.
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_1:32;
uint32_t optional_unique_id_1:32;
};
uint32_t val;
} efuse_rd_sys_part1_data1_reg_t;
@ -576,10 +613,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
* Stores the second 32 bits of the first part of system data.
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_2:32;
uint32_t optional_unique_id_2:32;
};
uint32_t val;
} efuse_rd_sys_part1_data2_reg_t;
@ -589,10 +626,10 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
* Stores the third 32 bits of the first part of system data.
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_3:32;
uint32_t optional_unique_id_3:32;
};
uint32_t val;
} efuse_rd_sys_part1_data3_reg_t;
@ -602,8 +639,10 @@ typedef union {
*/
typedef union {
struct {
uint32_t blk_version_major :2;
uint32_t reserved1:30;
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
* Stores the fourth 32 bits of the first part of system data.
*/
uint32_t sys_data_part1_4:32;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
@ -730,10 +769,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data6 : RO; bitpos: [31:0]; default: 0;
* Stores the sixth 32 bits of BLOCK3 (user).
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
uint32_t usr_data6:32;
uint32_t reserved_3_192:8;
/** custom_mac : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
uint32_t custom_mac:24;
};
uint32_t val;
} efuse_rd_usr_data6_reg_t;
@ -743,10 +786,14 @@ typedef union {
*/
typedef union {
struct {
/** usr_data7 : RO; bitpos: [31:0]; default: 0;
* Stores the seventh 32 bits of BLOCK3 (user).
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
uint32_t usr_data7:32;
uint32_t custom_mac_1:24;
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_3_248:8;
};
uint32_t val;
} efuse_rd_usr_data7_reg_t;
@ -1479,6 +1526,8 @@ typedef union {
uint32_t val;
} efuse_rd_sys_part2_data7_reg_t;
/** Group: Report Register */
/** Type of rd_repeat_err0 register
* Programming error record register 0 of BLOCK0.
*/
@ -1853,6 +1902,8 @@ typedef union {
uint32_t val;
} efuse_rd_rs_err1_reg_t;
/** Group: Configuration Register */
/** Type of clk register
* eFuse clcok configuration register.
*/
@ -1894,48 +1945,6 @@ typedef union {
uint32_t val;
} efuse_conf_reg_t;
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
uint32_t reserved_20:12;
};
uint32_t val;
} efuse_status_reg_t;
/** Type of cmd register
* eFuse command register.
*/
@ -1959,78 +1968,6 @@ typedef union {
uint32_t val;
} efuse_cmd_reg_t;
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WO; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Type of dac_conf register
* Controls the eFuse programming voltage.
*/
@ -2147,6 +2084,126 @@ typedef union {
uint32_t val;
} efuse_wr_tim_conf0_rs_bypass_reg_t;
/** Group: Status Register */
/** Type of status register
* eFuse status register.
*/
typedef union {
struct {
/** state : RO; bitpos: [3:0]; default: 0;
* Indicates the state of the eFuse state machine.
*/
uint32_t state:4;
/** otp_load_sw : RO; bitpos: [4]; default: 0;
* The value of OTP_LOAD_SW.
*/
uint32_t otp_load_sw:1;
/** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
* The value of OTP_VDDQ_C_SYNC2.
*/
uint32_t otp_vddq_c_sync2:1;
/** otp_strobe_sw : RO; bitpos: [6]; default: 0;
* The value of OTP_STROBE_SW.
*/
uint32_t otp_strobe_sw:1;
/** otp_csb_sw : RO; bitpos: [7]; default: 0;
* The value of OTP_CSB_SW.
*/
uint32_t otp_csb_sw:1;
/** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
* The value of OTP_PGENB_SW.
*/
uint32_t otp_pgenb_sw:1;
/** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
* The value of OTP_VDDQ_IS_SW.
*/
uint32_t otp_vddq_is_sw:1;
/** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0;
* Indicates the number of block valid bit.
*/
uint32_t blk0_valid_bit_cnt:10;
uint32_t reserved_20:12;
};
uint32_t val;
} efuse_status_reg_t;
/** Group: Interrupt Register */
/** Type of int_raw register
* eFuse raw interrupt register.
*/
typedef union {
struct {
/** read_done_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
* The raw bit signal for read_done interrupt.
*/
uint32_t read_done_int_raw:1;
/** pgm_done_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
* The raw bit signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_raw:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_raw_reg_t;
/** Type of int_st register
* eFuse interrupt status register.
*/
typedef union {
struct {
/** read_done_int_st : RO; bitpos: [0]; default: 0;
* The status signal for read_done interrupt.
*/
uint32_t read_done_int_st:1;
/** pgm_done_int_st : RO; bitpos: [1]; default: 0;
* The status signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_st:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_st_reg_t;
/** Type of int_ena register
* eFuse interrupt enable register.
*/
typedef union {
struct {
/** read_done_int_ena : R/W; bitpos: [0]; default: 0;
* The enable signal for read_done interrupt.
*/
uint32_t read_done_int_ena:1;
/** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
* The enable signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_ena:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_ena_reg_t;
/** Type of int_clr register
* eFuse interrupt clear register.
*/
typedef union {
struct {
/** read_done_int_clr : WO; bitpos: [0]; default: 0;
* The clear signal for read_done interrupt.
*/
uint32_t read_done_int_clr:1;
/** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
* The clear signal for pgm_done interrupt.
*/
uint32_t pgm_done_int_clr:1;
uint32_t reserved_2:30;
};
uint32_t val;
} efuse_int_clr_reg_t;
/** Group: Version Register */
/** Type of date register
* eFuse version register.
*/
@ -2162,7 +2219,7 @@ typedef union {
} efuse_date_reg_t;
typedef struct efuse_dev_t {
typedef struct {
volatile efuse_pgm_data0_reg_t pgm_data0;
volatile efuse_pgm_data1_reg_t pgm_data1;
volatile efuse_pgm_data2_reg_t pgm_data2;