kopia lustrzana https://github.com/espressif/esp-idf
esp_system: revert reset of systimer clk at startup
rodzic
aff0235e47
commit
cb5a8342d4
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@ -316,7 +316,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
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DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
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DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
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periph_ll_reset(PERIPH_SYSTIMER_MODULE);
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/* Enable RNG clock. */
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periph_module_enable(PERIPH_RNG_MODULE);
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