fix(wdt): changed ESP32-C3 WDT to use XTAL as clock

This clock is unchanged even when CPU/APB frequency changes (e.g. due to esp_pm),
which means timeout period is correct even after such a change.
pull/12276/head
Marius Vikhammer 2023-09-08 12:23:18 +08:00
rodzic b1e85404f1
commit ca99f55316
13 zmienionych plików z 74 dodań i 3 usunięć

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@ -13,10 +13,11 @@
#include "esp_rom_sys.h"
#include "esp_task_wdt.h"
#include "test_utils.h"
#include "soc/rtc.h"
#define TASK_WDT_TIMEOUT_MS 1000
static bool timeout_flag;
static volatile bool timeout_flag;
void esp_task_wdt_isr_user_handler(void)
{
@ -40,6 +41,41 @@ TEST_CASE("Task WDT task timeout", "[task_wdt]")
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit());
}
#if SOC_MWDT_SUPPORT_XTAL
#if CONFIG_IDF_TARGET_ESP32H2
#define TEST_CPU_FREQUENCY_MHZ 48
#else
#define TEST_CPU_FREQUENCY_MHZ 40
#endif
TEST_CASE("Task WDT task timeout - CPU Frequency changed", "[task_wdt]")
{
rtc_cpu_freq_config_t old_config, new_config;
rtc_clk_cpu_freq_get_config(&old_config);
TEST_ASSERT(rtc_clk_cpu_freq_mhz_to_config(TEST_CPU_FREQUENCY_MHZ, &new_config));
rtc_clk_cpu_freq_set_config(&new_config);
timeout_flag = false;
esp_task_wdt_config_t twdt_config = {
.timeout_ms = TASK_WDT_TIMEOUT_MS,
.idle_core_mask = 0,
.trigger_panic = false,
};
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_init(&twdt_config));
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_add(NULL));
/* Short delay to allow timeout to occur, if WDT depends on any of the clocks changed
then the timeout should be slower and test will fail */
esp_rom_delay_us(TASK_WDT_TIMEOUT_MS * 1000);
TEST_ASSERT_EQUAL(true, timeout_flag);
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_delete(NULL));
TEST_ASSERT_EQUAL(ESP_OK, esp_task_wdt_deinit());
rtc_clk_cpu_freq_set_config(&old_config);
}
#endif //SOC_MWDT_SUPPORT_XTAL
TEST_CASE("Task WDT inactive when no task to watch", "[task_wdt]")
{
/* Make sure a timeout is NOT trigger when we have no task to watch */

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@ -24,7 +24,7 @@ extern "C" {
#include "hal/misc.h"
/* Pre-calculated prescaler to achieve 500 ticks/us (MWDT1_TICKS_PER_US) when using default clock (MWDT_CLK_SRC_DEFAULT ) */
#define MWDT_LL_DEFAULT_CLK_PRESCALER 40000
#define MWDT_LL_DEFAULT_CLK_PRESCALER 20000
//Type check wdt_stage_action_t
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == TIMG_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");

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@ -539,6 +539,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 1
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
bool
default y

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@ -256,6 +256,9 @@
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (1U)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- eFuse CAPS----------------------------*/
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1
#define SOC_EFUSE_DIS_PAD_JTAG 1

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@ -763,6 +763,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_TWAI_CONTROLLER_NUM
int
default 1

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@ -335,7 +335,7 @@ typedef enum {
typedef enum {
MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MWDT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select APB as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////

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@ -339,6 +339,9 @@
#define SOC_TIMER_GROUP_SUPPORT_APB (1)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 1UL
#define SOC_TWAI_CLK_SUPPORT_APB 1

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@ -1007,6 +1007,10 @@ config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_TWAI_CONTROLLER_NUM
int
default 2

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@ -418,6 +418,9 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 2
#define SOC_TWAI_CLK_SUPPORT_XTAL 1

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@ -991,6 +991,10 @@ config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_TWAI_CONTROLLER_NUM
int
default 1

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@ -412,6 +412,9 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 1UL
#define SOC_TWAI_CLK_SUPPORT_XTAL 1

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@ -831,6 +831,10 @@ config SOC_TIMER_SUPPORT_ETM
bool
default y
config SOC_MWDT_SUPPORT_XTAL
bool
default y
config SOC_TWAI_CONTROLLER_NUM
int
default 2

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@ -414,6 +414,9 @@
#define SOC_TIMER_GROUP_TOTAL_TIMERS 4
#define SOC_TIMER_SUPPORT_ETM 1
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
/*-------------------------- TWAI CAPS ---------------------------------------*/
#define SOC_TWAI_CONTROLLER_NUM 2
#define SOC_TWAI_CLK_SUPPORT_XTAL 1