kopia lustrzana https://github.com/espressif/esp-idf
gpio: h2 support input hysteresis filter
wanlei
rodzic
c88efb7fa8
commit
c9bcec9212
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@ -239,6 +239,26 @@ int gpio_get_level(gpio_num_t gpio_num)
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return gpio_hal_get_level(gpio_context.gpio_hal, gpio_num);
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}
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#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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static esp_err_t gpio_hysteresis_enable(gpio_num_t gpio_num)
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{
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gpio_hal_hysteresis_soft_enable(gpio_context.gpio_hal, gpio_num, true);
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return ESP_OK;
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}
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static esp_err_t gpio_hysteresis_disable(gpio_num_t gpio_num)
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{
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gpio_hal_hysteresis_soft_enable(gpio_context.gpio_hal, gpio_num, false);
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return ESP_OK;
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}
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static esp_err_t gpio_hysteresis_by_efuse(gpio_num_t gpio_num)
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{
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gpio_hal_hysteresis_from_efuse(gpio_context.gpio_hal, gpio_num);
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return ESP_OK;
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}
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#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
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{
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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@ -386,6 +406,15 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
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gpio_intr_disable(io_num);
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}
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#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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if (pGPIOConfig->hys_ctrl_mode == GPIO_HYS_SOFT_ENABLE) {
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gpio_hysteresis_enable(io_num);
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} else if (pGPIOConfig->hys_ctrl_mode == GPIO_HYS_SOFT_DISABLE) {
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gpio_hysteresis_disable(io_num);
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} else {
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gpio_hysteresis_by_efuse(io_num);
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}
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#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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/* By default, all the pins have to be configured as GPIO pins. */
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gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO);
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}
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@ -48,6 +48,9 @@ typedef struct {
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gpio_pullup_t pull_up_en; /*!< GPIO pull-up */
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gpio_pulldown_t pull_down_en; /*!< GPIO pull-down */
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gpio_int_type_t intr_type; /*!< GPIO interrupt type */
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#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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gpio_hys_ctrl_mode_t hys_ctrl_mode; /*!< GPIO hysteresis: hysteresis filter on slope input */
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#endif
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} gpio_config_t;
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/**
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@ -12,6 +12,10 @@ if(CONFIG_SOC_SDM_SUPPORTED)
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list(APPEND srcs "test_sdm.c")
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endif()
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if(CONFIG_SOC_GPIO_SUPPORT_PIN_HYS_FILTER)
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list(APPEND srcs "test_hysteresis.c")
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endif()
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# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
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# the component can be registered as WHOLE_ARCHIVE
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idf_component_register(SRCS ${srcs}
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@ -1,26 +1,19 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "unity.h"
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#include "unity_test_runner.h"
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#include "unity_test_utils.h"
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#include "esp_heap_caps.h"
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// Some resources are lazy allocated in the driver, the threshold is left for that case
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#define TEST_MEMORY_LEAK_THRESHOLD (-300)
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#define TEST_MEMORY_LEAK_THRESHOLD (300)
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static size_t before_free_8bit;
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static size_t before_free_32bit;
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static void check_leak(size_t before_free, size_t after_free, const char *type)
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{
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ssize_t delta = after_free - before_free;
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printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
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TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
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}
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void setUp(void)
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{
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before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
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@ -31,8 +24,9 @@ void tearDown(void)
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{
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size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
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size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
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check_leak(before_free_8bit, after_free_8bit, "8BIT");
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check_leak(before_free_32bit, after_free_32bit, "32BIT");
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printf("\n");
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unity_utils_check_leak(before_free_8bit, after_free_8bit, "8BIT", TEST_MEMORY_LEAK_THRESHOLD);
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unity_utils_check_leak(before_free_32bit, after_free_32bit, "32BIT", TEST_MEMORY_LEAK_THRESHOLD);
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}
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void app_main(void)
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@ -0,0 +1,75 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "unity.h"
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#include "driver/gpio.h"
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/**
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* NOTE: To run this special feature test case, a slope analog signal is needed.
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* A simple RC circuit used here to formate pin switches to continuos slop signal.
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*
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* +---------+
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* | |
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* | (intr)26|----------------+ C:1000uF
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* | | | ++ +
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* | (wave)27|______+-----+___+___|| |_____
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* | | +-----+ || | |
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* | ESP32 | R:10k ++ + |
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* | | |
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* | GND|------------------------------+
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* +---------+
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*
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* or you can connect your slop signals from signal generator to ESP32 pin
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* which enabled the hysteresis feature directly to have a test.
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**/
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static void test_gpio_hysteresis_intr_handler(void *args)
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{
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esp_rom_printf("%d\n", ++*((uint32_t *)args));
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}
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// This case is now tested only manually
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TEST_CASE("GPIO Input hysteresis filter", "[gpio_filter][timeout=50][ignore]")
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{
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const gpio_num_t TEST_HYS_IO = 26;
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const gpio_num_t TEST_WAVE_IO = 27;
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uint32_t intr_cnt=0;
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gpio_config_t gpio_cfg = {
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.pin_bit_mask = 1 << TEST_WAVE_IO,
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.mode = GPIO_MODE_OUTPUT,
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.pull_down_en = GPIO_PULLDOWN_ENABLE,
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};
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TEST_ESP_OK(gpio_config(&gpio_cfg));
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gpio_cfg.pin_bit_mask = 1 << TEST_HYS_IO;
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gpio_cfg.mode = GPIO_MODE_INPUT;
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gpio_cfg.intr_type = GPIO_INTR_ANYEDGE;
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gpio_cfg.hys_ctrl_mode = GPIO_HYS_SOFT_ENABLE;
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TEST_ESP_OK(gpio_config(&gpio_cfg));
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gpio_install_isr_service(0);
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gpio_isr_handler_add(TEST_HYS_IO, test_gpio_hysteresis_intr_handler, &intr_cnt);
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// generate 5 rising and falling slopes to test gpio interrupt
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for (uint8_t i=0; i<5; i++) {
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printf("----falling %dth\n", i);
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gpio_set_level(TEST_WAVE_IO, 0);
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vTaskDelay(1500);
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printf("----rising %dth\n", i);
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gpio_set_level(TEST_WAVE_IO, 1);
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vTaskDelay(1500);
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}
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gpio_isr_handler_remove(TEST_HYS_IO);
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gpio_uninstall_isr_service();
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// should shot ISR exactly 10 times
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TEST_ASSERT_UINT32_WITHIN(1, 10, intr_cnt);
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}
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@ -226,6 +226,50 @@ static inline void gpio_ll_pin_filter_disable(gpio_dev_t *hw, uint32_t gpio_num)
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PIN_FILTER_DIS(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Select gpio hysteresis control by efuse.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pin_input_hysteresis_ctrl_sel_efuse(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_HYS_EN_SEL_EFUSE(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Select gpio hysteresis control by software.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pin_input_hysteresis_ctrl_sel_soft(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_HYS_EN_SEL_SOFT(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Enable gpio hysteresis if controlled by software.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pin_input_hysteresis_enable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_HYS_SOFT_ENABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Disable gpio hysteresis if controlled by software.
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*
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* @param hw Peripheral GPIO hardware instance address.
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* @param gpio_num GPIO number
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*/
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static inline void gpio_ll_pin_input_hysteresis_disable(gpio_dev_t *hw, uint32_t gpio_num)
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{
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PIN_HYS_SOFT_DISABLE(IO_MUX_GPIO0_REG + (gpio_num * 4));
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}
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/**
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* @brief Disable output mode on GPIO.
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*
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@ -29,3 +29,16 @@ void gpio_hal_intr_disable(gpio_hal_context_t *hal, uint32_t gpio_num)
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gpio_ll_clear_intr_status_high(hal->dev, BIT(gpio_num - 32));
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}
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}
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#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable)
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{
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if (enable) {
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gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num);
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gpio_ll_pin_input_hysteresis_enable(hal->dev, gpio_num);
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} else {
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gpio_ll_pin_input_hysteresis_ctrl_sel_soft(hal->dev, gpio_num);
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gpio_ll_pin_input_hysteresis_disable(hal->dev, gpio_num);
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}
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}
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#endif //SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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@ -485,6 +485,25 @@ void gpio_hal_sleep_pupd_config_unapply(gpio_hal_context_t *hal, uint32_t gpio_n
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*/
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#define gpio_hal_iomux_func_sel(pin_name, func) gpio_ll_iomux_func_sel(pin_name, func)
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#if SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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/**
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* @brief Control gpio hysteresis enable/disable by software.
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*
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* @param hal Context of the HAL layer
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* @param gpio_num GPIO number
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* @param enable enable or disable the hysteresis
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*/
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void gpio_hal_hysteresis_soft_enable(gpio_hal_context_t *hal, uint32_t gpio_num, bool enable);
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/**
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* @brief Set gpio hysteresis enable/disable by efuse.
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*
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* @param hal Context of the HAL layer
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* @param gpio_num GPIO number
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*/
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#define gpio_hal_hysteresis_from_efuse(hal, gpio_num) gpio_ll_pin_input_hysteresis_ctrl_sel_efuse((hal)->dev, gpio_num)
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#endif // SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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#ifdef __cplusplus
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}
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#endif
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@ -473,6 +473,15 @@ typedef enum {
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GPIO_DRIVE_CAP_MAX,
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} gpio_drive_cap_t;
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/**
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* @brief Available option for configuring hysteresis feature of GPIOs
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*/
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typedef enum {
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GPIO_HYS_CTRL_EFUSE = 0, /*!< Pad input hysteresis ctrl by efuse */
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GPIO_HYS_SOFT_ENABLE = 1, /*!< Pad input hysteresis enable by software */
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GPIO_HYS_SOFT_DISABLE = 2, /*!< Pad input hysteresis disable by software */
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} gpio_hys_ctrl_mode_t;
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#ifdef __cplusplus
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}
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#endif
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@ -303,6 +303,10 @@ config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
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bool
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default y
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config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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bool
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default y
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config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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int
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default 8
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@ -69,6 +69,24 @@
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#define FILTER_EN_V 1
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#define FILTER_EN_S 15
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/* HYS_EN : R/W; bitpos: [16]; default: 0;
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* Software enables hysteresis function for the pad.
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* 1: Hysteresis enabled. 0: Hysteresis disabled.
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*/
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#define HYS_EN (BIT(16))
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#define HYS_EN_M (HYS_EN_V << HYS_EN_S)
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#define HYS_EN_V 0x00000001
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#define HYS_EN_S 16
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/* HYS_SEL : R/W; bitpos: [17]; default: 0;
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* Select enabling signals of the pad from software and efuse hardware.
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* 1: Select enabling siganl from software.
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* 0: Select enabling signal from efuse hardware.
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*/
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#define HYS_SEL (BIT(17))
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#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S)
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#define HYS_SEL_V 0x00000001
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#define HYS_SEL_S 17
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#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
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@ -90,6 +108,10 @@
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#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
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#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
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#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
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#define PIN_HYS_EN_SEL_EFUSE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_SEL)
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#define PIN_HYS_EN_SEL_SOFT(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_SEL)
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#define PIN_HYS_SOFT_ENABLE(PIN_NAME) REG_SET_BIT(PIN_NAME, HYS_EN)
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#define PIN_HYS_SOFT_DISABLE(PIN_NAME) REG_CLR_BIT(PIN_NAME, HYS_EN)
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#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
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#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
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@ -156,6 +156,7 @@
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#define SOC_GPIO_PORT 1U
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#define SOC_GPIO_PIN_COUNT 28
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#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
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#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
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#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8
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// GPIO peripheral has the ETM extension
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@ -21,6 +21,7 @@ GPIO Summary
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:SOC_ULP_SUPPORTED: - The :doc:`Ultra Low Power co-processor <../../api-reference/system/ulp>` is running
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- Analog functions such as ADC/DAC/etc are in use.
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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GPIO Glitch Filter
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@ -50,6 +51,20 @@ GPIO Summary
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The glitch filter is disabled by default, and can be enabled by calling :cpp:func:`gpio_glitch_filter_enable`. To recycle the filter, you can call :cpp:func:`gpio_del_glitch_filter`. Please note, before deleting the filter, you should disable it first by calling :cpp:func:`gpio_glitch_filter_disable`.
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.. only:: SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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GPIO Hysteresis Filter
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----------------------
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{IDF_TARGET_NAME} support the hardware hysteresis of the input pin, which can reduce the GPIO interrupt shoot by accident due to unstable sampling when the input voltage is near the critical of logic 0 and 1, especially when the input logic level conversion is slow or the voltage setup time is too long.
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Each pin can enable hysteresis function independently. By default, it controlled by eFuse and been closed, but it can also be enabled or disabled by software manually. You can select the hysteresis control mode by configuring :cpp:member:`gpio_config_t::hys_ctrl_mode`.
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.. note::
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When the hysteresis function is controlled by eFuse, this feature can still be controlled independently for each pin, you need to `burn the eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ to enable the hysteresis function on specific GPIO additionally.
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Application Example
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-------------------
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@ -21,6 +21,7 @@ GPIO 汇总
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:SOC_ULP_SUPPORTED: - :doc:`超低功耗协处理器 (ULP) <../../api-reference/system/ulp>` 运行时
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- 使用 ADC/DAC 等模拟功能时
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.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
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GPIO 毛刺过滤器
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@ -50,6 +51,20 @@ GPIO 汇总
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毛刺过滤器默认关闭，可调用 :cpp:func:`gpio_glitch_filter_enable` 使能过滤器。如需回收这个过滤器，可以调用 :cpp:func:`gpio_del_glitch_filter` 函数。在回收句柄前，请确保过滤器处于关闭状态，否则需调用 :cpp:func:`gpio_glitch_filter_disable`。
|
||||
|
||||
|
||||
.. only:: SOC_GPIO_SUPPORT_PIN_HYS_FILTER
|
||||
|
||||
GPIO 迟滞过滤器
|
||||
---------------
|
||||
|
||||
{IDF_TARGET_NAME} 支持输入引脚的硬件迟滞，这可以减少由于输入电压在逻辑 0、1 临界值附近时采样不稳定造成的 GPIO 中断误触，尤其是当输入逻辑电平转换较慢，电平建立时间较长时。
|
||||
|
||||
每个引脚可以独立启用迟滞功能。默认情况下，它由 eFuse 控制，且处于关闭状态，但也可以由软件控制启用或禁用。您可以通过配置 :cpp:member:`gpio_config_t::hys_ctrl_mode` 来选择迟滞控制模式。
|
||||
|
||||
.. note::
|
||||
|
||||
当迟滞功能由 eFuse 控制时，仍然可以独立的控制每个引脚的该功能，您需要 `烧断 eFuse <https://docs.espressif.com/projects/esptool/en/latest/esp32/espefuse/index.html>`_ ，以在特定 GPIO上 启用迟滞功能。
|
||||
|
||||
|
||||
应用示例
|
||||
-------------------
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue