From 6dffac74e9cbde8e695c44daa647fc6d28312146 Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Wed, 4 Jan 2023 08:11:52 +0100 Subject: [PATCH 1/3] heap: Fix IRAM level 2 starting address The IRAM level 2 address should start at the same address as DRAM level 2 and not DRAM level 3. --- components/heap/port/esp32c6/memory_layout.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c index 201059bfd6..39118f3260 100644 --- a/components/heap/port/esp32c6/memory_layout.c +++ b/components/heap/port/esp32c6/memory_layout.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -69,7 +69,7 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor const soc_memory_region_t soc_memory_regions[] = { { 0x40800000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40800000}, //D/IRAM level0, can be used as trace memory { 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory - { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level2, can be used as trace memory + { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level2, can be used as trace memory { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP From 9b2f6f01d6c0d189a38a08b5bf9e1b78494e7aef Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Thu, 5 Jan 2023 08:19:08 +0100 Subject: [PATCH 2/3] tools: Fix esp32c2_data_info.yaml memory values to match documentation --- tools/idf_size_yaml/esp32c6_data_info.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/idf_size_yaml/esp32c6_data_info.yaml b/tools/idf_size_yaml/esp32c6_data_info.yaml index 93b1978fa3..a454a6e063 100644 --- a/tools/idf_size_yaml/esp32c6_data_info.yaml +++ b/tools/idf_size_yaml/esp32c6_data_info.yaml @@ -8,10 +8,10 @@ DRAM: secondary_address: 0x40800000 CACHE_I: primary_address: 0x42000000 - length: 0x800000 + length: 0x1000000 CACHE_D: primary_address: 0x42000000 - length: 0x800000 + length: 0x1000000 RTC_SLOW_D: # TODO: IDF-5667 Better to rename to LP_RAM primary_address: 0x50000000 length: 0x4000 From b8a498845132874a50035abbf9c911914e9b9977 Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Thu, 5 Jan 2023 09:02:19 +0100 Subject: [PATCH 3/3] soc: Update calculation of TWAI 1/2 base addresses --- components/soc/esp32c6/include/soc/soc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32c6/include/soc/soc.h b/components/soc/esp32c6/include/soc/soc.h index f35d791da1..27eb71e1e4 100644 --- a/components/soc/esp32c6/include/soc/soc.h +++ b/components/soc/esp32c6/include/soc/soc.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -26,7 +26,7 @@ #define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 -#define REG_TWAI_BASE(i) (DR_REG_TWAI_BASE + (i) * 0x2000) // TWAI0 and TWAI1 +#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr)