diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml
index 4a7ab0ebe0..a8bd3cdde8 100644
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
@@ -211,6 +211,26 @@ example_test_pytest_esp32c3_flash_encryption:
     TARGET: ESP32C3
     ENV_MARKER: flash_encryption
 
+example_test_pytest_esp32s2_deepsleep: # Temp tag, will be removed IDF-5213
+  extends:
+    - .pytest_examples_dir_template
+    - .rules:test:example_test-esp32s2
+  needs:
+    - build_pytest_examples_esp32s2
+  variables:
+    TARGET: ESP32S2
+    ENV_MARKER: deepsleep_temp_tag
+
+example_test_pytest_esp32s3_deepsleep: # Temp tag, will be removed IDF-5213
+  extends:
+    - .pytest_examples_dir_template
+    - .rules:test:example_test-esp32s3
+  needs:
+    - build_pytest_examples_esp32s3
+  variables:
+    TARGET: ESP32S3
+    ENV_MARKER: deepsleep_temp_tag
+
 .pytest_components_dir_template:
   extends: .pytest_template
   variables:
diff --git a/components/ulp/ulp_fsm/ulp.c b/components/ulp/ulp_fsm/ulp.c
index 5d138af12b..f6c21b3dd1 100644
--- a/components/ulp/ulp_fsm/ulp.c
+++ b/components/ulp/ulp_fsm/ulp.c
@@ -42,12 +42,6 @@ static const char* TAG = "ulp";
 
 esp_err_t ulp_run(uint32_t entry_point)
 {
-#if CONFIG_IDF_TARGET_ESP32S3
-    ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip");
-    abort();
-// Fix in-progress: DIG-160
-#endif //CONFIG_IDF_TARGET_ESP32S3
-
 #if CONFIG_IDF_TARGET_ESP32
     // disable ULP timer
     CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c
index 588d13bef5..501d04c3d9 100644
--- a/components/ulp/ulp_riscv/ulp_riscv.c
+++ b/components/ulp/ulp_riscv/ulp_riscv.c
@@ -48,17 +48,14 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
 {
     esp_err_t ret = ESP_OK;
 
-#if CONFIG_IDF_TARGET_ESP32S3
-    ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip");
-    abort();
-// Fix in-progress: DIG-160
-#endif //CONFIG_IDF_TARGET_ESP32S3
 
 #if CONFIG_IDF_TARGET_ESP32S2
-    /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
+    /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
+    esp_rom_delay_us(20);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
-    /* The coprocessor cpu trap signal doesnt have a stable reset value,
+     /* The coprocessor cpu trap signal doesnt have a stable reset value,
        force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
 
@@ -75,14 +72,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
     ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source);
 
 #elif CONFIG_IDF_TARGET_ESP32S3
-    /* The coprocessor cpu trap signal doesnt have a stable reset value,
-       force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
+    /* Reset COCPU when power on. */
     SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
+    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
     esp_rom_delay_us(20);
     CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
-
-    /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
-    SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
 
     /* Disable ULP timer */
     CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
diff --git a/components/ulp/ulp_riscv/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_riscv_utils.c
index c14d08aeac..75e48982c0 100644
--- a/components/ulp/ulp_riscv/ulp_riscv_utils.c
+++ b/components/ulp/ulp_riscv/ulp_riscv_utils.c
@@ -13,7 +13,7 @@
 void ulp_riscv_rescue_from_monitor(void)
 {
     /* Rescue RISCV from monitor state. */
-    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN);
 }
 
 void ulp_riscv_wakeup_main_processor(void)
diff --git a/examples/system/deep_sleep/README.md b/examples/system/deep_sleep/README.md
index 4c098a244b..04109c6348 100644
--- a/examples/system/deep_sleep/README.md
+++ b/examples/system/deep_sleep/README.md
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
-| ----------------- | ----- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-S3 | ESP32-C3 |
+| ----------------- | ----- | -------- | -------- | -------- |
 
 # Deep Sleep Example
 
diff --git a/examples/system/deep_sleep/pytest_deep_sleep.py b/examples/system/deep_sleep/pytest_deep_sleep.py
index 8d9bc4040f..161747773e 100644
--- a/examples/system/deep_sleep/pytest_deep_sleep.py
+++ b/examples/system/deep_sleep/pytest_deep_sleep.py
@@ -9,15 +9,8 @@ from pytest_embedded import Dut
 
 touch_wake_up_support = ['esp32', 'esp32s2']
 
-CONFIGS = [
-    pytest.param('esp32_singlecore', marks=[pytest.mark.esp32]),
-    pytest.param('generic', marks=[pytest.mark.esp32, pytest.mark.esp32c3]),  # Disabled for now: IDF-4801
-]
 
-
-@pytest.mark.parametrize('config', CONFIGS, indirect=True)
-@pytest.mark.generic
-def test_deep_sleep(dut: Dut) -> None:
+def deep_sleep_test(dut: Dut) -> None:
 
     def expect_enable_deep_sleep_touch() -> None:
         # different targets configure different wake pin(s)
@@ -64,3 +57,26 @@ def test_deep_sleep(dut: Dut) -> None:
     # Check that it measured 2xxxxms in deep sleep, i.e at least 20 seconds:
     dut.expect(r'Wake up from timer. Time spent in deep sleep: 2\d{4}ms', timeout=2)
     expect_enable_deep_sleep()
+
+
+CONFIGS = [
+    pytest.param('esp32_singlecore', marks=[pytest.mark.esp32]),
+    pytest.param('basic', marks=[pytest.mark.esp32, pytest.mark.esp32c3]),
+]
+
+
+@pytest.mark.parametrize('config', CONFIGS, indirect=True)
+@pytest.mark.generic
+def test_deep_sleep(dut: Dut) -> None:
+    deep_sleep_test(dut)
+
+
+CONFIGS_S2_S3 = [
+    pytest.param('basic', marks=[pytest.mark.esp32s2, pytest.mark.esp32s3]),  # S2/S3 runner on isolated runners for now, IDF-XX
+]
+
+
+@pytest.mark.parametrize('config', CONFIGS_S2_S3, indirect=True)
+@pytest.mark.deepsleep_temp_tag
+def test_deep_sleep_s2_s3(dut: Dut) -> None:
+    deep_sleep_test(dut)
diff --git a/examples/system/deep_sleep/sdkconfig.ci.generic b/examples/system/deep_sleep/sdkconfig.ci.basic
similarity index 100%
rename from examples/system/deep_sleep/sdkconfig.ci.generic
rename to examples/system/deep_sleep/sdkconfig.ci.basic
diff --git a/examples/system/ulp_fsm/ulp/CMakeLists.txt b/examples/system/ulp_fsm/ulp/CMakeLists.txt
index 02e0567b23..05e73f3ef7 100644
--- a/examples/system/ulp_fsm/ulp/CMakeLists.txt
+++ b/examples/system/ulp_fsm/ulp/CMakeLists.txt
@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(IDF_TARGET STREQUAL "esp32s3")
-    #IDF-4514
-    message(FATAL_ERROR "\n **** ERROR **** : DO NOT BUILD AND RUN THIS APP ON ESP32-S3 AS IT MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_example)
diff --git a/examples/system/ulp_riscv/ds18b20_onewire/CMakeLists.txt b/examples/system/ulp_riscv/ds18b20_onewire/CMakeLists.txt
index f99acbc8db..64f23a6847 100644
--- a/examples/system/ulp_riscv/ds18b20_onewire/CMakeLists.txt
+++ b/examples/system/ulp_riscv/ds18b20_onewire/CMakeLists.txt
@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_ds18b20_example)
diff --git a/examples/system/ulp_riscv/ds18b20_onewire/sdkconfig.defaults b/examples/system/ulp_riscv/ds18b20_onewire/sdkconfig.defaults
index 2fde2935c8..a28f71162e 100644
--- a/examples/system/ulp_riscv/ds18b20_onewire/sdkconfig.defaults
+++ b/examples/system/ulp_riscv/ds18b20_onewire/sdkconfig.defaults
@@ -1,4 +1,3 @@
-CONFIG_IDF_TARGET="esp32s2"
 # Enable ULP
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_RISCV=y
diff --git a/examples/system/ulp_riscv/gpio/CMakeLists.txt b/examples/system/ulp_riscv/gpio/CMakeLists.txt
index b56b27ff9f..e36a9e69fc 100644
--- a/examples/system/ulp_riscv/gpio/CMakeLists.txt
+++ b/examples/system/ulp_riscv/gpio/CMakeLists.txt
@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_example)
diff --git a/examples/system/ulp_riscv/gpio/README.md b/examples/system/ulp_riscv/gpio/README.md
index 7339e0d3a2..bfe9e639b7 100644
--- a/examples/system/ulp_riscv/gpio/README.md
+++ b/examples/system/ulp_riscv/gpio/README.md
@@ -1,12 +1,12 @@
-| Supported Targets | ESP32-S2 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 
 # ULP-RISC-V simple example with GPIO Polling:
 
 This example demonstrates how to program the ULP-RISC-V coprocessor to poll a gpio and wakeup the main CPU when it changes its state;
 
 ULP program written in C can be found across `ulp/main.c`. The build system compiles and links this program, converts it into binary format, and embeds it into the .rodata section of the ESP-IDF application.
- 
+
 At runtime, the application running inside the main CPU loads ULP program into the `RTC_SLOW_MEM` memory region using `ulp_riscv_load_binary` function. The main code then configures the ULP wakeup period and starts the coprocessor by using `ulp_riscv_run`. Once the ULP program is started, it runs periodically, with the period set by the main program. The main program enables ULP wakeup source and puts the chip into deep sleep mode.
 
 When the ULP program finds an state changing in the pin, it saves the current state and sends a wakeup signal to the main CPU.
@@ -19,13 +19,13 @@ In this example the input signal is connected to GPIO0. Note that this pin was c
 ## Example output
 
 ```
-Not a ULP wakeup, initializing it! 
+Not a ULP wakeup, initializing it!
 Entering in deep sleep
 
 ...
 
-ULP-RISC-V woke up the main CPU! 
-ULP-RISC-V read changes in GPIO_0 current is: High 
+ULP-RISC-V woke up the main CPU!
+ULP-RISC-V read changes in GPIO_0 current is: High
 Entering in deep sleep
 
 ```
\ No newline at end of file
diff --git a/examples/system/ulp_riscv/gpio/pytest_ulp_riscv_gpio.py b/examples/system/ulp_riscv/gpio/pytest_ulp_riscv_gpio.py
index f57382f0f8..6f588e48ad 100644
--- a/examples/system/ulp_riscv/gpio/pytest_ulp_riscv_gpio.py
+++ b/examples/system/ulp_riscv/gpio/pytest_ulp_riscv_gpio.py
@@ -1,18 +1,24 @@
 # SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 
+import time
+
 import pexpect
 import pytest
 from pytest_embedded import Dut
 
 
 @pytest.mark.esp32s2
-@pytest.mark.generic
+@pytest.mark.esp32s3
+@pytest.mark.deepsleep_temp_tag
 def test_ulp_riscv_gpio(dut: Dut) -> None:
 
     dut.expect_exact('Not a ULP-RISC-V wakeup, initializing it!')
     dut.expect_exact('Entering in deep sleep')
 
+    # Give the chip time to enter deepsleep
+    time.sleep(1)
+
     # Run two times to make sure device sleep
     # and wake up properly
     for i in range(0, 2):
diff --git a/examples/system/ulp_riscv/gpio/sdkconfig.defaults b/examples/system/ulp_riscv/gpio/sdkconfig.defaults
index 2fde2935c8..a28f71162e 100644
--- a/examples/system/ulp_riscv/gpio/sdkconfig.defaults
+++ b/examples/system/ulp_riscv/gpio/sdkconfig.defaults
@@ -1,4 +1,3 @@
-CONFIG_IDF_TARGET="esp32s2"
 # Enable ULP
 CONFIG_ULP_COPROC_ENABLED=y
 CONFIG_ULP_COPROC_RISCV=y
diff --git a/examples/system/ulp_riscv/gpio_interrupt/CMakeLists.txt b/examples/system/ulp_riscv/gpio_interrupt/CMakeLists.txt
index b56b27ff9f..e36a9e69fc 100644
--- a/examples/system/ulp_riscv/gpio_interrupt/CMakeLists.txt
+++ b/examples/system/ulp_riscv/gpio_interrupt/CMakeLists.txt
@@ -2,11 +2,5 @@
 # in this exact order for cmake to work correctly
 cmake_minimum_required(VERSION 3.16)
 
-if(NOT IDF_TARGET STREQUAL "esp32s2")
-    #IDF-4514
-    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
-    return()
-endif()
-
 include($ENV{IDF_PATH}/tools/cmake/project.cmake)
 project(ulp_riscv_example)
diff --git a/examples/system/ulp_riscv/gpio_interrupt/README.md b/examples/system/ulp_riscv/gpio_interrupt/README.md
index 5fd432b6fc..eec681dd68 100644
--- a/examples/system/ulp_riscv/gpio_interrupt/README.md
+++ b/examples/system/ulp_riscv/gpio_interrupt/README.md
@@ -1,6 +1,5 @@
-| Supported Targets | ESP32-S2 |
-| ----------------- | -------- |
-
+| Supported Targets | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 # ULP-RISC-V simple example with GPIO Interrupt:
 
 This example demonstrates how to program the ULP-RISC-V coprocessor to wake up from a RTC IO interrupt, instead of waking periodically from the ULP timer.
diff --git a/pytest.ini b/pytest.ini
index 32e659777e..003fefc3e2 100644
--- a/pytest.ini
+++ b/pytest.ini
@@ -44,7 +44,7 @@ markers =
   ethernet_flash_8m: ethernet runner with 8mb flash
   wifi: wifi runner
   wifi_bt: wifi runner with bluetooth
-  deepsleep: deepsleep runners
+  deepsleep_temp_tag: temporary env for running potentially harmfull deepsleep related tests
 
   # multi-dut markers
   multi_dut_generic: tests should be run on generic runners, at least have two duts connected.