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ble: use modem_clock api to set clock on ESP32-C6

pull/11524/head
Shen Weilong 2023-05-17 20:02:21 +08:00
rodzic d7a141f3ea
commit c7f357523a
1 zmienionych plików z 6 dodań i 37 usunięć
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43
components/bt/controller/esp32h2/bt.c
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@ -562,32 +562,6 @@ void controller_sleep_deinit(void)
#endif //CONFIG_PM_ENABLE
}
#define REG_MODEM_SYSCON_BASE 0x600A5400
#define REG_MODEM_LPCON_BASE 0x600AD000
#define DR_REG_MODEM_SYSCON_BASE REG_MODEM_SYSCON_BASE
#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4)
#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x10)
#define MODEM_LPCON_CLK_CONF_REG (REG_MODEM_LPCON_BASE + 0x0008)
#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (REG_MODEM_LPCON_BASE + 0x000C)
#include "hal/clk_tree_ll.h"
static void enable_chip_clk(void)
{
WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF_REG,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_SYSCON_CLK_CONF1_REG,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
// SET BIT for BLE RTC clk
SET_PERI_REG_MASK(PMU_HP_SLEEP_LP_CK_POWER_REG,PMU_HP_SLEEP_XPD_XTAL32K);
// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_SEL_XTAL32K,1);
// REG_SET_FIELD(LP_CLKRST_LPPERI_REG,LP_CLKRST_LP_BLETIMER_DIV_NUM,0);
/* For chip */
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_REG ,0xFFFFFFFF);
WRITE_PERI_REG(MODEM_LPCON_CLK_CONF_FORCE_ON_REG ,0xFFFFFFFF);
}
esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
{
uint8_t mac[6];
@ -612,8 +586,6 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
return ret;
}
enable_chip_clk();
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
@ -653,9 +625,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
#endif // CONFIG_BT_NIMBLE_ENABLED
/* Enable BT-related clocks */
// modem_clock_module_enable(PERIPH_BT_MODULE);
// modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
// esp_phy_modem_init();
modem_clock_module_enable(PERIPH_BT_MODULE);
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL, 249);
esp_phy_enable();
esp_btbb_enable();
s_ble_active = true;
@ -697,9 +668,8 @@ free_controller:
ble_controller_deinit();
esp_btbb_disable();
esp_phy_disable();
// esp_phy_modem_deinit();
// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
// modem_clock_module_disable(PERIPH_BT_MODULE);
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
modem_clock_module_disable(PERIPH_BT_MODULE);
#if CONFIG_BT_NIMBLE_ENABLED
ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
#endif // CONFIG_BT_NIMBLE_ENABLED
@ -728,9 +698,8 @@ esp_err_t esp_bt_controller_deinit(void)
esp_phy_disable();
s_ble_active = false;
}
// esp_phy_modem_deinit();
// modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
// modem_clock_module_disable(PERIPH_BT_MODULE);
modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
modem_clock_module_disable(PERIPH_BT_MODULE);
ble_controller_deinit();