kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'esp32c2/IDRAM_PMP_split' into 'master'
esp32c2: Enable IRAM/DRAM split using PMP Closes IDF-3837 See merge request espressif/esp-idf!18156pull/9062/head
commit
c6e2ae76a9
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@ -5,6 +5,29 @@
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*/
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#include <assert.h>
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#include "esp_cpu.h"
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#include "sdkconfig.h"
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#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
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extern int _iram_end;
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extern int _data_start;
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#define IRAM_END (int)&_iram_end
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#define DRAM_START (int)&_data_start
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#else
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#define IRAM_END SOC_DIRAM_IRAM_HIGH
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#define DRAM_START SOC_DIRAM_DRAM_LOW
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#endif
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#ifdef BOOTLOADER_BUILD
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// Without L bit set
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#define CONDITIONAL_NONE 0x0
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#define CONDITIONAL_RX PMP_R | PMP_X
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#define CONDITIONAL_RW PMP_R | PMP_W
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#else
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// With L bit set
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#define CONDITIONAL_NONE NONE
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#define CONDITIONAL_RX RX
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#define CONDITIONAL_RW RW
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#endif
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void esp_cpu_configure_region_protection(void)
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{
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@ -19,47 +42,71 @@ void esp_cpu_configure_region_protection(void)
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* 3) 3-15 PMPADDR entries be hardcoded to fixed value, 0-2 PMPADDR be programmed to split ID SRAM
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* as IRAM/DRAM. All PMPCFG entryies be available.
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*
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* 4) Ideally, PMPADDR 0-2 entries should be configured twice, once during bootloader startup and another during app startup.
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* However, the CPU currently always executes in machine mode and to enforce these permissions in machine mode, we need
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* to set the Lock (L) bit but if set once, it cannot be reconfigured. So, we only configure 0-2 PMPADDR during app startup.
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*/
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const unsigned NONE = PMP_L ;
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const unsigned NONE = PMP_L ;
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const unsigned R = PMP_L | PMP_R;
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const unsigned X = PMP_L | PMP_X;
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const unsigned RW = PMP_L | PMP_R | PMP_W;
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const unsigned RX = PMP_L | PMP_R | PMP_X;
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const unsigned RWX = PMP_L | PMP_R | PMP_W | PMP_X;
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/* There are 3 configuration scenarios for PMPADDR 0-2
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*
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* 1. Bootloader build:
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* - We cannot set the lock bit as we need to reconfigure it again for the application.
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* We configure PMPADDR 0-1 to cover entire valid IRAM range and PMPADDR 2-3 to cover entire valid DRAM range.
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*
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* 2. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT enabled
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* - We split the SRAM into IRAM and DRAM such that IRAM region cannot be accessed via DBUS
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* and DRAM region cannot be accessed via IBUS. We use _iram_end and _data_start markers to set the boundaries.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* 3. Application build with CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT disabled
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* - The IRAM-DRAM split is not enabled so we just need to ensure that access to only valid address ranges are successful
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* so for that we set PMPADDR 0-1 to cover entire valid IRAM range and PMPADDR 2-3 to cover entire DRAM region.
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* We also lock these entries so the R/W/X permissions are enforced even for machine mode
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*
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* PMPADDR 3-15 are hard-coded and are appicable to both, bootloader and application. So we configure and lock
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* these during BOOTLOADER build itself. During application build, reconfiguration of these PMPADDR entries
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* are silently ignored by the CPU
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*/
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// 1. IRAM
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PMP_ENTRY_SET(0,SOC_DIRAM_IRAM_LOW, NONE);
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PMP_ENTRY_SET(1,SOC_DIRAM_IRAM_HIGH, PMP_TOR|RWX); //TODO IRAM/DRAM spilt address
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PMP_ENTRY_SET(0, SOC_DIRAM_IRAM_LOW, CONDITIONAL_NONE);
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PMP_ENTRY_SET(1, IRAM_END, PMP_TOR | CONDITIONAL_RX);
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// 2. DRAM
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PMP_ENTRY_SET(2,SOC_DIRAM_DRAM_LOW, NONE); //TODO IRAM/DRAM spilt address
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PMP_ENTRY_CFG_SET(3,PMP_TOR|RW);
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PMP_ENTRY_SET(2, DRAM_START, CONDITIONAL_NONE);
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PMP_ENTRY_CFG_SET(3, PMP_TOR | CONDITIONAL_RW);
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// 3. Debug region
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PMP_ENTRY_CFG_SET(4,PMP_NAPOT|RWX);
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PMP_ENTRY_CFG_SET(4, PMP_NAPOT | RWX);
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// 4. DROM (flash dcache)
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PMP_ENTRY_CFG_SET(5,PMP_NAPOT|R);
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PMP_ENTRY_CFG_SET(5, PMP_NAPOT | R);
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// 5. DROM_MASK
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PMP_ENTRY_CFG_SET(6,NONE);
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PMP_ENTRY_CFG_SET(7,PMP_TOR|R);
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PMP_ENTRY_CFG_SET(6, NONE);
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PMP_ENTRY_CFG_SET(7, PMP_TOR | R);
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// 6. IROM_MASK
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PMP_ENTRY_CFG_SET(8,NONE);
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PMP_ENTRY_CFG_SET(9,PMP_TOR|RX);
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PMP_ENTRY_CFG_SET(8, NONE);
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PMP_ENTRY_CFG_SET(9, PMP_TOR | RX);
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// 7. IROM (flash icache)
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PMP_ENTRY_CFG_SET(10,PMP_NAPOT|RX);
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PMP_ENTRY_CFG_SET(10, PMP_NAPOT | RX);
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// 8. Peripheral addresses
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PMP_ENTRY_CFG_SET(11,PMP_NAPOT|RW);
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PMP_ENTRY_CFG_SET(11, PMP_NAPOT | RW);
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// 9. SRAM (used as ICache)
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PMP_ENTRY_CFG_SET(12,PMP_NAPOT|X);
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PMP_ENTRY_CFG_SET(12, PMP_NAPOT | X);
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// 10. no access to any address below(0x0-0xFFFF_FFFF)
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PMP_ENTRY_CFG_SET(13,PMP_NA4|NONE);// last 4 bytes(0xFFFFFFFC)
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PMP_ENTRY_CFG_SET(14,NONE);
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PMP_ENTRY_CFG_SET(15,PMP_TOR|NONE);
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PMP_ENTRY_CFG_SET(13, PMP_NA4 | NONE);// last 4 bytes(0xFFFFFFFC)
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PMP_ENTRY_CFG_SET(14, NONE);
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PMP_ENTRY_CFG_SET(15, PMP_TOR | NONE);
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}
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@ -117,6 +117,18 @@ menu "ESP System Settings"
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menu "Memory protection"
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config ESP_SYSTEM_PMP_IDRAM_SPLIT
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bool "Enable IRAM/DRAM split protection"
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depends on SOC_CPU_IDRAM_SPLIT_USING_PMP
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default "y"
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help
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If enabled, the CPU watches all the memory access and raises an exception in case
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of any memory violation. This feature automatically splits
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the SRAM memory, using PMP, into data and instruction segments and sets Read/Execute permissions
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for the instruction part (below given splitting address) and Read/Write permissions
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for the data part (above the splitting address). The memory protection is effective
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on all access through the IRAM0 and DRAM0 buses.
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config ESP_SYSTEM_MEMPROT_DEPCHECK
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bool
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default y if IDF_TARGET_ESP32S2
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@ -151,6 +151,10 @@ config SOC_CPU_WATCHPOINT_SIZE
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hex
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default 0x80000000
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config SOC_CPU_IDRAM_SPLIT_USING_PMP
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bool
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default y
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config SOC_GDMA_GROUPS
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int
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default 1
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@ -80,6 +80,8 @@
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#define SOC_CPU_WATCHPOINT_SIZE 0x80000000 // bytes
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#define SOC_CPU_IDRAM_SPLIT_USING_PMP 1
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/*-------------------------- GDMA CAPS -------------------------------------*/
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#define SOC_GDMA_GROUPS (1U) // Number of GDMA groups
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#define SOC_GDMA_PAIRS_PER_GROUP (1U) // Number of GDMA pairs in each group
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