diff --git a/components/driver/esp32c3/adc.c b/components/driver/esp32c3/adc.c index 81b30860c9..4dbd4f7056 100644 --- a/components/driver/esp32c3/adc.c +++ b/components/driver/esp32c3/adc.c @@ -605,86 +605,6 @@ esp_err_t adc_digi_controller_config(const adc_digi_config_t *config) return ESP_OK; } -esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config) -{ - if (adc_unit & ADC_UNIT_1) { - return ESP_ERR_NOT_SUPPORTED; - } - ADC_ENTER_CRITICAL(); - adc_hal_arbiter_config(config); - ADC_EXIT_CRITICAL(); - return ESP_OK; -} - -/** - * @brief Set ADC module controller. - * There are five SAR ADC controllers: - * Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes; - * Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep; - * the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2. - * - * @note Only ADC2 support arbiter to switch controllers automatically. Access to the ADC is based on the priority of the controller. - * @note For ADC1, Controller access is mutually exclusive. - * - * @param adc_unit ADC unit. - * @param ctrl ADC controller, Refer to `adc_controller_t`. - * - * @return - * - ESP_OK Success - */ -esp_err_t adc_set_controller(adc_unit_t adc_unit, adc_controller_t ctrl) -{ - adc_arbiter_t config = {0}; - adc_arbiter_t cfg = ADC_ARBITER_CONFIG_DEFAULT(); - - if (adc_unit & ADC_UNIT_1) { - adc_hal_set_controller(ADC_NUM_1, ctrl); - } - if (adc_unit & ADC_UNIT_2) { - adc_hal_set_controller(ADC_NUM_2, ctrl); - switch (ctrl) { - case ADC2_CTRL_FORCE_PWDET: - config.pwdet_pri = 2; - config.mode = ADC_ARB_MODE_SHIELD; - adc_hal_arbiter_config(&config); - adc_hal_set_controller(ADC_NUM_2, ADC2_CTRL_PWDET); - break; - case ADC2_CTRL_FORCE_RTC: - config.rtc_pri = 2; - config.mode = ADC_ARB_MODE_SHIELD; - adc_hal_arbiter_config(&config); - adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC); - break; - case ADC2_CTRL_FORCE_DIG: - config.dig_pri = 2; - config.mode = ADC_ARB_MODE_SHIELD; - adc_hal_arbiter_config(&config); - adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_DIG); - break; - default: - adc_hal_arbiter_config(&cfg); - break; - } - } - return ESP_OK; -} - -/** - * @brief Reset FSM of adc digital controller. - * - * @return - * - ESP_OK Success - */ -esp_err_t adc_digi_reset(void) -{ - ADC_ENTER_CRITICAL(); - adc_hal_digi_reset(); - adc_hal_digi_clear_pattern_table(ADC_NUM_1); - adc_hal_digi_clear_pattern_table(ADC_NUM_2); - ADC_EXIT_CRITICAL(); - return ESP_OK; -} - /*************************************/ /* Digital controller filter setting */ /*************************************/ @@ -742,90 +662,6 @@ esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable) return ESP_OK; } -/**************************************/ -/* Digital controller intr setting */ -/**************************************/ - -esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) -{ - ADC_ENTER_CRITICAL(); - if (adc_unit & ADC_UNIT_1) { - adc_hal_digi_intr_enable(ADC_NUM_1, intr_mask); - } - if (adc_unit & ADC_UNIT_2) { - adc_hal_digi_intr_enable(ADC_NUM_2, intr_mask); - } - ADC_EXIT_CRITICAL(); - return ESP_OK; -} - -esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) -{ - ADC_ENTER_CRITICAL(); - if (adc_unit & ADC_UNIT_1) { - adc_hal_digi_intr_disable(ADC_NUM_1, intr_mask); - } - if (adc_unit & ADC_UNIT_2) { - adc_hal_digi_intr_disable(ADC_NUM_2, intr_mask); - } - ADC_EXIT_CRITICAL(); - return ESP_OK; -} - -esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask) -{ - ADC_ENTER_CRITICAL(); - if (adc_unit & ADC_UNIT_1) { - adc_hal_digi_intr_clear(ADC_NUM_1, intr_mask); - } - if (adc_unit & ADC_UNIT_2) { - adc_hal_digi_intr_clear(ADC_NUM_2, intr_mask); - } - ADC_EXIT_CRITICAL(); - return ESP_OK; -} - -uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit) -{ - uint32_t ret = 0; - ADC_ENTER_CRITICAL(); - if (adc_unit & ADC_UNIT_1) { - ret = adc_hal_digi_get_intr_status(ADC_NUM_1); - } - if (adc_unit & ADC_UNIT_2) { - ret = adc_hal_digi_get_intr_status(ADC_NUM_2); - } - ADC_EXIT_CRITICAL(); - return ret; -} - -static bool s_isr_registered = 0; -static intr_handle_t s_adc_isr_handle = NULL; - -esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags) -{ - ADC_CHECK((fn != NULL), "Parameter error", ESP_ERR_INVALID_ARG); - ADC_CHECK(s_isr_registered == 0, "ADC ISR have installed, can not install again", ESP_FAIL); - - esp_err_t ret = esp_intr_alloc(ETS_APB_ADC_INTR_SOURCE, intr_alloc_flags, fn, arg, &s_adc_isr_handle); - if (ret == ESP_OK) { - s_isr_registered = 1; - } - return ret; -} - -esp_err_t adc_digi_isr_deregister(void) -{ - esp_err_t ret = ESP_FAIL; - if (s_isr_registered) { - ret = esp_intr_free(s_adc_isr_handle); - if (ret == ESP_OK) { - s_isr_registered = 0; - } - } - return ret; -} - /*--------------------------------------------------------------- RTC controller setting ---------------------------------------------------------------*/ diff --git a/components/driver/esp32c3/include/driver/adc.h b/components/driver/esp32c3/include/driver/adc.h index 463778a3a9..2678a9e61e 100644 --- a/components/driver/esp32c3/include/driver/adc.h +++ b/components/driver/esp32c3/include/driver/adc.h @@ -22,25 +22,6 @@ extern "C" { /*--------------------------------------------------------------- Common setting ---------------------------------------------------------------*/ - -/** - * @brief Config ADC module arbiter. - * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority, - * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data. - * - * @note Only ADC2 support arbiter. - * @note Default priority: Wi-Fi > RTC > Digital; - * @note In normal use, there is no need to call this interface to config arbiter. - * - * @param adc_unit ADC unit. - * @param config Refer to `adc_arbiter_t`. - * - * @return - * - ESP_OK Success - * - ESP_ERR_NOT_SUPPORTED ADC unit not support arbiter. - */ -esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config); - /*************************************/ /* Digital controller filter setting */ /*************************************/ @@ -114,78 +95,6 @@ esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monit */ esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable); -/**************************************/ -/* Digital controller intr setting */ -/**************************************/ - -/** - * @brief Enable interrupt of adc digital controller by bitmask. - * - * @param adc_unit ADC unit. - * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. - * - * @return - * - ESP_OK Success - */ -esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); - -/** - * @brief Disable interrupt of adc digital controller by bitmask. - * - * @param adc_unit ADC unit. - * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. - * - * @return - * - ESP_OK Success - */ -esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); - -/** - * @brief Clear interrupt of adc digital controller by bitmask. - * - * @param adc_unit ADC unit. - * @param intr_mask Interrupt bitmask. See ``adc_digi_intr_t``. - * - * @return - * - ESP_OK Success - */ -esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask); - -/** - * @brief Get interrupt status mask of adc digital controller. - * - * @param adc_unit ADC unit. - * @return - * - intr Interrupt bitmask, See ``adc_digi_intr_t``. - */ -uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit); - -/** - * @brief Register ADC interrupt handler, the handler is an ISR. - * The handler will be attached to the same CPU core that this function is running on. - * - * @param fn Interrupt handler function. - * @param arg Parameter for handler function - * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred) - * ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. - * - * @return - * - ESP_OK Success - * - ESP_ERR_NOT_FOUND Can not find the interrupt that matches the flags. - * - ESP_ERR_INVALID_ARG Function pointer error. - */ -esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags); - -/** - * @brief Deregister ADC interrupt handler, the handler is an ISR. - * - * @return - * - ESP_OK Success - * - ESP_ERR_INVALID_ARG hander error. - * - ESP_FAIL ISR not be registered. - */ -esp_err_t adc_digi_isr_deregister(void); - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/adc_hal.c b/components/hal/esp32c3/adc_hal.c index 105dff6490..bec18db5fb 100644 --- a/components/hal/esp32c3/adc_hal.c +++ b/components/hal/esp32c3/adc_hal.c @@ -45,6 +45,18 @@ void adc_hal_digi_deinit(void) adc_hal_deinit(); } +/** + * - Set ADC digital controller clock division factor. The clock is divided from `APLL` or `APB` clock. + * Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1). + * - Enable clock and select clock source for ADC digital controller. + */ +static void adc_hal_digi_clk_config(void) +{ + //Here we set the clock divider factor to make the digital clock to 5M Hz + adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT); + adc_ll_digi_controller_clk_enable(0); +} + void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) { //only one pattern table is supported on C3, but LL still needs one argument. @@ -74,31 +86,6 @@ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg) adc_hal_digi_clk_config(); } -void adc_hal_digi_clk_config(void) -{ - //Here we set the clock divider factor to make the digital clock to 5M Hz - adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT); - adc_ll_digi_controller_clk_enable(0); -} - -/** - * Enable digital controller to trigger the measurement. - */ -void adc_hal_digi_enable(void) -{ - adc_ll_digi_dma_enable(); - adc_ll_digi_trigger_enable(); -} - -/** - * Disable digital controller to trigger the measurement. - */ -void adc_hal_digi_disable(void) -{ - adc_ll_digi_trigger_disable(); - adc_ll_digi_dma_disable(); -} - static void filter_update(adc_digi_filter_idx_t idx) { //ESP32-C3 has no enable bit, the filter will be enabled when the filter channel is configured diff --git a/components/hal/esp32c3/include/hal/adc_hal.h b/components/hal/esp32c3/include/hal/adc_hal.h index 2f6fffeaad..9993f9e8d9 100644 --- a/components/hal/esp32c3/include/hal/adc_hal.h +++ b/components/hal/esp32c3/include/hal/adc_hal.h @@ -46,41 +46,6 @@ void adc_hal_digi_deinit(void); */ void adc_hal_digi_controller_config(const adc_digi_config_t *cfg); -/** - * ADC Digital controller output data invert or not. - * - * @param adc_n ADC unit. - * @param inv_en data invert or not. - */ -#define adc_hal_digi_output_invert(adc_n, inv_en) adc_ll_digi_output_invert(adc_n, inv_en) - -/** - * Sets the number of interval clock cycles for the digital controller to trigger the measurement. - * - * @note The trigger interval should not be less than the sampling time of the SAR ADC. - * @param cycle The number of clock cycles for the trigger interval. The unit is the divided clock. Range: 40 ~ 4095. - */ -#define adc_hal_digi_set_trigger_interval(cycle) adc_ll_digi_set_trigger_interval(cycle) - -/** - * Enable digital controller to trigger the measurement. - */ -void adc_hal_digi_enable(void); - -/** - * Disable digital controller to trigger the measurement. - */ -void adc_hal_digi_disable(void); - -/** - * Set ADC digital controller clock division factor. The clock divided from `APLL` or `APB` clock. - * Enable clock and select clock source for ADC digital controller. - * Expression: controller_clk = APLL/APB * (div_num + div_a / div_b + 1). - * - * @param clk Refer to `adc_digi_clk_t`. - */ -void adc_hal_digi_clk_config(void); - /** * Reset adc digital controller filter. * @@ -132,63 +97,6 @@ void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monito */ void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable); -/** - * Enable interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -#define adc_hal_digi_intr_enable(adc_n, intr) adc_ll_digi_intr_enable(adc_n, intr) - -/** - * Disable interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -#define adc_hal_digi_intr_disable(adc_n, intr) adc_ll_digi_intr_disable(adc_n, intr) - -/** - * Clear interrupt of adc digital controller by bitmask. - * - * @param adc_n ADC unit. - * @param intr Interrupt bitmask. - */ -#define adc_hal_digi_intr_clear(adc_n, intr) adc_ll_digi_intr_clear(adc_n, intr) - -/** - * Get interrupt status mask of adc digital controller. - * - * @param adc_n ADC unit. - * @return - * - intr Interrupt bitmask. - */ -#define adc_hal_digi_get_intr_status(adc_n) adc_ll_digi_get_intr_status(adc_n) - - -/** - * Set DMA eof num of adc digital controller. - * If the number of measurements reaches `dma_eof_num`, then `dma_in_suc_eof` signal is generated. - * - * @param num eof num of DMA. - */ -#define adc_hal_digi_dma_set_eof_num(num) adc_ll_digi_dma_set_eof_num(num) - -/** - * Enable output data to DMA from adc digital controller. - */ -#define adc_hal_digi_dma_enable() adc_ll_digi_dma_enable() - -/** - * Disable output data to DMA from adc digital controller. - */ -#define adc_hal_digi_dma_disable() adc_ll_digi_dma_disable() - -/** - * Reset adc digital controller. - */ -#define adc_hal_digi_reset() adc_ll_digi_reset() - /*--------------------------------------------------------------- Common setting ---------------------------------------------------------------*/ diff --git a/components/hal/esp32c3/include/hal/adc_ll.h b/components/hal/esp32c3/include/hal/adc_ll.h index ecbface280..5ee33aed07 100644 --- a/components/hal/esp32c3/include/hal/adc_ll.h +++ b/components/hal/esp32c3/include/hal/adc_ll.h @@ -29,7 +29,6 @@ extern "C" { #endif -#define ADC_LL_ADC2_CHANNEL_MAX 1 #define ADC_LL_CLKM_DIV_NUM_DEFAULT 15 #define ADC_LL_CLKM_DIV_B_DEFAULT 1 #define ADC_LL_CLKM_DIV_A_DEFAULT 0 @@ -74,7 +73,7 @@ typedef enum { ADC2_CTRL_FORCE_PWDET = 3, /*!