diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h
index 0cfb05a266..f7cb496b4b 100644
--- a/components/hal/esp32c3/include/hal/i2s_ll.h
+++ b/components/hal/esp32c3/include/hal/i2s_ll.h
@@ -487,7 +487,7 @@ static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(output) when receiving left channel data
  */
-static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->tx_conf.tx_ws_idle_pol = ws_pol_level;
 }
@@ -498,7 +498,7 @@ static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(input) when receiving left channel data
  */
-static inline void i2s_rx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->rx_conf.rx_ws_idle_pol = ws_pol_level;
 }
diff --git a/components/hal/esp32h2/include/hal/i2s_ll.h b/components/hal/esp32h2/include/hal/i2s_ll.h
index 365362479c..38a700c5f6 100644
--- a/components/hal/esp32h2/include/hal/i2s_ll.h
+++ b/components/hal/esp32h2/include/hal/i2s_ll.h
@@ -488,7 +488,7 @@ static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(output) when receiving left channel data
  */
-static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->tx_conf.tx_ws_idle_pol = ws_pol_level;
 }
@@ -499,7 +499,7 @@ static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(input) when receiving left channel data
  */
-static inline void i2s_rx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->rx_conf.rx_ws_idle_pol = ws_pol_level;
 }
diff --git a/components/hal/esp32s3/include/hal/i2s_ll.h b/components/hal/esp32s3/include/hal/i2s_ll.h
index 366d498746..c1b3ae7f50 100644
--- a/components/hal/esp32s3/include/hal/i2s_ll.h
+++ b/components/hal/esp32s3/include/hal/i2s_ll.h
@@ -490,7 +490,7 @@ static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(output) when receiving left channel data
  */
-static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_tx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->tx_conf.tx_ws_idle_pol = ws_pol_level;
 }
@@ -501,7 +501,7 @@ static inline void i2s_tx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
  * @param hw Peripheral I2S hardware instance address.
  * @param ws_pol_level pin level of WS(input) when receiving left channel data
  */
-static inline void i2s_rx_set_ws_idle_pol(i2s_dev_t *hw, int ws_pol_level)
+static inline void i2s_ll_rx_set_ws_idle_pol(i2s_dev_t *hw, bool ws_pol_level)
 {
     hw->rx_conf.rx_ws_idle_pol = ws_pol_level;
 }
diff --git a/components/hal/i2s_hal.c b/components/hal/i2s_hal.c
index 66045c531a..bc34eba55a 100644
--- a/components/hal/i2s_hal.c
+++ b/components/hal/i2s_hal.c
@@ -168,6 +168,10 @@ void i2s_hal_tx_set_common_mode(i2s_hal_context_t *hal, const i2s_hal_config_t *
     i2s_ll_mclk_use_tx_clk(hal->dev);
 
     i2s_ll_tx_set_active_chan_mask(hal->dev, hal_cfg->chan_mask);
+    // In TDM mode(more than 2 channels), the ws polarity should be high first.
+    if (hal_cfg->total_chan > 2) {
+        i2s_ll_tx_set_ws_idle_pol(hal->dev, true);
+    }
     i2s_ll_tx_enable_left_align(hal->dev, hal_cfg->left_align);
     i2s_ll_tx_enable_big_endian(hal->dev, hal_cfg->big_edin);
     i2s_ll_tx_set_bit_order(hal->dev, hal_cfg->bit_order_msb);
@@ -190,6 +194,10 @@ void i2s_hal_rx_set_common_mode(i2s_hal_context_t *hal, const i2s_hal_config_t *
     i2s_ll_mclk_use_rx_clk(hal->dev);
 
     i2s_ll_rx_set_active_chan_mask(hal->dev, hal_cfg->chan_mask);
+    // In TDM mode(more than 2 channels), the ws polarity should be high first.
+    if (hal_cfg->total_chan > 2) {
+        i2s_ll_rx_set_ws_idle_pol(hal->dev, true);
+    }
     i2s_ll_rx_enable_left_align(hal->dev, hal_cfg->left_align);
     i2s_ll_rx_enable_big_endian(hal->dev, hal_cfg->big_edin);
     i2s_ll_rx_set_bit_order(hal->dev, hal_cfg->bit_order_msb);