diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index a4a2849c3c..f7b9977dc0 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -255,8 +255,8 @@ menu "Bootloader config" depends on BOOTLOADER_APP_ANTI_ROLLBACK range 1 32 if IDF_TARGET_ESP32 default 32 if IDF_TARGET_ESP32 - range 1 16 if IDF_TARGET_ESP32S2 - default 16 if IDF_TARGET_ESP32S2 + range 1 16 + default 16 help The size of the efuse secure version field. Its length is limited to 32 bits for ESP32 and 16 bits for ESP32-S2. diff --git a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld index 312ceaa531..e190d4d3b8 100644 --- a/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s3/bootloader.ld @@ -25,15 +25,17 @@ SECTIONS *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ *liblog.a:(.literal .text .literal.* .text.*) *libgcc.a:(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_clock.*(.literal .text .literal.* .text.*) - *libbootloader_support.a:bootloader_common.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) *libbootloader_support.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*) *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*) *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*) @@ -43,6 +45,8 @@ SECTIONS *libspi_flash.a:*.*(.literal .text .literal.* .text.*) *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) *libsoc.a:rtc_clk.*(.literal .text .literal.* .text.*) + *libsoc.a:rtc_time.*(.literal .text .literal.* .text.*) + *libsoc.a:regi2c_ctrl.*(.literal .text .literal.* .text.*) *libefuse.a:*.*(.literal .text .literal.* .text.*) *(.fini.literal) *(.fini) diff --git a/components/bootloader_support/src/bootloader_random_esp32s3.c b/components/bootloader_support/src/bootloader_random_esp32s3.c index a7f6b7e45a..7298d5e3b9 100644 --- a/components/bootloader_support/src/bootloader_random_esp32s3.c +++ b/components/bootloader_support/src/bootloader_random_esp32s3.c @@ -20,6 +20,9 @@ static const char *TAG = "bootloader_random"; void bootloader_random_enable(void) { ESP_LOGW(TAG, "RNG for ESP32-S3 not currently supported"); // IDF-1878 + // Don't forget to remove the following line + // *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + // In the bootloader.ld when RNG support is ready for ESP32-S3 } void bootloader_random_disable(void) diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld index 981ee3a922..fe09fc8fd5 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.spiflash.ld @@ -7,6 +7,7 @@ PROVIDE ( g_ticks_per_us_pro = g_ticks_per_us ); PROVIDE ( g_rom_flashchip = SPI_flashchip_data ); PROVIDE ( g_rom_spiflash_chip = SPI_flashchip_data ); PROVIDE ( esp_rom_spiflash_config_param = SPIParamCfg ); +PROVIDE ( esp_rom_spiflash_read_status = SPI_read_status ); PROVIDE ( esp_rom_spiflash_read_statushigh = SPI_read_status_high ); PROVIDE ( esp_rom_spiflash_read_user_cmd = SPI_user_command_read ); PROVIDE ( esp_rom_spiflash_write = SPIWrite ); diff --git a/components/esp_system/port/async_memcpy_impl_gdma.c b/components/esp_system/port/async_memcpy_impl_gdma.c index 96dacfa9e2..abaa5c30b1 100644 --- a/components/esp_system/port/async_memcpy_impl_gdma.c +++ b/components/esp_system/port/async_memcpy_impl_gdma.c @@ -61,7 +61,8 @@ esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl, dma_descriptor_t *ou gdma_ll_clear_interrupt_status(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, UINT32_MAX); gdma_ll_enable_m2m_mode(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true); gdma_ll_tx_enable_auto_write_back(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true); - gdma_ll_enable_owner_check(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true); + gdma_ll_tx_enable_owner_check(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true); + gdma_ll_rx_enable_owner_check(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true); gdma_ll_tx_set_desc_addr(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, (uint32_t)outlink_base); gdma_ll_rx_set_desc_addr(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, (uint32_t)inlink_base); return ESP_OK; diff --git a/components/esp_system/test/test_intr_alloc.c b/components/esp_system/test/test_intr_alloc.c index e6bb963da3..1e7590902b 100644 --- a/components/esp_system/test/test_intr_alloc.c +++ b/components/esp_system/test/test_intr_alloc.c @@ -19,6 +19,8 @@ #include "driver/timer.h" #include "sdkconfig.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) + #define TIMER_DIVIDER 16 /*!< Hardware timer clock divider */ #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */ #define TIMER_INTERVAL0_SEC (3.4179) /*!< test interval for timer 0 */ @@ -354,3 +356,4 @@ TEST_CASE("alloc and free isr handle on different core", "[intr_alloc]") } #endif +#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) \ No newline at end of file diff --git a/components/esp_system/test/test_sleep.c b/components/esp_system/test/test_sleep.c index 5e6d90197c..e7b5d9a1f9 100644 --- a/components/esp_system/test/test_sleep.c +++ b/components/esp_system/test/test_sleep.c @@ -31,6 +31,7 @@ #include "esp32s3/rom/rtc.h" #endif +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) #define ESP_EXT0_WAKEUP_LEVEL_LOW 0 #define ESP_EXT0_WAKEUP_LEVEL_HIGH 1 @@ -527,3 +528,5 @@ static void check_time_deepsleep(void) } TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep); + +#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index 662f112875..d85e447d95 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -13,16 +13,16 @@ // limitations under the License. #pragma once -#ifdef __cplusplus -extern "C" { -#endif - #include #include #include "soc/soc_caps.h" #include "soc/gdma_struct.h" #include "soc/gdma_reg.h" +#ifdef __cplusplus +extern "C" { +#endif + #define GDMA_LL_EVENT_TX_L3_FIFO_UDF (1<<17) #define GDMA_LL_EVENT_TX_L3_FIFO_OVF (1<<16) #define GDMA_LL_EVENT_TX_L1_FIFO_UDF (1<<15) @@ -59,20 +59,13 @@ extern "C" { static inline void gdma_ll_enable_m2m_mode(gdma_dev_t *dev, uint32_t channel, bool enable) { dev->conf0[channel].mem_trans_en = enable; - if (!enable) { + if (enable) { + // to enable m2m mode, the tx chan has to be the same to rx chan, and set to a valid value dev->peri_sel[channel].peri_in_sel = 0; dev->peri_sel[channel].peri_out_sel = 0; } } -/** - * @brief Enable DMA to check the owner bit in the descriptor, disabled by default - */ -static inline void gdma_ll_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) -{ - dev->conf1[channel].check_owner = enable; -} - /** * @brief Get DMA interrupt status word */ @@ -110,6 +103,14 @@ static inline void gdma_ll_enable_clock(gdma_dev_t *dev, bool enable) } ///////////////////////////////////// RX ///////////////////////////////////////// +/** + * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->conf1[channel].check_owner = enable; +} + /** * @brief Enable DMA RX channel burst reading data, disabled by default */ @@ -305,6 +306,14 @@ static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t c ///////////////////////////////////// TX ///////////////////////////////////////// +/** + * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default + */ +static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable) +{ + dev->conf1[channel].check_owner = enable; +} + /** * @brief Enable DMA TX channel burst sending data, disabled by default */ diff --git a/tools/ci/config/build.yml b/tools/ci/config/build.yml index 999f460a31..4e925e2d3c 100644 --- a/tools/ci/config/build.yml +++ b/tools/ci/config/build.yml @@ -201,6 +201,12 @@ build_test_apps_esp32s2: variables: IDF_TARGET: esp32s2 +build_test_apps_esp32s3: + extends: .build_test_apps + parallel: 8 + variables: + IDF_TARGET: esp32s3 + .build_component_ut: extends: .build_test_apps variables: diff --git a/tools/test_apps/build_system/rsource_test/main/port/esp32s3/Kconfig b/tools/test_apps/build_system/rsource_test/main/port/esp32s3/Kconfig new file mode 100644 index 0000000000..c18c28fd4d --- /dev/null +++ b/tools/test_apps/build_system/rsource_test/main/port/esp32s3/Kconfig @@ -0,0 +1 @@ +rsource "../../../Kconfig.extra" diff --git a/tools/test_apps/protocols/esp_netif/build_config/README.md b/tools/test_apps/protocols/esp_netif/build_config/README.md index d08acda7f3..443d8c2207 100644 --- a/tools/test_apps/protocols/esp_netif/build_config/README.md +++ b/tools/test_apps/protocols/esp_netif/build_config/README.md @@ -1,3 +1,6 @@ +| Supported Targets | ESP32 | ESP32-S2 | +| ----------------- | ----- | -------- | + # Build only test for C++/C configuration This test application aims to exercise different configuration options using standard espressif initialization pattern: diff --git a/tools/test_apps/protocols/mqtt/build_test/README.md b/tools/test_apps/protocols/mqtt/build_test/README.md index 210877c4af..d4a84228e6 100644 --- a/tools/test_apps/protocols/mqtt/build_test/README.md +++ b/tools/test_apps/protocols/mqtt/build_test/README.md @@ -1,3 +1,6 @@ +| Supported Targets | ESP32 | ESP32-S2 | +| ----------------- | ----- | -------- | + # Build only test for C++ This test app ensures that calling all mqtt-client API could be called from C++ diff --git a/tools/test_apps/protocols/mqtt/publish_connect_test/README.md b/tools/test_apps/protocols/mqtt/publish_connect_test/README.md index fe866d1715..b52d36eac5 100644 --- a/tools/test_apps/protocols/mqtt/publish_connect_test/README.md +++ b/tools/test_apps/protocols/mqtt/publish_connect_test/README.md @@ -1,3 +1,6 @@ +| Supported Targets | ESP32 | ESP32-S2 | +| ----------------- | ----- | -------- | + # ESP-MQTT advanced publish and connect test project Main purpose of this application is to test the MQTT library to correctly publish and receive messages (of different size and sequences) over different transports. diff --git a/tools/unit-test-app/configs/default_s3 b/tools/unit-test-app/configs/default_s3 new file mode 100644 index 0000000000..260c7190da --- /dev/null +++ b/tools/unit-test-app/configs/default_s3 @@ -0,0 +1,3 @@ +# This config is split between targets since different component needs to be included +CONFIG_IDF_TARGET="esp32s3" +TEST_COMPONENTS=freertos esp32s3 esp_ipc esp_system esp_timer driver heap pthread soc spi_flash vfs diff --git a/tools/unit-test-app/configs/release_s3 b/tools/unit-test-app/configs/release_s3 new file mode 100644 index 0000000000..823e25b848 --- /dev/null +++ b/tools/unit-test-app/configs/release_s3 @@ -0,0 +1,5 @@ +CONFIG_IDF_TARGET="esp32s3" +TEST_COMPONENTS=freertos esp32s3 esp_system esp_ipc esp_timer driver heap pthread soc spi_flash vfs +CONFIG_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y +CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y