feat(ana_cmpr): support analog comparator on C5

components/esp_driver_ana_cmpr/test_apps/analog_comparator/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 |
-| ----------------- | --------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| ----------------- | -------- | --------- | -------- | -------- |

components/esp_driver_ana_cmpr/test_apps/analog_comparator/pytest_ana_cmpr.py

@@ -6,6 +6,7 @@ from pytest_embedded import Dut
 
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(

components/hal/esp32c5/include/hal/ana_cmpr_ll.h

@@ -0,0 +1,169 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/assert.h"
+#include "soc/ana_cmpr_struct.h"
+#include "soc/soc_etm_source.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ANALOG_CMPR_LL_GET_HW(unit)     (&ANALOG_CMPR[unit])
+#define ANALOG_CMPR_LL_GET_UNIT(hw)     (0)
+#define ANALOG_CMPR_LL_EVENT_CROSS      (1 << 0)
+
+#define ANALOG_CMPR_LL_NEG_CROSS_MASK(unit)   (1UL << ((int)unit * 3))
+#define ANALOG_CMPR_LL_POS_CROSS_MASK(unit)   (1UL << ((int)unit * 3 + 1))
+
+#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type)   (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type))
+
+
+/**
+ * @brief Enable analog comparator
+ *
+ * @param hw Analog comparator register base address
+ * @param en True to enable, False to disable
+ */
+static inline void analog_cmpr_ll_enable(analog_cmpr_dev_t *hw, bool en)
+{
+    hw->pad_comp_config->xpd_comp_0 = en;
+}
+
+/**
+ * @brief Set the voltage of the internal reference
+ *
+ * @param hw Analog comparator register base address
+ * @param volt_level The voltage level of the internal reference, range [0.0V, 0.7VDD], step 0.1VDD
+ */
+__attribute__((always_inline))
+static inline void analog_cmpr_ll_set_internal_ref_voltage(analog_cmpr_dev_t *hw, uint32_t volt_level)
+{
+    hw->pad_comp_config->dref_comp_0 = volt_level;
+}
+
+/**
+ * @brief Get the voltage of the internal reference
+ *
+ * @param hw Analog comparator register base address
+ * @return The voltage of the internal reference
+ */
+static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *hw)
+{
+    return hw->pad_comp_config->dref_comp_0 * 0.1F;
+}
+
+/**
+ * @brief The reference voltage comes from internal or external
+ *
+ * @note Also see `analog_cmpr_ll_set_internal_ref_voltage` to use the internal reference voltage
+ *
+ * @param hw Analog comparator register base address
+ * @param ref_src reference source, 0 for internal, 1 for external GPIO pad (GPIO10)
+ */
+static inline void analog_cmpr_ll_set_ref_source(analog_cmpr_dev_t *hw, uint32_t ref_src)
+{
+    hw->pad_comp_config->mode_comp_0 = ref_src;
+}
+
+/**
+ * @brief Get the interrupt mask by trigger type
+ *
+ * @param hw Analog comparator register base address
+ * @param type The type of cross interrupt
+ *              - 0: disable interrupt
+ *              - 1: enable positive cross interrupt (input analog goes from low to high and across the reference voltage)
+ *              - 2: enable negative cross interrupt (input analog goes from high to low and across the reference voltage)
+ *              - 3: enable any positive or negative cross interrupt
+ * @return interrupt mask
+ */
+__attribute__((always_inline))
+static inline uint32_t analog_cmpr_ll_get_intr_mask_by_type(analog_cmpr_dev_t *hw, uint8_t type)
+{
+    uint32_t unit = ANALOG_CMPR_LL_GET_UNIT(hw);
+    uint32_t mask = 0;
+    if (type & 0x01) {
+        mask |= ANALOG_CMPR_LL_POS_CROSS_MASK(unit);
+    }
+    if (type & 0x02) {
+        mask |= ANALOG_CMPR_LL_NEG_CROSS_MASK(unit);
+    }
+    return mask;
+}
+
+/**
+ * @brief Set the debounce cycle for the cross detection
+ *
+ * @note When the comparator detects a cross, it will wait for the debounce cycle to make sure the cross is stable.
+ *
+ * @param hw Analog comparator register base address
+ * @param cycle The debounce cycle
+ */
+__attribute__((always_inline))
+static inline void analog_cmpr_ll_set_debounce_cycle(analog_cmpr_dev_t *hw, uint32_t cycle)
+{
+    hw->pad_comp_filter->zero_det_filter_cnt_0 = cycle;
+}
+
+/**
+ * @brief Enable comparator interrupt
+ *
+ * @param hw Analog comparator register base address
+ * @param mask Interrupt mask
+ * @param enable True to enable, False to disable
+ */
+static inline void analog_cmpr_ll_enable_intr(analog_cmpr_dev_t *hw, uint32_t mask, bool enable)
+{
+    uint32_t val = hw->int_ena->val;
+    if (enable) {
+        val |= mask;
+    } else {
+        val &= ~mask;
+    }
+    hw->int_ena->val = val;
+}
+
+/**
+ * @brief Get comparator interrupt status
+ *
+ * @param hw Analog comparator register base address
+ */
+__attribute__((always_inline))
+static inline uint32_t analog_cmpr_ll_get_intr_status(analog_cmpr_dev_t *hw)
+{
+    return hw->int_st->val;
+}
+
+/**
+ * @brief Clear comparator interrupt status
+ *
+ * @param hw Analog comparator register base address
+ * @param mask Interrupt status word
+ */
+__attribute__((always_inline))
+static inline void analog_cmpr_ll_clear_intr(analog_cmpr_dev_t *hw, uint32_t mask)
+{
+    hw->int_clr->val = mask;
+}
+
+/**
+ * @brief Get the interrupt status register address
+ *
+ * @param hw Analog comparator register base address
+ * @return The interrupt status register address
+ */
+static inline volatile void *analog_cmpr_ll_get_intr_status_reg(analog_cmpr_dev_t *hw)
+{
+    return hw->int_st;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c5/ana_cmpr_periph.c

@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ana_cmpr_periph.h"
+#include "soc/ana_cmpr_struct.h"
+
+const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
+    [0] = {
+        .src_gpio = ANA_CMPR0_SRC_GPIO,
+        .ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO,
+        .intr_src = ETS_GPIO_NMI_SOURCE,
+    },
+};
+
+analog_cmpr_dev_t ANALOG_CMPR[SOC_ANA_CMPR_NUM] = {
+    [0] = {
+        .pad_comp_config = &GPIO_EXT.pad_comp_config_0,
+        .pad_comp_filter = &GPIO_EXT.pad_comp_filter_0,
+        .int_st = &GPIO_EXT.int_st,
+        .int_ena = &GPIO_EXT.int_ena,
+        .int_clr = &GPIO_EXT.int_clr,
+    },
+};

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -7,6 +7,10 @@ config SOC_ADC_SUPPORTED
     bool
     default y
 
+config SOC_ANA_CMPR_SUPPORTED
+    bool
+    default y
+
 config SOC_DEDICATED_GPIO_SUPPORTED
     bool
     default y
@@ -571,6 +575,18 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
     bool
     default y
 
+config SOC_ANA_CMPR_NUM
+    int
+    default 1
+
+config SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE
+    bool
+    default y
+
+config SOC_ANA_CMPR_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_I2C_NUM
     int
     default 2

components/soc/esp32c5/include/soc/ana_cmpr_channel.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ANA_CMPR0_EXT_REF_GPIO    8       /*!< The GPIO that can be used as external reference voltage */
+#define ANA_CMPR0_SRC_GPIO        9       /*!< The GPIO that used for inputting the source signal to compare */

components/soc/esp32c5/include/soc/ana_cmpr_struct.h

@@ -0,0 +1,36 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+/* NOTE: this file is created manually for compatibility */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/gpio_ext_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief The Analog Comparator Device struct
+ * @note  The field in it are register pointers, which point to the physical address
+ *        of the corresponding configuration register
+ * @note  see 'ana_cmpr_periph.c' for the device instance
+ */
+typedef struct {
+    volatile gpio_ext_pad_comp_config_0_reg_t *pad_comp_config;
+    volatile gpio_ext_pad_comp_filter_0_reg_t *pad_comp_filter;
+    volatile gpio_ext_int_st_reg_t *int_st;
+    volatile gpio_ext_int_ena_reg_t *int_ena;
+    volatile gpio_ext_int_clr_reg_t *int_clr;
+} analog_cmpr_dev_t;
+
+extern analog_cmpr_dev_t ANALOG_CMPR[1];
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c5/include/soc/clk_tree_defs.h

@@ -402,6 +402,23 @@ typedef enum {
     GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
 } soc_periph_glitch_filter_clk_src_t;
 
+///////////////////////////////////////////////////Analog Comparator////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Analog Comparator
+ */
+#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Analog Comparator clock source
+ */
+typedef enum {
+    ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                   /*!< Select XTAL clock as the source clock */
+    ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,             /*!< Select RC_FAST clock as the source clock */
+    ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< Select PLL_F80M clock as the source clock */
+    ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,            /*!< Select PLL_F80M as the default clock choice */
+} soc_periph_ana_cmpr_clk_src_t;
+
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32c5/include/soc/soc_caps.h

@@ -18,6 +18,7 @@
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
+#define SOC_ANA_CMPR_SUPPORTED          1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
@@ -251,6 +252,11 @@
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
 #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
+/*------------------------- Analog Comparator CAPS ---------------------------*/
+#define SOC_ANA_CMPR_NUM                       (1U)
+#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE      (1)  // Support positive/negative/any cross interrupt
+#define SOC_ANA_CMPR_SUPPORT_ETM               (1)
+
 /*-------------------------- I2C CAPS ----------------------------------------*/
 #define SOC_I2C_NUM                 (2U)
 #define SOC_HP_I2C_NUM              (1U)

docs/docs_not_updated/esp32c5.txt

@@ -27,7 +27,6 @@ api-reference/peripherals/twai.rst
 api-reference/peripherals/gptimer.rst
 api-reference/peripherals/touch_element.rst
 api-reference/peripherals/lcd.rst
-api-reference/peripherals/ana_cmpr.rst
 api-reference/peripherals/spi_features.rst
 api-reference/peripherals/touch_pad.rst
 api-reference/peripherals/adc_calibration.rst

docs/en/api-reference/peripherals/ana_cmpr.rst

@@ -3,8 +3,8 @@ Analog Comparator
 
 :link_to_translation:`zh_CN:[中文]`
 
-{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"}
-{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"}
+{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="NOT UPDATED", esp32h2="GPIO11", esp32p4="GPIO52", esp32c5="GPIO9", esp32c61="GPIO9"}
+{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="NOT UPDATED", esp32h2="GPIO10", esp32p4="GPIO51", esp32c5="GPIO8", esp32c61="GPIO8"}
 {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="NOT UPDATED", esp32p4="GPIO54"}
 {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="NOT UPDATED", esp32p4="GPIO53"}
 

docs/zh_CN/api-reference/peripherals/ana_cmpr.rst

@@ -3,8 +3,8 @@
 
 :link_to_translation:`en:[English]`
 
-{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52", esp32c61="GPIO9"}
-{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51", esp32c61="GPIO8"}
+{IDF_TARGET_ANA_CMPR_SRC_CHAN0: default="未更新", esp32h2="GPIO11", esp32p4="GPIO52", esp32c5="GPIO9", esp32c61="GPIO9"}
+{IDF_TARGET_ANA_CMPR_EXT_REF_CHAN0: default="未更新", esp32h2="GPIO10", esp32p4="GPIO51", esp32c5="GPIO8", esp32c61="GPIO8"}
 {IDF_TARGET_ANA_CMPR_SRC_CHAN1: default="未更新", esp32p4="GPIO54"}
 {IDF_TARGET_ANA_CMPR_EXT_REF_CHAN1: default="未更新", esp32p4="GPIO53"}
 

examples/peripherals/analog_comparator/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C61 | ESP32-H2 | ESP32-P4 |
-| ----------------- | --------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| ----------------- | -------- | --------- | -------- | -------- |
 
 # Analog Comparator Example
 

examples/peripherals/analog_comparator/pytest_ana_cmpr_example.py

@@ -6,6 +6,7 @@ from pytest_embedded import Dut
 
 @pytest.mark.esp32h2
 @pytest.mark.esp32p4
+@pytest.mark.esp32c5
 @pytest.mark.esp32c61
 @pytest.mark.generic
 @pytest.mark.parametrize(