diff --git a/components/esp32/spiram_psram.c b/components/esp32/spiram_psram.c
index b63fbcd631..9e18dbf61b 100644
--- a/components/esp32/spiram_psram.c
+++ b/components/esp32/spiram_psram.c
@@ -117,6 +117,11 @@ typedef enum {
 #define D2WD_PSRAM_CLK_IO          CONFIG_D2WD_PSRAM_CLK_IO  // Default value is 9
 #define D2WD_PSRAM_CS_IO           CONFIG_D2WD_PSRAM_CS_IO   // Default value is 10
 
+// There is no reason to change the pin of an embedded psram.
+// So define the number of pin directly, instead of configurable.
+#define D0WDR2_V3_PSRAM_CLK_IO    6
+#define D0WDR2_V3_PSRAM_CS_IO     16
+
 // For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
 #define PICO_PSRAM_CLK_IO          6
 #define PICO_PSRAM_CS_IO           CONFIG_PICO_PSRAM_CS_IO   // Default value is 10
@@ -839,6 +844,16 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
         ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD");
         psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO;
         psram_io.psram_cs_io  = D0WD_PSRAM_CS_IO;
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3) {
+        ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WDR2-V3");
+        rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
+        if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
+            ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
+            return ESP_FAIL;
+        }
+        s_clk_mode = PSRAM_CLK_MODE_NORM;
+        psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
+        psram_io.psram_cs_io  = D0WDR2_V3_PSRAM_CS_IO;
     } else {
         ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
         abort();
diff --git a/components/soc/soc/esp32/include/soc/efuse_reg.h b/components/soc/soc/esp32/include/soc/efuse_reg.h
index b82ac9e981..c3ef23ef38 100644
--- a/components/soc/soc/esp32/include/soc/efuse_reg.h
+++ b/components/soc/soc/esp32/include/soc/efuse_reg.h
@@ -116,6 +116,7 @@
 #define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH   4
 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4  5
 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302  6
+#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3  7
 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */
 /*description: read for SPI_pad_config_hd*/
 #define EFUSE_RD_SPI_PAD_CONFIG_HD  0x0000001F