From 6382f28998b0ed3e2a01af16f23ff5e174227ed1 Mon Sep 17 00:00:00 2001 From: Guillaume Souchere Date: Wed, 25 Jan 2023 11:13:09 +0100 Subject: [PATCH] heap: Modify the memory type of the memory used as startup stack when memory protection is enabled If memory protection is enabled on esp32c3 and esp32s3, we don't want to the heap component to see the startup stack memory as D/IRAM but as DRAM only. Introduce a new type to make this possible in the same fashion the regular D/IRAM regions are handled. --- components/heap/port/esp32c3/memory_layout.c | 13 +++-- components/heap/port/esp32c6/memory_layout.c | 13 +++-- components/heap/port/esp32h2/memory_layout.c | 13 +++-- components/heap/port/esp32h4/memory_layout.c | 11 +++-- components/heap/port/esp32s3/memory_layout.c | 51 ++++++++++++-------- components/heap/test_apps/pytest_heap.py | 1 - 6 files changed, 66 insertions(+), 36 deletions(-) diff --git a/components/heap/port/esp32c3/memory_layout.c b/components/heap/port/esp32c3/memory_layout.c index 2866b4f81d..2cad273fe9 100644 --- a/components/heap/port/esp32c3/memory_layout.c +++ b/components/heap/port/esp32c3/memory_layout.c @@ -30,7 +30,8 @@ enum { SOC_MEMORY_TYPE_DRAM = 0, SOC_MEMORY_TYPE_STACK_DRAM = 1, SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_STACK_DIRAM = 3, + SOC_MEMORY_TYPE_RTCRAM = 4, SOC_MEMORY_TYPE_NUM, }; @@ -38,17 +39,21 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { // Type 0: DRAM [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM + // Type 3: DIRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, + // Type 4: RTCRAM [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM #else #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -70,7 +75,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32c6/memory_layout.c b/components/heap/port/esp32c6/memory_layout.c index 39118f3260..94369e4515 100644 --- a/components/heap/port/esp32c6/memory_layout.c +++ b/components/heap/port/esp32c6/memory_layout.c @@ -30,7 +30,8 @@ enum { SOC_MEMORY_TYPE_DRAM = 0, SOC_MEMORY_TYPE_STACK_DRAM = 1, SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_STACK_DIRAM = 3, + SOC_MEMORY_TYPE_RTCRAM = 4, SOC_MEMORY_TYPE_NUM, }; @@ -38,17 +39,21 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { // Type 0: DRAM [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM + // Type 3: DIRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, + // Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM #else #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -71,7 +76,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x40820000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level1, can be used as trace memory { 0x40840000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level2, can be used as trace memory { 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_DEFAULT, 0x40860000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, APP_USABLE_DRAM_END}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0}, //LPRAM #endif diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index 0743e6e558..98e4924484 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -28,7 +28,8 @@ enum { SOC_MEMORY_TYPE_DRAM = 0, SOC_MEMORY_TYPE_STACK_DRAM = 1, SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_STACK_DIRAM = 3, + SOC_MEMORY_TYPE_RTCRAM = 4, SOC_MEMORY_TYPE_NUM, }; @@ -36,17 +37,21 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { // Type 0: DRAM [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM + // Type 3: DIRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, + // Type 4: RTCRAM // TODO: IDF-5667 Better to rename to LPRAM [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM #else #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -70,7 +75,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x40820000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40820000}, //D/IRAM level 2 { 0x40830000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40830000}, //D/IRAM level 3 { 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_DEFAULT, 0x40840000}, //D/IRAM level 4 - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, APP_USABLE_DRAM_END}, //D/IRAM level 4 + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, APP_USABLE_DRAM_END}, //D/IRAM level 4 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32h4/memory_layout.c b/components/heap/port/esp32h4/memory_layout.c index 50f30edadb..d0875728c5 100644 --- a/components/heap/port/esp32h4/memory_layout.c +++ b/components/heap/port/esp32h4/memory_layout.c @@ -29,7 +29,8 @@ enum { SOC_MEMORY_TYPE_DRAM = 0, SOC_MEMORY_TYPE_STACK_DRAM = 1, SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_STACK_DIRAM = 3, + SOC_MEMORY_TYPE_RTCRAM = 4, SOC_MEMORY_TYPE_NUM, }; @@ -40,14 +41,18 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, // Type 2: DRAM which has an alias on the I-port [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM + // Type 3: DIRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, + // Type 4: RTCRAM [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, }; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM #else #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM #endif const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -69,7 +74,7 @@ const soc_memory_region_t soc_memory_regions[] = { { 0x3FC80000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //D/IRAM level1, can be used as trace memory { 0x3FCA0000, 0x20000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //D/IRAM level2, can be used as trace memory { 0x3FCC0000, (APP_USABLE_DRAM_END-0x3FCC0000), SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //D/IRAM level3, can be used as trace memory - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //D/IRAM level3, can be used as trace memory (ROM reserved area) #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP { 0x50000000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 93962fd681..3566c70f2f 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -29,13 +29,14 @@ /* Index of memory in `soc_memory_types[]` */ enum { - SOC_MEMORY_TYPE_DRAM = 0, - SOC_MEMORY_TYPE_STACK_DRAM = 1, - SOC_MEMORY_TYPE_DIRAM = 2, - SOC_MEMORY_TYPE_IRAM = 3, - SOC_MEMORY_TYPE_SPIRAM = 4, - SOC_MEMORY_TYPE_NODMARAM = 5, - SOC_MEMORY_TYPE_RTCRAM = 6, + SOC_MEMORY_TYPE_DRAM = 0, + SOC_MEMORY_TYPE_STACK_DRAM = 1, + SOC_MEMORY_TYPE_DIRAM = 2, + SOC_MEMORY_TYPE_STACK_DIRAM = 3, + SOC_MEMORY_TYPE_IRAM = 4, + SOC_MEMORY_TYPE_SPIRAM = 5, + SOC_MEMORY_TYPE_NODMARAM = 6, + SOC_MEMORY_TYPE_RTCRAM = 7, SOC_MEMORY_TYPE_NUM, }; @@ -43,19 +44,29 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { // Type 0: DRAM [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 1: DRAM used for startup stacks - [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, // Type 2: DRAM which has an alias on the I-port [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC | MALLOC_CAP_RETENTION}, true, false}, - // Type 3: IRAM + // Type 3: DIRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DIRAM] = { "STACK/DIRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT | MALLOC_CAP_RETENTION, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, true, true}, + // Type 4: IRAM [SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, - // Type 4: SPI SRAM data + // Type 5: SPI SRAM data [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, - // Type 5: DRAM which is not DMA accesible + // Type 6: DRAM which is not DMA accesible [SOC_MEMORY_TYPE_NODMARAM] = { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 6: RTC Fast RAM + // Type 7: RTC Fast RAM [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; +#ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DRAM +#else +#define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DIRAM +#define SOC_MEMORY_TYPE_STACK_DEFAULT SOC_MEMORY_TYPE_STACK_DIRAM +#endif + const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); /** @@ -78,14 +89,14 @@ const soc_memory_region_t soc_memory_regions[] = { #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB { 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0}, //Level 1, IRAM #endif - { 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy - { 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy - { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy - { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy - { 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy - { 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy - { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task + { 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DEFAULT, 0x40378000}, //Level 2, IDRAM, can be used as trace memory + { 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40380000}, //Level 3, IDRAM, can be used as trace memory + { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x40390000}, //Level 4, IDRAM, can be used as trace memory + { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403A0000}, //Level 5, IDRAM, can be used as trace memory + { 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403B0000}, //Level 6, IDRAM, can be used as trace memory + { 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DEFAULT, 0x403C0000}, //Level 7, IDRAM, can be used as trace memory + { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DEFAULT, 0x403D0000}, //Level 8, IDRAM, can be used as trace memory, + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DEFAULT, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memory, ROM reserved area, recycled by heap allocator in app_main task #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB { 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM, DMA is accessible but retention DMA is inaccessible #endif diff --git a/components/heap/test_apps/pytest_heap.py b/components/heap/test_apps/pytest_heap.py index a6f6007461..9f7be28ca1 100644 --- a/components/heap/test_apps/pytest_heap.py +++ b/components/heap/test_apps/pytest_heap.py @@ -96,7 +96,6 @@ def test_heap_trace_dump(dut: Dut) -> None: @pytest.mark.generic @pytest.mark.supported_targets -@pytest.mark.temp_skip_ci(targets=['esp32c3', 'esp32s3'], reason='test failed') @pytest.mark.parametrize( 'config', [