kopia lustrzana https://github.com/espressif/esp-idf
fix(esp32s3): patch Cache_WriteBack_Addr api
avoid accessing cachelines that are being writebackedpull/11821/head
rodzic
a2d76ad38a
commit
b1436633c5
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@ -46,7 +46,7 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL)
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list(APPEND sources "patches/esp_rom_wdt.c")
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endif()
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if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG)
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if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG)
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list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c")
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endif()
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@ -82,3 +82,7 @@ config ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG
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config ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG
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bool
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default y
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config ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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bool
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default y
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@ -26,3 +26,4 @@
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#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init
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#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
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#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti
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#define ESP_ROM_HAS_CACHE_WRITEBACK_BUG (1) // ROM api Cache_WriteBack_Addr address or size misalignment may cause cache hit with wrong value.
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@ -381,7 +381,7 @@ PROVIDE( Cache_WriteBack_Items = 0x40001698 );
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PROVIDE( Cache_Op_Addr = 0x400016a4 );
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PROVIDE( Cache_Invalidate_Addr = 0x400016b0 );
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PROVIDE( Cache_Clean_Addr = 0x400016bc );
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PROVIDE( Cache_WriteBack_Addr = 0x400016c8 );
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PROVIDE( rom_Cache_WriteBack_Addr = 0x400016c8 );
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PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 );
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PROVIDE( Cache_Invalidate_DCache_All = 0x400016e0 );
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PROVIDE( Cache_Clean_All = 0x400016ec );
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@ -8,10 +8,14 @@
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "soc/extmem_reg.h"
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#include "xtensa/xtruntime.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#endif
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#define ALIGN_UP(addr, align) (((addr) + (align)-1) & ~((align)-1))
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#define ALIGN_DOWN(addr, align) ((addr) & ~((align) - 1))
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// this api is renamed for patch
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extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
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uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped)
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@ -83,3 +87,89 @@ void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode)
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extern void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
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#endif
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#endif
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#if CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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static void __attribute__((optimize("-O2"))) Cache_WriteBack_Items_Freeze(uint32_t addr, uint32_t items)
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{
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/* Please do not modify this function, it must strictly follow the current execution sequence,
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* otherwise it may cause unexpected errors.
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*/
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REG_WRITE(EXTMEM_DCACHE_SYNC_ADDR_REG, addr);
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REG_SET_FIELD(EXTMEM_DCACHE_SYNC_SIZE_REG, EXTMEM_DCACHE_SYNC_SIZE, items);
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/*enable dcache freeze, mode = CACHE_FREEZE_ACK_BUSY*/
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REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_MODE);
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REG_SET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA);
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while (!REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE));
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REG_SET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_WRITEBACK_ENA);
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while(!REG_GET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_SYNC_DONE));
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/*disable dcache freeze*/
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REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA);
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while (REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE));
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}
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// renamed for patch
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extern int rom_Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
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int Cache_WriteBack_Addr(uint32_t addr, uint32_t size)
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{
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/* Do special processing for unaligned memory at the start and end of the cache writeback memory.
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* 1. Disable the interrupt to prevent the current CPU accessing the same cacheline.
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* 2. Enable dcache freeze to prevent the another CPU accessing the same cacheline.
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*/
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uint32_t irq_status;
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uint32_t start_len, end_len;
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uint32_t start, end;
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uint32_t dcache_line_size;
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uint32_t autoload;
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int ret = 0;
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start = addr;
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end = addr + size;
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dcache_line_size = Cache_Get_DCache_Line_Size();
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if (size == 0) {
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return 0;
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}
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/*the start address is unaligned*/
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if (start & (dcache_line_size -1)) {
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addr = ALIGN_UP(start, dcache_line_size);
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start_len = addr - start;
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size = (size < start_len) ? 0 : (size - start_len);
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/*writeback start unaligned mem, one cacheline*/
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irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts
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Cache_WriteBack_Items_Freeze(start, 1);
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XTOS_RESTORE_INTLEVEL(irq_status);
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if (size == 0) {
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return 0;
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}
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}
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/*the end address is unaligned*/
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if (end & (dcache_line_size -1)) {
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end = ALIGN_DOWN(end, dcache_line_size);
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end_len = addr + size - end;
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size = (size - end_len);
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/*writeback end unaligned mem, one cacheline*/
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irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts
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Cache_WriteBack_Items_Freeze(end, 1);
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XTOS_RESTORE_INTLEVEL(irq_status);
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if (size == 0) {
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return 0;
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}
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}
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/*suspend autoload, avoid load cachelines being written back*/
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autoload = Cache_Suspend_DCache_Autoload();
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ret = rom_Cache_WriteBack_Addr(addr, size);
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Cache_Resume_DCache_Autoload(autoload);
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return ret;
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}
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extern int Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
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#endif
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