kopia lustrzana https://github.com/espressif/esp-idf
feat(efuse): Support Linux target
Konstantin Kondrashov
rodzic
e4fd0b7862
commit
aed84fa818
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@ -1,9 +1,5 @@
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idf_build_get_property(target IDF_TARGET)
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if(${target} STREQUAL "linux")
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return() # This component is not supported by the POSIX/Linux simulator
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endif()
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if(CONFIG_EFUSE_VIRTUAL)
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message(STATUS "Efuse virtual mode is enabled. If Secure boot or Flash encryption is on"
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" it does not provide any security. FOR TESTING ONLY!")
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@ -43,8 +39,10 @@ else()
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PRIV_REQUIRES bootloader_support soc spi_flash esp_system esp_partition esp_app_format
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INCLUDE_DIRS "${include_dirs}"
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PRIV_INCLUDE_DIRS "${private_include}")
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# Forces the linker to include esp_efuse_startup.c
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target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_efuse_startup_include_func")
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if(NOT ${target} STREQUAL "linux")
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# Forces the linker to include esp_efuse_startup.c
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target_link_libraries(${COMPONENT_LIB} INTERFACE "-u esp_efuse_startup_include_func")
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endif()
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endif()
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if(target)
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@ -16,7 +16,8 @@ menu "eFuse Bit Manager"
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config EFUSE_VIRTUAL
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bool "Simulate eFuse operations in RAM"
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default n
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default n if !IDF_TARGET_LINUX
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default y if IDF_TARGET_LINUX
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help
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If "n" - No virtual mode. All eFuse operations are real and use eFuse registers.
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If "y" - The virtual mode is enabled and all eFuse operations (read and write) are redirected
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@ -30,7 +31,7 @@ menu "eFuse Bit Manager"
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config EFUSE_VIRTUAL_KEEP_IN_FLASH
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bool "Keep eFuses in flash"
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depends on EFUSE_VIRTUAL
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depends on EFUSE_VIRTUAL && !IDF_TARGET_LINUX
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help
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In addition to the "Simulate eFuse operations in RAM" option, this option just adds
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a feature to keep eFuses after reboots in flash memory. To use this mode the partition_table
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@ -0,0 +1,52 @@
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/*
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* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "esp_efuse.h"
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#include "esp_efuse_utility.h"
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#include "esp_efuse_table.h"
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#include "stdlib.h"
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#include "esp_types.h"
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#include "assert.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "soc/efuse_periph.h"
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#include "sys/param.h"
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static __attribute__((unused)) const char *TAG = "efuse";
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// Contains functions that provide access to efuse fields which are often used in IDF.
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// Returns chip package from efuse
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uint32_t esp_efuse_get_pkg_ver(void)
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{
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uint32_t pkg_ver = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
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return pkg_ver;
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}
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esp_err_t esp_efuse_disable_rom_download_mode(void)
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{
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return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
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}
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esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
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{
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int cur_log_scheme = 0;
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esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, ESP_EFUSE_UART_PRINT_CONTROL[0]->bit_count);
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if (!cur_log_scheme) { // not burned yet
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return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, ESP_EFUSE_UART_PRINT_CONTROL[0]->bit_count);
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} else {
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return ESP_ERR_INVALID_STATE;
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}
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}
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esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
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{
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if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
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return ESP_ERR_INVALID_STATE;
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}
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return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
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}
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Plik diff jest za duży
Load Diff
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@ -0,0 +1,244 @@
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# field_name, | efuse_block, | bit_start, | bit_count, |comment #
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# | (EFUSE_BLK0 | (0..255) | (1-256) | #
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# | EFUSE_BLK1 | | | #
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# | ...) | | | #
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##########################################################################
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# !!!!!!!!!!! #
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# After editing this file, run the command manually "idf.py efuse-common-table"
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# this will generate new source files, next rebuild all the sources.
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# !!!!!!!!!!! #
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# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70
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WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
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WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
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WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
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WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE
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WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
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WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE
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WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
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WR_DIS.DIS_USB_OTG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB] wr_dis of DIS_USB_OTG
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WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
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WR_DIS.DIS_APP_CPU, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_APP_CPU
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WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.HARD_DIS_JTAG] wr_dis of DIS_PAD_JTAG
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WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
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WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
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WR_DIS.DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_USB_DEVICE] wr_dis of DIS_USB_SERIAL_JTAG
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WR_DIS.STRAP_JTAG_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of STRAP_JTAG_SEL
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WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of USB_PHY_SEL
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WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD
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WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
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WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE
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WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
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WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
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WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
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WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
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WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
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WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
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WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
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WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
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WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
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WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
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WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
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WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
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WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
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WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
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WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
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WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_LEGACY_SPI_BOOT] wr_dis of DIS_DIRECT_BOOT
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WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [WR_DIS.UART_PRINT_CHANNEL] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
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WR_DIS.FLASH_ECC_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_MODE
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WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [WR_DIS.DIS_USB_DOWNLOAD_MODE] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
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WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
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WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
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WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION
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WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
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WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE
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WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN
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WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
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WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
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WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 19, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE
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WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
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WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 19, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
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WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
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WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
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WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
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WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
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WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
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WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
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WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
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WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
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WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
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WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
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WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
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WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
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WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
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WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
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WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
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WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
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WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
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WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP
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WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
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WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
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WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP
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WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
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WR_DIS.K_RTC_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_RTC_LDO
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WR_DIS.K_DIG_LDO, EFUSE_BLK0, 20, 1, [] wr_dis of K_DIG_LDO
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WR_DIS.V_RTC_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_RTC_DBIAS20
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WR_DIS.V_DIG_DBIAS20, EFUSE_BLK0, 20, 1, [] wr_dis of V_DIG_DBIAS20
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WR_DIS.DIG_DBIAS_HVT, EFUSE_BLK0, 20, 1, [] wr_dis of DIG_DBIAS_HVT
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WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
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WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
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WR_DIS.ADC2_CAL_VOL_ATTEN3, EFUSE_BLK0, 20, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN3
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WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
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WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
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WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MAJOR
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WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
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WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
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WR_DIS.ADC1_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN0
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WR_DIS.ADC1_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN1
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WR_DIS.ADC1_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN2
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WR_DIS.ADC1_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_INIT_CODE_ATTEN3
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WR_DIS.ADC2_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN0
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WR_DIS.ADC2_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN1
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WR_DIS.ADC2_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN2
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WR_DIS.ADC2_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_INIT_CODE_ATTEN3
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WR_DIS.ADC1_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN0
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WR_DIS.ADC1_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN1
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WR_DIS.ADC1_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN2
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WR_DIS.ADC1_CAL_VOL_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CAL_VOL_ATTEN3
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WR_DIS.ADC2_CAL_VOL_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN0
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WR_DIS.ADC2_CAL_VOL_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN1
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WR_DIS.ADC2_CAL_VOL_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_CAL_VOL_ATTEN2
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WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
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WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
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WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
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WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
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WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
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WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
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WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
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WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
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WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
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WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
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WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
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RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
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RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
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RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
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RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
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RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
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RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
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RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
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RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
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DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
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DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache
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DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Set this bit to disable Icache in download mode (boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
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DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0; 1; 2; 3; 6; 7)
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DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
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DIS_USB_OTG, EFUSE_BLK0, 45, 1, [DIS_USB] Set this bit to disable USB function
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DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable CAN function
|
||||
DIS_APP_CPU, EFUSE_BLK0, 47, 1, [] Disable app cpu
|
||||
SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module
|
||||
DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [HARD_DIS_JTAG] Set this bit to disable JTAG in the hard way. JTAG is disabled permanently
|
||||
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Set this bit to disable flash encryption when in download boot modes
|
||||
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Set this bit to exchange USB D+ and D- pins
|
||||
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 58, 1, [EXT_PHY_ENABLE] Set this bit to enable external PHY
|
||||
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] SPI regulator power up signal
|
||||
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
|
||||
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit and force to use the configuration of eFuse to configure VDD_SPI
|
||||
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
|
||||
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
|
||||
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
|
||||
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
|
||||
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of Key0
|
||||
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of Key1
|
||||
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of Key2
|
||||
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of Key3
|
||||
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of Key4
|
||||
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of Key5
|
||||
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
|
||||
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable revoking aggressive secure boot
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 118, 1, [] Set this bit to disable function of usb switch to jtag in module of usb device
|
||||
DIS_USB_SERIAL_JTAG, EFUSE_BLK0, 119, 1, [DIS_USB_DEVICE] Set this bit to disable usb device
|
||||
STRAP_JTAG_SEL, EFUSE_BLK0, 120, 1, [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0
|
||||
USB_PHY_SEL, EFUSE_BLK0, 121, 1, [] This bit is used to switch internal PHY and external PHY for USB OTG and USB Device {0: "internal PHY is assigned to USB Device while external PHY is assigned to USB OTG"; 1: "internal PHY is assigned to USB OTG while external PHY is assigned to USB Device"}
|
||||
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash waiting time after power-up; in unit of ms. If the value is less than 15; the waiting time is the configurable value. Otherwise; the waiting time is twice the configurable value
|
||||
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable download mode (boot_mode[3:0] = 0; 1; 2; 3; 6; 7)
|
||||
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [DIS_LEGACY_SPI_BOOT] Disable direct boot mode
|
||||
DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [UART_PRINT_CHANNEL] USB printing {0: "Enable"; 1: "Disable"}
|
||||
FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, [] Flash ECC mode in ROM {0: "16to18 byte"; 1: "16to17 byte"}
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [DIS_USB_DOWNLOAD_MODE] Set this bit to disable UART download mode through USB
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
|
||||
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
|
||||
FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
|
||||
FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, [] Set Flash page size
|
||||
FLASH_ECC_EN, EFUSE_BLK0, 140, 1, [] Set 1 to enable ECC for flash boot
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, [] Set this bit to force ROM code to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 142, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
|
||||
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, [] Set this bit to disable download through USB-OTG
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
|
||||
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK
|
||||
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1)
|
||||
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0)
|
||||
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS
|
||||
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3)
|
||||
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2)
|
||||
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS
|
||||
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4
|
||||
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5
|
||||
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6
|
||||
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7
|
||||
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 114, 3, [] WAFER_VERSION_MINOR least significant bits
|
||||
PKG_VERSION, EFUSE_BLK1, 117, 3, [] Package version
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VERSION_MINOR
|
||||
FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"}
|
||||
FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"}
|
||||
FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"}
|
||||
PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}
|
||||
PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"}
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"}
|
||||
K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO
|
||||
K_DIG_LDO, EFUSE_BLK1, 148, 7, [] BLOCK1 K_DIG_LDO
|
||||
V_RTC_DBIAS20, EFUSE_BLK1, 155, 8, [] BLOCK1 voltage of rtc dbias20
|
||||
V_DIG_DBIAS20, EFUSE_BLK1, 163, 8, [] BLOCK1 voltage of digital dbias20
|
||||
DIG_DBIAS_HVT, EFUSE_BLK1, 171, 5, [] BLOCK1 digital dbias when hvt
|
||||
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 183, 1, [] WAFER_VERSION_MINOR most significant bit
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, [] WAFER_VERSION_MAJOR
|
||||
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, [] ADC2 calibration voltage at atten3
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, [] BLK_VERSION_MAJOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"}
|
||||
TEMP_CALIB, EFUSE_BLK2, 132, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 141, 8, [] ADC OCode
|
||||
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, [] ADC1 init code at atten0
|
||||
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, [] ADC1 init code at atten1
|
||||
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, [] ADC1 init code at atten2
|
||||
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, [] ADC1 init code at atten3
|
||||
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, [] ADC2 init code at atten0
|
||||
ADC2_INIT_CODE_ATTEN1, EFUSE_BLK2, 183, 6, [] ADC2 init code at atten1
|
||||
ADC2_INIT_CODE_ATTEN2, EFUSE_BLK2, 189, 6, [] ADC2 init code at atten2
|
||||
ADC2_INIT_CODE_ATTEN3, EFUSE_BLK2, 195, 6, [] ADC2 init code at atten3
|
||||
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 201, 8, [] ADC1 calibration voltage at atten0
|
||||
ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 209, 8, [] ADC1 calibration voltage at atten1
|
||||
ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 217, 8, [] ADC1 calibration voltage at atten2
|
||||
ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 225, 8, [] ADC1 calibration voltage at atten3
|
||||
ADC2_CAL_VOL_ATTEN0, EFUSE_BLK2, 233, 8, [] ADC2 calibration voltage at atten0
|
||||
ADC2_CAL_VOL_ATTEN1, EFUSE_BLK2, 241, 7, [] ADC2 calibration voltage at atten1
|
||||
ADC2_CAL_VOL_ATTEN2, EFUSE_BLK2, 248, 7, [] ADC2 calibration voltage at atten2
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
|
||||
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
|
Nie można renderować tego pliku, ponieważ zawiera nieoczekiwany znak w wierszu 8 i kolumnie 53.
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|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_log.h"
|
||||
#include "assert.h"
|
||||
#include "sdkconfig.h"
|
||||
#include <sys/param.h>
|
||||
|
||||
#ifndef CONFIG_EFUSE_VIRTUAL
|
||||
#error Linux target supports only VIRTUAL eFuses
|
||||
#endif // CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
static const char *TAG = "efuse";
|
||||
|
||||
extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
|
||||
|
||||
/*Range addresses to read blocks*/
|
||||
const esp_efuse_range_addr_t range_read_addr_blocks[] = {
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK0][0], (uintptr_t) &virt_blocks[EFUSE_BLK0][5]}, // range address of EFUSE_BLK0 REPEAT
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK1][0], (uintptr_t) &virt_blocks[EFUSE_BLK1][5]}, // range address of EFUSE_BLK1 MAC_SPI_8M
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK2][0], (uintptr_t) &virt_blocks[EFUSE_BLK2][7]}, // range address of EFUSE_BLK2 SYS_DATA
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK3][0], (uintptr_t) &virt_blocks[EFUSE_BLK3][7]}, // range address of EFUSE_BLK3 USR_DATA
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK4][0], (uintptr_t) &virt_blocks[EFUSE_BLK4][7]}, // range address of EFUSE_BLK4 KEY0
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK5][0], (uintptr_t) &virt_blocks[EFUSE_BLK5][7]}, // range address of EFUSE_BLK5 KEY1
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK6][0], (uintptr_t) &virt_blocks[EFUSE_BLK6][7]}, // range address of EFUSE_BLK6 KEY2
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK7][0], (uintptr_t) &virt_blocks[EFUSE_BLK7][7]}, // range address of EFUSE_BLK7 KEY3
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK8][0], (uintptr_t) &virt_blocks[EFUSE_BLK8][7]}, // range address of EFUSE_BLK8 KEY4
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK9][0], (uintptr_t) &virt_blocks[EFUSE_BLK9][7]}, // range address of EFUSE_BLK9 KEY5
|
||||
{(uintptr_t) &virt_blocks[EFUSE_BLK10][0], (uintptr_t) &virt_blocks[EFUSE_BLK10][7]}, // range address of EFUSE_BLK10 KEY6
|
||||
};
|
||||
|
||||
static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
|
||||
|
||||
/*Range addresses to write blocks (it is not real regs, it is buffer) */
|
||||
const esp_efuse_range_addr_t range_write_addr_blocks[] = {
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK0][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK0][5]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK1][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK1][5]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK2][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK2][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK3][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK3][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK4][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK4][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK5][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK5][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK6][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK6][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK7][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK7][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK8][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK8][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK9][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK9][7]},
|
||||
{(uintptr_t) &write_mass_blocks[EFUSE_BLK10][0], (uintptr_t) &write_mass_blocks[EFUSE_BLK10][7]},
|
||||
};
|
||||
|
||||
// Efuse read operation: copies data from physical efuses to efuse read registers.
|
||||
void esp_efuse_utility_clear_program_registers(void)
|
||||
{
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_utility_check_errors(void)
|
||||
{
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
// Burn values written to the efuse write registers
|
||||
esp_err_t esp_efuse_utility_burn_chip(void)
|
||||
{
|
||||
return esp_efuse_utility_burn_chip_opt(false, true);
|
||||
}
|
||||
|
||||
esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data)
|
||||
{
|
||||
esp_err_t error = ESP_OK;
|
||||
ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
|
||||
for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
|
||||
int subblock = 0;
|
||||
for (uintptr_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
|
||||
esp_efuse_utility_write_efuses_to_flash();
|
||||
#endif
|
||||
esp_efuse_utility_reset();
|
||||
return error;
|
||||
}
|
||||
|
||||
// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
|
||||
// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
|
||||
// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
|
||||
// They will be filled during the burn operation.
|
||||
esp_err_t esp_efuse_utility_apply_new_coding_scheme()
|
||||
{
|
||||
// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
|
||||
for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
|
||||
for (uintptr_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block)) {
|
||||
int num_reg = 0;
|
||||
for (uintptr_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
|
||||
if (esp_efuse_utility_read_reg(num_block, num_reg)) {
|
||||
ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
|
||||
return ESP_ERR_CODING;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return ESP_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Type of eFuse blocks for LINUX target based on ESP32S3
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */
|
||||
|
||||
EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
|
||||
|
||||
EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
|
||||
|
||||
EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/
|
||||
|
||||
EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */
|
||||
|
||||
EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */
|
||||
|
||||
EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */
|
||||
|
||||
EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */
|
||||
|
||||
EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */
|
||||
|
||||
EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */
|
||||
EFUSE_BLK_KEY_MAX = 10,
|
||||
|
||||
EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
|
||||
|
||||
EFUSE_BLK_MAX
|
||||
} esp_efuse_block_t;
|
||||
|
||||
/**
|
||||
* @brief Type of coding scheme
|
||||
*/
|
||||
typedef enum {
|
||||
EFUSE_CODING_SCHEME_NONE = 0, /**< None */
|
||||
EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */
|
||||
} esp_efuse_coding_scheme_t;
|
||||
|
||||
/**
|
||||
* @brief Type of key purpose
|
||||
*/
|
||||
typedef enum {
|
||||
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
|
||||
ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< XTS_AES_256_KEY_1 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< XTS_AES_256_KEY_2 (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
|
||||
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
|
||||
ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */
|
||||
} esp_efuse_purpose_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,306 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table e0674ff40a1e124670c6eecf33410e76
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
// To show efuse_table run the command 'show_efuse_table'.
|
||||
|
||||
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB ESP_EFUSE_WR_DIS_DIS_USB_OTG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_APP_CPU[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
|
||||
#define ESP_EFUSE_WR_DIS_HARD_DIS_JTAG ESP_EFUSE_WR_DIS_DIS_PAD_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DEVICE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_STRAP_JTAG_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[];
|
||||
#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG[];
|
||||
#define ESP_EFUSE_DIS_USB ESP_EFUSE_DIS_USB_OTG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
|
||||
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_APP_CPU[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
|
||||
#define ESP_EFUSE_HARD_DIS_JTAG ESP_EFUSE_DIS_PAD_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
|
||||
#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_FORCE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
|
||||
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
|
||||
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
|
||||
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
|
||||
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
|
||||
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
|
||||
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG[];
|
||||
#define ESP_EFUSE_DIS_USB_DEVICE ESP_EFUSE_DIS_USB_SERIAL_JTAG
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_STRAP_JTAG_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
|
||||
#define ESP_EFUSE_DIS_LEGACY_SPI_BOOT ESP_EFUSE_DIS_DIRECT_BOOT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
|
||||
#define ESP_EFUSE_UART_PRINT_CHANNEL ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
|
||||
#define ESP_EFUSE_DIS_USB_DOWNLOAD_MODE ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
|
||||
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
|
||||
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
|
||||
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
|
||||
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */
|
||||
|
||||
#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
|
||||
|
||||
#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
set(EFUSE_SOC_SRCS "esp_efuse_table.c"
|
||||
"esp_efuse_fields.c"
|
||||
"esp_efuse_utility.c")
|
||||
|
|
@ -29,8 +29,8 @@ extern "C" {
|
|||
* @brief Structure range address by blocks
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t start;
|
||||
uint32_t end;
|
||||
uintptr_t start;
|
||||
uintptr_t end;
|
||||
} esp_efuse_range_addr_t;
|
||||
|
||||
/**
|
||||
|
|
@ -235,7 +235,7 @@ void esp_efuse_utility_erase_efuses_in_flash(void);
|
|||
*
|
||||
* @return a numeric read register address of the first word in the block.
|
||||
*/
|
||||
uint32_t esp_efuse_utility_get_read_register_address(esp_efuse_block_t block);
|
||||
uintptr_t esp_efuse_utility_get_read_register_address(esp_efuse_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Checks the correctness of burned data in the given block.
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ esp_err_t esp_efuse_write_field_cnt(const esp_efuse_desc_t* field[], size_t cnt)
|
|||
err = esp_efuse_utility_process(field, &cnt, 0, esp_efuse_utility_write_cnt);
|
||||
|
||||
if (cnt != 0) {
|
||||
ESP_LOGE(TAG, "The required number of bits can not be set. [Not set %d]", cnt);
|
||||
ESP_LOGE(TAG, "The required number of bits can not be set. [Not set %u]", (unsigned)cnt);
|
||||
err = ESP_ERR_EFUSE_CNT_IS_FULL;
|
||||
}
|
||||
if (err == ESP_OK_EFUSE_CNT) {
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ esp_err_t esp_efuse_update_secure_version(uint32_t secure_version)
|
|||
{
|
||||
size_t size = MIN(APP_SEC_VER_SIZE_EFUSE_FIELD, esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION));
|
||||
if (size < secure_version) {
|
||||
ESP_LOGE(TAG, "Max secure version is %d. Given %"PRIu32" version can not be written.", size, secure_version);
|
||||
ESP_LOGE(TAG, "Max secure version is %u. Given %"PRIu32" version can not be written.", (unsigned)size, secure_version);
|
||||
return ESP_ERR_INVALID_ARG;
|
||||
}
|
||||
esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(ESP_EFUSE_SECURE_VERSION_NUM_BLOCK);
|
||||
|
|
|
|||
|
|
@ -150,7 +150,7 @@ void esp_efuse_utility_reset(void)
|
|||
esp_efuse_utility_clear_program_registers();
|
||||
++s_burn_counter;
|
||||
for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
for (uintptr_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
REG_WRITE(addr_wr_block, 0);
|
||||
}
|
||||
}
|
||||
|
|
@ -159,7 +159,7 @@ void esp_efuse_utility_reset(void)
|
|||
void esp_efuse_utility_debug_dump_pending(void)
|
||||
{
|
||||
for (int num_block = 0; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
for (uintptr_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
|
||||
if (REG_READ(addr_wr_block) != 0) {
|
||||
esp_efuse_utility_debug_dump_single_block(num_block, false);
|
||||
break;
|
||||
|
|
@ -203,7 +203,7 @@ void esp_efuse_utility_update_virt_blocks(void)
|
|||
ESP_EARLY_LOGW(TAG, "[Virtual] Loading virtual efuse blocks from real efuses");
|
||||
for (int num_block = EFUSE_BLK0; num_block < EFUSE_BLK_MAX; num_block++) {
|
||||
int subblock = 0;
|
||||
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4) {
|
||||
for (uintptr_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4) {
|
||||
virt_blocks[num_block][subblock++] = REG_READ(addr_rd_block);
|
||||
}
|
||||
ESP_EARLY_LOGD(TAG, "[Virtual] virt_blocks[%d] is filled by EFUSE_BLOCK%d", num_block, num_block);
|
||||
|
|
@ -223,17 +223,17 @@ void esp_efuse_utility_debug_dump_single_block(int num_block, bool from_read)
|
|||
esp_rom_printf("%d) ", num_block);
|
||||
int num_reg = 0;
|
||||
if (from_read) {
|
||||
for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, num_reg++) {
|
||||
for (uintptr_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, num_reg++) {
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
esp_rom_printf("0x%08" PRIx32, virt_blocks[num_block][num_reg]);
|
||||
esp_rom_printf("%08" PRIx32 " ", virt_blocks[num_block][num_reg]);
|
||||
#else
|
||||
esp_rom_printf("0x%08" PRIx32, REG_READ(addr_rd_block));
|
||||
esp_rom_printf("%08" PRIx32 " ", REG_READ(addr_rd_block));
|
||||
(void) num_reg;
|
||||
#endif
|
||||
}
|
||||
} else {
|
||||
for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, num_reg++) {
|
||||
esp_rom_printf("0x%08" PRIx32, REG_READ(addr_wr_block));
|
||||
for (uintptr_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4, num_reg++) {
|
||||
esp_rom_printf("%08" PRIx32 " ", REG_READ(addr_wr_block));
|
||||
}
|
||||
}
|
||||
esp_rom_printf("\n");
|
||||
|
|
@ -291,7 +291,7 @@ static void write_reg(esp_efuse_block_t blk, unsigned int num_reg, uint32_t valu
|
|||
assert(blk >= 0 && blk < EFUSE_BLK_MAX);
|
||||
assert(num_reg <= (range_read_addr_blocks[blk].end - range_read_addr_blocks[blk].start) / sizeof(uint32_t));
|
||||
|
||||
uint32_t addr_wr_reg = range_write_addr_blocks[blk].start + num_reg * 4;
|
||||
uintptr_t addr_wr_reg = range_write_addr_blocks[blk].start + num_reg * 4;
|
||||
uint32_t reg_to_write = REG_READ(addr_wr_reg) | value;
|
||||
// The register can be written in parts so we combine the new value with the one already available.
|
||||
REG_WRITE(addr_wr_reg, reg_to_write);
|
||||
|
|
@ -399,11 +399,11 @@ static bool check_range_of_bits(esp_efuse_block_t blk, int offset_in_bits, int s
|
|||
return true;
|
||||
}
|
||||
|
||||
uint32_t esp_efuse_utility_get_read_register_address(esp_efuse_block_t block)
|
||||
uintptr_t esp_efuse_utility_get_read_register_address(esp_efuse_block_t block)
|
||||
{
|
||||
assert(block < EFUSE_BLK_MAX);
|
||||
#ifdef CONFIG_EFUSE_VIRTUAL
|
||||
return (uint32_t)&virt_blocks[block][0];
|
||||
return (uintptr_t)&virt_blocks[block][0];
|
||||
#else
|
||||
return range_read_addr_blocks[block].start;
|
||||
#endif
|
||||
|
|
@ -501,8 +501,8 @@ void esp_efuse_utility_write_efuses_to_flash(void)
|
|||
|
||||
bool esp_efuse_utility_is_correct_written_data(esp_efuse_block_t block, unsigned r_data_len)
|
||||
{
|
||||
uint32_t* w_data = (uint32_t*)range_write_addr_blocks[block].start;
|
||||
uint32_t* r_data = (uint32_t*)range_read_addr_blocks[block].start;
|
||||
uintptr_t* w_data = (uintptr_t*)range_write_addr_blocks[block].start;
|
||||
uintptr_t* r_data = (uintptr_t*)range_read_addr_blocks[block].start;
|
||||
|
||||
bool correct_written_data = memcmp(w_data, r_data, r_data_len) == 0;
|
||||
if (correct_written_data) {
|
||||
|
|
|
|||
|
|
@ -1,9 +1,9 @@
|
|||
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
|
||||
|
||||
components/efuse/test_apps:
|
||||
enable:
|
||||
- if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux")
|
||||
disable_test:
|
||||
- if: IDF_TARGET in ["esp32s2", "esp32s3"]
|
||||
temporary: true
|
||||
reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3.
|
||||
disable:
|
||||
- if: SOC_EFUSE_SUPPORTED != 1
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -11,18 +11,18 @@
|
|||
#include "unity.h"
|
||||
#include "esp_log.h"
|
||||
#include <string.h>
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "esp_efuse.h"
|
||||
#include "esp_efuse_table.h"
|
||||
#include "esp_efuse_utility.h"
|
||||
#include "esp_efuse_test_table.h"
|
||||
#include "esp_timer.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_random.h"
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/semphr.h"
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_rom_efuse.h"
|
||||
#include "bootloader_common.h"
|
||||
|
||||
#ifdef CONFIG_IDF_TARGET_ESP32
|
||||
#define MAC_FACTORY_HAS_CRC 1
|
||||
|
|
@ -35,6 +35,7 @@ __attribute__((unused)) static const char* TAG = "efuse_test";
|
|||
|
||||
static void test_read_blob(void)
|
||||
{
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
esp_efuse_utility_update_virt_blocks();
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
|
||||
|
|
@ -75,6 +76,7 @@ TEST_CASE("efuse test read_field_blob", "[efuse]")
|
|||
|
||||
static void test_read_cnt(void)
|
||||
{
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
esp_efuse_utility_update_virt_blocks();
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
|
||||
|
|
@ -403,9 +405,7 @@ void test_cnt_part(const esp_efuse_desc_t* field[], uint8_t *arr_r, int arr_size
|
|||
while(field_size > num_bits_summ_r) {
|
||||
num_bits_w = 0;
|
||||
while(num_bits_w == 0 || (num_bits_summ_r + num_bits_w) > field_size) {
|
||||
bootloader_random_enable();
|
||||
bootloader_fill_random(&num_bits_w, 1);
|
||||
bootloader_random_disable();
|
||||
esp_fill_random(&num_bits_w, 1);
|
||||
num_bits_w = num_bits_w * field_size / 255;
|
||||
if (num_bits_w != 0 && (num_bits_summ_r + num_bits_w) <= field_size) {
|
||||
break;
|
||||
|
|
@ -438,16 +438,12 @@ void test_blob_part(const esp_efuse_desc_t* field[], uint8_t *arr_w, uint8_t *ar
|
|||
int num_bits_summ_r = 0;
|
||||
int num_bits_w = 0;
|
||||
memset(arr_w, 0, arr_size);
|
||||
bootloader_random_enable();
|
||||
bootloader_fill_random(arr_w, arr_size);
|
||||
bootloader_random_disable();
|
||||
esp_fill_random(arr_w, arr_size);
|
||||
ESP_LOG_BUFFER_HEX_LEVEL(TAG, arr_w, arr_size, ESP_LOG_INFO);
|
||||
while(field_size > num_bits_summ_r) {
|
||||
num_bits_w = 0;
|
||||
while(num_bits_w == 0 || (num_bits_summ_r + num_bits_w) > field_size) {
|
||||
bootloader_random_enable();
|
||||
bootloader_fill_random(&num_bits_w, 1);
|
||||
bootloader_random_disable();
|
||||
esp_fill_random(&num_bits_w, 1);
|
||||
num_bits_w = num_bits_w * field_size / 255;
|
||||
if (num_bits_w != 0 && (num_bits_summ_r + num_bits_w) <= field_size) {
|
||||
break;
|
||||
|
|
@ -498,9 +494,7 @@ void check_efuse_table_test(int cycle)
|
|||
ESP_LOGI(TAG, "Cycle#%d/%d", c, cycle);
|
||||
|
||||
memset(arr_w, 0, arr_size);
|
||||
bootloader_random_enable();
|
||||
bootloader_fill_random(arr_w, arr_size);
|
||||
bootloader_random_disable();
|
||||
esp_fill_random(arr_w, arr_size);
|
||||
cut_tail_arr(arr_w, 0, field_size);
|
||||
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
|
|
@ -523,6 +517,8 @@ void check_efuse_table_test(int cycle)
|
|||
|
||||
TEST_CASE("efuse esp_efuse_table_test", "[efuse]")
|
||||
{
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(EFUSE_BLK2);
|
||||
if (coding_scheme == EFUSE_CODING_SCHEME_NONE) {
|
||||
check_efuse_table_test(2);
|
||||
|
|
@ -534,6 +530,8 @@ TEST_CASE("efuse esp_efuse_table_test", "[efuse]")
|
|||
|
||||
TEST_CASE("Test esp_efuse_read_block esp_efuse_write_block functions", "[efuse]")
|
||||
{
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
int count_useful_reg = 0;
|
||||
esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(EFUSE_BLK2);
|
||||
if (coding_scheme == EFUSE_CODING_SCHEME_NONE) {
|
||||
|
|
@ -730,6 +728,7 @@ TEST_CASE("Batch mode is thread-safe", "[efuse]")
|
|||
#endif // #ifndef CONFIG_FREERTOS_UNICORE
|
||||
|
||||
|
||||
#if !CONFIG_IDF_TARGET_LINUX
|
||||
static volatile bool cmd_stop_reset_task1;
|
||||
static void efuse_burn_task(void* arg)
|
||||
{
|
||||
|
|
@ -787,6 +786,7 @@ TEST_CASE("Check a case when ESP_ERR_DAMAGED_READING occurs and read and burn ar
|
|||
vSemaphoreDelete(sema[0]);
|
||||
vSemaphoreDelete(sema[1]);
|
||||
}
|
||||
#endif // !CONFIG_IDF_TARGET_LINUX
|
||||
#endif // #ifdef CONFIG_EFUSE_VIRTUAL
|
||||
|
||||
#ifndef CONFIG_FREERTOS_UNICORE
|
||||
|
|
@ -864,5 +864,5 @@ TEST_CASE("Test a real write (FPGA)", "[efuse]")
|
|||
TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]")
|
||||
{
|
||||
esp_efuse_utility_update_virt_blocks();
|
||||
TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), bootloader_common_get_chip_ver_pkg());
|
||||
TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), efuse_ll_get_chip_ver_pkg());
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
#include "esp_efuse_utility.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "unity.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_random.h"
|
||||
|
||||
typedef struct {
|
||||
uint8_t unencoded[24];
|
||||
|
|
@ -107,7 +107,6 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]")
|
|||
int useful_data_in_byte;
|
||||
uint8_t buf[32];
|
||||
uint32_t encoded[8];
|
||||
bootloader_random_enable();
|
||||
esp_efuse_coding_scheme_t coding_scheme = esp_efuse_get_coding_scheme(EFUSE_BLK2);
|
||||
if (coding_scheme == EFUSE_CODING_SCHEME_NONE) {
|
||||
printf("EFUSE_CODING_SCHEME_NONE\n");
|
||||
|
|
@ -127,7 +126,7 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]")
|
|||
memset(buf, 0, sizeof(buf));
|
||||
memset(encoded, 0, sizeof(encoded));
|
||||
// get test data
|
||||
bootloader_fill_random(buf, useful_data_in_byte);
|
||||
esp_fill_random(buf, useful_data_in_byte);
|
||||
memset(buf, 0, i);
|
||||
|
||||
esp_efuse_utility_reset();
|
||||
|
|
@ -176,7 +175,6 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]")
|
|||
TEST_ASSERT_EQUAL_HEX32_ARRAY(buf, w_data_after_coding, 8);
|
||||
}
|
||||
esp_efuse_utility_reset();
|
||||
bootloader_random_disable();
|
||||
}
|
||||
|
||||
TEST_CASE("Test data does not match the coding scheme", "[efuse]")
|
||||
|
|
|
|||
|
|
@ -386,7 +386,11 @@ TEST_CASE("Test esp_efuse_write_keys for returned errors", "[efuse]")
|
|||
TEST_CASE("Test revocation APIs", "[efuse]")
|
||||
{
|
||||
esp_efuse_utility_reset();
|
||||
#ifdef CONFIG_EFUSE_FPGA_TEST
|
||||
esp_efuse_utility_update_virt_blocks();
|
||||
#else
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
#endif
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
|
||||
TEST_ASSERT_FALSE(esp_efuse_get_digest_revoke(0));
|
||||
|
|
@ -422,7 +426,11 @@ TEST_CASE("Test revocation APIs", "[efuse]")
|
|||
TEST_CASE("Test set_write_protect_of_digest_revoke", "[efuse]")
|
||||
{
|
||||
esp_efuse_utility_reset();
|
||||
#ifdef CONFIG_EFUSE_FPGA_TEST
|
||||
esp_efuse_utility_update_virt_blocks();
|
||||
#else
|
||||
esp_efuse_utility_erase_virt_blocks();
|
||||
#endif
|
||||
esp_efuse_utility_debug_dump_blocks();
|
||||
|
||||
TEST_ASSERT_FALSE(esp_efuse_get_digest_revoke(0));
|
||||
|
|
|
|||
|
|
@ -1,16 +1,11 @@
|
|||
# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-License-Identifier: Unlicense OR CC0-1.0
|
||||
|
||||
import pytest
|
||||
from pytest_embedded import Dut
|
||||
|
||||
|
||||
@pytest.mark.esp32
|
||||
@pytest.mark.esp32c2
|
||||
@pytest.mark.esp32c3
|
||||
@pytest.mark.esp32c6
|
||||
@pytest.mark.esp32h2
|
||||
@pytest.mark.esp32p4
|
||||
@pytest.mark.supported_targets
|
||||
@pytest.mark.temp_skip_ci(targets=['esp32s2', 'esp32s3'], reason='eFuse for S2 and S3 is similar to the C3 chip, so testing on C3 is enough')
|
||||
@pytest.mark.generic
|
||||
def test_efuse(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
|
@ -21,3 +16,11 @@ def test_efuse(dut: Dut) -> None:
|
|||
@pytest.mark.host_test
|
||||
def test_efuse_qemu(dut: Dut) -> None:
|
||||
dut.run_all_single_board_cases()
|
||||
|
||||
|
||||
@pytest.mark.linux
|
||||
@pytest.mark.host_test
|
||||
def test_efuse_linux(dut: Dut) -> None:
|
||||
dut.expect_exact('Press ENTER to see the list of tests.')
|
||||
dut.write('*')
|
||||
dut.expect_unity_test_output(timeout=60)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
# General options for additional checks
|
||||
CONFIG_HEAP_POISONING_COMPREHENSIVE=y
|
||||
CONFIG_COMPILER_WARN_WRITE_STRINGS=y
|
||||
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
|
||||
CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK=y
|
||||
CONFIG_COMPILER_STACK_CHECK_MODE_STRONG=y
|
||||
CONFIG_COMPILER_STACK_CHECK=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -49,10 +49,14 @@ extern "C" {
|
|||
if(!(CONDITION)) _ESP_FAULT_RESET(); \
|
||||
} while(0)
|
||||
|
||||
#ifndef CONFIG_IDF_TARGET_ARCH_RISCV
|
||||
#if CONFIG_IDF_TARGET_ARCH_XTENSA
|
||||
#define _ESP_FAULT_ILLEGAL_INSTRUCTION asm volatile("ill.n; ill.n; ill.n; ill.n; ill.n; ill.n; ill.n;")
|
||||
#else
|
||||
#elif CONFIG_IDF_TARGET_ARCH_RISCV
|
||||
#define _ESP_FAULT_ILLEGAL_INSTRUCTION asm volatile("unimp; unimp; unimp; unimp; unimp;")
|
||||
#elif CONFIG_IDF_TARGET_LINUX
|
||||
#define _ESP_FAULT_ILLEGAL_INSTRUCTION
|
||||
#else
|
||||
#error "_ESP_FAULT_ILLEGAL_INSTRUCTION is not defined for this TARGET"
|
||||
#endif
|
||||
|
||||
// Uncomment this macro to get debug output if ESP_FAULT_ASSERT() fails
|
||||
|
|
|
|||
|
|
@ -0,0 +1,7 @@
|
|||
config ESP_REV_MIN_FULL
|
||||
int
|
||||
default 0
|
||||
|
||||
config ESP_REV_MAX_FULL
|
||||
int
|
||||
default 999
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ETS_EFUSE_BLOCK0 = 0,
|
||||
ETS_EFUSE_MAC_SPI_SYS_0 = 1,
|
||||
ETS_EFUSE_BLOCK_SYS_DATA = 2,
|
||||
ETS_EFUSE_BLOCK_USR_DATA = 3,
|
||||
ETS_EFUSE_BLOCK_KEY0 = 4,
|
||||
ETS_EFUSE_BLOCK_KEY1 = 5,
|
||||
ETS_EFUSE_BLOCK_KEY2 = 6,
|
||||
ETS_EFUSE_BLOCK_KEY3 = 7,
|
||||
ETS_EFUSE_BLOCK_KEY4 = 8,
|
||||
ETS_EFUSE_BLOCK_KEY5 = 9,
|
||||
ETS_EFUSE_BLOCK_KEY6 = 10,
|
||||
ETS_EFUSE_BLOCK_MAX,
|
||||
} ets_efuse_block_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -9,7 +9,9 @@
|
|||
#include "esp_attr.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_bit_defs.h"
|
||||
#if !CONFIG_IDF_TARGET_LINUX
|
||||
#include "esp_cpu.h"
|
||||
#endif
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
|
|
|
|||
|
|
@ -124,7 +124,7 @@ extern void vPortCancelThread( void *pxTaskToDelete );
|
|||
* are always a full memory barrier. ISRs are emulated as signals
|
||||
* which also imply a full memory barrier.
|
||||
*
|
||||
* Thus, only a compilier barrier is needed to prevent the compiler
|
||||
* Thus, only a compiler barrier is needed to prevent the compiler
|
||||
* reordering.
|
||||
*/
|
||||
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||
|
|
@ -140,4 +140,6 @@ extern unsigned long ulPortGetRunTime( void );
|
|||
// We need additional definitions for ESP-IDF code
|
||||
#include "portmacro_idf.h"
|
||||
|
||||
void vPortSetStackWatchpoint(void *pxStackStart);
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
*
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* SPDX-FileContributor: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileContributor: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
|
|
@ -564,3 +564,9 @@ unsigned long ulPortGetRunTime( void )
|
|||
return ( unsigned long ) xTimes.tms_utime;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vPortSetStackWatchpoint( void *pxStackStart )
|
||||
{
|
||||
(void) pxStackStart;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -5,15 +5,14 @@ set(includes "platform_port/include")
|
|||
|
||||
# target specific include must be added before the generic one
|
||||
# because of the "include_next" directive used by the efuse_hal.h
|
||||
if(NOT ${target} STREQUAL "linux")
|
||||
list(APPEND includes "${target}/include")
|
||||
list(APPEND includes "${target}/include")
|
||||
|
||||
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
|
||||
list(APPEND includes "${target}/beta3/include")
|
||||
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
|
||||
list(APPEND includes "${target}/mp/include")
|
||||
endif()
|
||||
if(CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION)
|
||||
list(APPEND includes "${target}/beta3/include")
|
||||
elseif(CONFIG_IDF_TARGET_ESP32C5_MP_VERSION)
|
||||
list(APPEND includes "${target}/mp/include")
|
||||
endif()
|
||||
|
||||
list(APPEND includes "include")
|
||||
|
||||
if(CONFIG_SOC_MPU_SUPPORTED)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
IRAM_ATTR uint32_t efuse_hal_get_major_chip_version(void)
|
||||
{
|
||||
return efuse_ll_get_chip_wafer_version_major();
|
||||
}
|
||||
|
||||
IRAM_ATTR uint32_t efuse_hal_get_minor_chip_version(void)
|
||||
{
|
||||
return efuse_ll_get_chip_wafer_version_minor();
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
void efuse_hal_set_timing(uint32_t apb_freq_hz)
|
||||
{
|
||||
(void) apb_freq_hz;
|
||||
}
|
||||
|
||||
void efuse_hal_read(void)
|
||||
{
|
||||
}
|
||||
|
||||
void efuse_hal_clear_program_registers(void)
|
||||
{
|
||||
}
|
||||
|
||||
void efuse_hal_program(uint32_t block)
|
||||
{
|
||||
(void) block;
|
||||
}
|
||||
|
||||
void efuse_hal_rs_calculate(const void *data, void *rs_values)
|
||||
{
|
||||
(void) data;
|
||||
(void) rs_values;
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
bool efuse_hal_is_coding_error_in_block(unsigned block)
|
||||
{
|
||||
(void) block;
|
||||
return false;
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include_next "hal/efuse_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief set eFuse timings
|
||||
*
|
||||
* @param apb_freq_hz APB frequency in Hz
|
||||
*/
|
||||
void efuse_hal_set_timing(uint32_t apb_freq_hz);
|
||||
|
||||
/**
|
||||
* @brief trigger eFuse read operation
|
||||
*/
|
||||
void efuse_hal_read(void);
|
||||
|
||||
/**
|
||||
* @brief clear registers for programming eFuses
|
||||
*/
|
||||
void efuse_hal_clear_program_registers(void);
|
||||
|
||||
/**
|
||||
* @brief burn eFuses written in programming registers (one block at once)
|
||||
*
|
||||
* @param block block number
|
||||
*/
|
||||
void efuse_hal_program(uint32_t block);
|
||||
|
||||
/**
|
||||
* @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
|
||||
*
|
||||
* @param data Pointer to data buffer (length 32 bytes)
|
||||
* @param rs_values Pointer to write encoded data to (length 12 bytes)
|
||||
*/
|
||||
void efuse_hal_rs_calculate(const void *data, void *rs_values);
|
||||
|
||||
/**
|
||||
* @brief Checks coding error in a block
|
||||
*
|
||||
* @param block Index of efuse block
|
||||
*
|
||||
* @return True - block has an error.
|
||||
* False - no error.
|
||||
*/
|
||||
bool efuse_hal_is_coding_error_in_block(unsigned block);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "rom/efuse.h"
|
||||
#include "soc/efuse_periph.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Always inline these functions even no gcc optimization is applied.
|
||||
|
||||
/******************* eFuse fields *************************/
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_flash_crypt_cnt(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_wdt_delay_sel(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac0(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_mac1(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_major_chip_version() to get major chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// use efuse_hal_get_minor_chip_version() to get minor chip version
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_rtc_ldo(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_k_dig_ldo(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_rtc_dbias20(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_v_dig_dbias20(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dig_dbias_hvt(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline bool efuse_ll_get_pgm_cmd(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
|
||||
{
|
||||
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
|
||||
(void) block;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
|
||||
{
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
|
||||
{
|
||||
(void) val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
|
||||
{
|
||||
(void) val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
|
||||
{
|
||||
(void) val;
|
||||
}
|
||||
|
||||
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
|
||||
{
|
||||
(void) value;
|
||||
}
|
||||
|
||||
/******************* eFuse control functions *************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -3,6 +3,14 @@
|
|||
# using gen_soc_caps_kconfig.py, do not edit manually
|
||||
#####################################################
|
||||
|
||||
config SOC_EFUSE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_KEY_PURPOSE_FIELD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GPIO_IN_RANGE_MAX
|
||||
int
|
||||
default 65535
|
||||
|
|
@ -18,3 +26,63 @@ config SOC_I2C_SUPPORT_SLAVE
|
|||
config SOC_I2C_SUPPORT_10BIT_ADDR
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_DOWNLOAD_ICACHE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_DOWNLOAD_DCACHE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_HARD_DIS_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_USB_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_SOFT_DIS_JTAG
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_DIRECT_BOOT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_DIS_ICACHE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SECURE_BOOT_V2_RSA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
|
||||
int
|
||||
default 3
|
||||
|
||||
config SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_128
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_FLASH_ENCRYPTION_XTS_AES_256
|
||||
bool
|
||||
default y
|
||||
|
|
|
|||
|
|
@ -0,0 +1,10 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) do { \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
} while(0)
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
((uint32_t)*(volatile uintptr_t *)(_r)); \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
|
@ -21,6 +21,10 @@
|
|||
|
||||
#pragma once
|
||||
|
||||
/*-------------------------- COMMON CAPS ---------------------------------------*/
|
||||
#define SOC_EFUSE_SUPPORTED (1)
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD (1)
|
||||
|
||||
/*-------------------------- GPIO CAPS ---------------------------------------*/
|
||||
#define SOC_GPIO_IN_RANGE_MAX (65535)
|
||||
#define SOC_GPIO_OUT_RANGE_MAX (65535)
|
||||
|
|
@ -28,3 +32,24 @@
|
|||
/*-------------------------- I2C CAPS ----------------------------------------*/
|
||||
#define SOC_I2C_SUPPORT_SLAVE (1)
|
||||
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
|
||||
|
||||
/*-------------------------- eFuse CAPS----------------------------*/
|
||||
#define SOC_EFUSE_DIS_DOWNLOAD_ICACHE (1)
|
||||
#define SOC_EFUSE_DIS_DOWNLOAD_DCACHE (1)
|
||||
#define SOC_EFUSE_HARD_DIS_JTAG (1)
|
||||
#define SOC_EFUSE_DIS_USB_JTAG (1)
|
||||
#define SOC_EFUSE_SOFT_DIS_JTAG (1)
|
||||
#define SOC_EFUSE_DIS_DIRECT_BOOT (1)
|
||||
#define SOC_EFUSE_DIS_ICACHE (1)
|
||||
|
||||
/*-------------------------- Secure Boot CAPS----------------------------*/
|
||||
#define SOC_SECURE_BOOT_V2_RSA (1)
|
||||
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS (3U)
|
||||
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS (1)
|
||||
#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY (1)
|
||||
|
||||
/*-------------------------- Flash Encryption CAPS----------------------------*/
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES (1)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS (1)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 (1)
|
||||
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 (1)
|
||||
|
|
|
|||
|
|
@ -44,9 +44,15 @@ examples/system/deep_sleep_wake_stub:
|
|||
reason: target(s) is not supported yet # TODO: [ESP32C5] IDF-8638
|
||||
|
||||
examples/system/efuse:
|
||||
enable:
|
||||
- if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux"
|
||||
disable:
|
||||
- if: IDF_TARGET != "esp32" and (NIGHTLY_RUN != "1" or IDF_TARGET == "linux")
|
||||
reason: no target specific functionality, testing on a single target is sufficient
|
||||
- if: IDF_TARGET not in ["esp32", "linux"] and NIGHTLY_RUN != "1"
|
||||
- if: IDF_TARGET == "linux" and CONFIG_NAME == "virt_flash_enc"
|
||||
- if: IDF_TARGET == "linux" and CONFIG_NAME == "virt_flash_enc_release"
|
||||
- if: IDF_TARGET == "linux" and CONFIG_NAME == "virt_sb_v2_and_fe"
|
||||
- if: IDF_TARGET == "linux" and CONFIG_NAME == "virt_secure_boot_v2"
|
||||
reason: Security features are not yet supported for Linux.
|
||||
depends_components:
|
||||
- efuse
|
||||
- bootloader_support
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
|
||||
|
||||
# eFuse Example
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ typedef struct {
|
|||
uint8_t setting_1; /*!< Setting 1: length 6 bits */
|
||||
uint8_t setting_2; /*!< Setting 2: length 5 bits */
|
||||
size_t custom_secure_version; /*!< Custom secure version: length 16 bits */
|
||||
uint16_t reserv; /*!< Reserv */
|
||||
uint16_t reserve; /*!< Reserve */
|
||||
} device_desc_t;
|
||||
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ static void print_device_desc(device_desc_t *desc)
|
|||
}
|
||||
ESP_LOGI(TAG, "setting_1 = %d", desc->setting_1);
|
||||
ESP_LOGI(TAG, "setting_2 = %d", desc->setting_2);
|
||||
ESP_LOGI(TAG, "custom_secure_version = %d", desc->custom_secure_version);
|
||||
ESP_LOGI(TAG, "custom_secure_version = %u", (unsigned)desc->custom_secure_version);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -71,7 +71,7 @@ static void read_efuse_fields(device_desc_t *desc)
|
|||
|
||||
size_t secure_version = 0;
|
||||
ESP_ERROR_CHECK(esp_efuse_read_field_cnt(ESP_EFUSE_SECURE_VERSION, &secure_version));
|
||||
ESP_LOGI(TAG, "2. read secure_version: %d", secure_version);
|
||||
ESP_LOGI(TAG, "2. read secure_version: %u", (unsigned)secure_version);
|
||||
|
||||
ESP_LOGI(TAG, "3. read custom fields");
|
||||
read_device_desc_efuse_fields(desc);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
# SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
# SPDX-License-Identifier: Unlicense OR CC0-1.0
|
||||
from __future__ import unicode_literals
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
|
|
@ -10,11 +8,7 @@ from pytest_embedded import Dut
|
|||
from pytest_embedded_qemu.dut import QemuDut
|
||||
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.esp32
|
||||
@pytest.mark.esp32c2
|
||||
@pytest.mark.esp32c3
|
||||
def test_examples_efuse(dut: Dut) -> None:
|
||||
def basic_efuse_example(dut: Dut) -> None:
|
||||
dut.expect(r'example: Coding Scheme (3/4)|(NONE)|(REPEAT)|(RS \(Reed-Solomon coding\))', timeout=20)
|
||||
dut.expect(['example: read efuse fields',
|
||||
r'example: 1. read MAC address: {}'.format(r':'.join((r'[0-9a-f]{2}',) * 6)),
|
||||
|
|
@ -37,6 +31,20 @@ def test_examples_efuse(dut: Dut) -> None:
|
|||
'example: Done'], expect_all=True)
|
||||
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.esp32
|
||||
@pytest.mark.esp32c2
|
||||
@pytest.mark.esp32c3
|
||||
def test_examples_efuse(dut: Dut) -> None:
|
||||
basic_efuse_example(dut)
|
||||
|
||||
|
||||
@pytest.mark.linux
|
||||
@pytest.mark.host_test
|
||||
def test_examples_efuse_linux(dut: Dut) -> None:
|
||||
basic_efuse_example(dut)
|
||||
|
||||
|
||||
@pytest.mark.generic
|
||||
@pytest.mark.esp32
|
||||
@pytest.mark.esp32c2
|
||||
|
|
|
|||
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_IDF_TARGET="linux"
|
||||
CONFIG_EFUSE_CUSTOM_TABLE=y
|
||||
CONFIG_EFUSE_VIRTUAL=y
|
||||
Ładowanie…
Reference in New Issue