From 8a10ba41791d23cf45cf118e15bc6181f5f0e40f Mon Sep 17 00:00:00 2001 From: Li Shuai Date: Wed, 30 Jun 2021 20:33:07 +0800 Subject: [PATCH] system: fix app cpu core clock gate invalid issue --- components/esp_system/port/cpu_start.c | 6 ++++++ components/soc/esp32s3/include/soc/soc_caps.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index faf2a38eac..c30cb3e1a8 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -413,7 +413,13 @@ void IRAM_ATTR call_start_cpu0(void) DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN); // stop the other core #elif CONFIG_IDF_TARGET_ESP32S3 REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); +#if SOC_APPCPU_HAS_CLOCK_GATING_BUG + /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETING + signals to ensure that the App core stops running in single-core mode. */ + REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING); #endif +#endif // CONFIG_IDF_TARGET_ESP32 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE #endif // SOC_CPU_CORES_NUM > 1 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index a97f63c52a..20432f3735 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -27,6 +27,9 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 #define SOC_PSRAM_DMA_CAPABLE 1 +/*-------------------------- SOC CAPS ----------------------------------------*/ +#define SOC_APPCPU_HAS_CLOCK_GATING_BUG (1) + /*-------------------------- ADC CAPS ----------------------------------------*/ #define SOC_ADC_PERIPH_NUM (2) #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)