kopia lustrzana https://github.com/espressif/esp-idf
Brownout works (in as far brownout can work...), int wdt works.
rodzic
53146799a0
commit
ae5c563080
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@ -151,16 +151,13 @@ config INT_WDT
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interrupt handler did not return. It will try to invoke the panic handler first and failing that
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reset the SoC.
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config INT_WDT_TIMEOUT_MS_MIN
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default (2000/CONFIG_FREERTOS_HZ)
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config INT_WDT_TIMEOUT_MS
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int "Interrupt watchdog timeout (ms)"
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depends on INT_WDT
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default 100
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range INT_WDT_TIMEOUT_MS_MIN 10000
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default 10
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range INT_WDT_TIMEOUT_MIN 10000
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help
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The timeout of the watchdog, in miliseconds.
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The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
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config TASK_WDT
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bool "Task watchdog"
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@ -23,15 +23,9 @@
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void esp_brownout_init() {
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// WRITE_PERI_REG(RTC_CNTL_BROWN_OUT_REG,
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// RTC_CNTL_BROWN_OUT_ENA | (CONFIG_BROWNOUT_DET_LVL << RTC_CNTL_DBROWN_OUT_THRES_S) |
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// RTC_CNTL_BROWN_OUT_RST_ENA | (((CONFIG_BROWNOUT_DET_RESETDELAY*150)/1000) << RTC_CNTL_BROWN_OUT_RST_WAIT_S) |
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// RTC_CNTL_BROWN_OUT_PD_RF_ENA|RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA);
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WRITE_PERI_REG(RTC_CNTL_BROWN_OUT_REG,
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RTC_CNTL_BROWN_OUT_ENA | (4 << RTC_CNTL_DBROWN_OUT_THRES_S) |
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RTC_CNTL_BROWN_OUT_RST_ENA | (0x3FF << RTC_CNTL_BROWN_OUT_RST_WAIT_S) |
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RTC_CNTL_BROWN_OUT_PD_RF_ENA | RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA);
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RTC_CNTL_BROWN_OUT_ENA | (CONFIG_BROWNOUT_DET_LVL << RTC_CNTL_DBROWN_OUT_THRES_S) |
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RTC_CNTL_BROWN_OUT_RST_ENA | (((CONFIG_BROWNOUT_DET_RESETDELAY*150)/1000) << RTC_CNTL_BROWN_OUT_RST_WAIT_S) |
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RTC_CNTL_BROWN_OUT_PD_RF_ENA|RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA);
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}
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@ -44,6 +44,8 @@
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#include "esp_log.h"
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#include "esp_brownout.h"
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#include "esp_int_wdt.h"
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#include "esp_task_wdt.h"
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void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
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void start_cpu0_default(void) IRAM_ATTR;
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@ -143,10 +145,10 @@ void start_cpu0_default(void)
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esp_brownout_init();
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#endif
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#if CONFIG_INT_WDT
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int_wdt_init()
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int_wdt_init();
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#endif
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#if CONFIG_TASK_WDT
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task_wdt_init()
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task_wdt_init();
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#endif
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xTaskCreatePinnedToCore(&main_task, "main",
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@ -47,11 +47,6 @@ This uses the TIMERG1 WDT.
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#define WDT_WRITE_KEY 0x50D83AA1
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static void esp_int_wdt_isr(void *arg) {
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abort();
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}
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void int_wdt_init() {
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TIMERG1.wdt_wprotect=WDT_WRITE_KEY;
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TIMERG1.wdt_config0.sys_reset_length=7; //3.2uS
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@ -67,7 +62,9 @@ void int_wdt_init() {
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TIMERG1.wdt_wprotect=0;
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ESP_INTR_DISABLE(WDT_INT_NUM);
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intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
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xt_set_interrupt_handler(WDT_INT_NUM, int_wdt_isr, NULL);
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//We do not register a handler for the interrupt because it is interrupt level 4 which
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//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
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//this interrupt.
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ESP_INTR_ENABLE(WDT_INT_NUM);
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}
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@ -339,12 +339,12 @@ _xt_panic:
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rsr a0, EXCSAVE_1 /* save interruptee's a0 */
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s32i a0, sp, XT_STK_A0
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/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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/* Set up PS for C, disable all interrupts, and clear EXCM. */
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movi a0, PS_INTLEVEL(7) | PS_UM | PS_WOE
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wsr a0, PS
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//Call panic handler
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mov a2,sp
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mov a6,sp
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call4 panicHandler
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1: j 1b /* loop infinitely */
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@ -1607,6 +1607,13 @@ _xt_highint4:
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ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
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*/
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/* On the ESP32, this level is used for the INT_WDT handler. If that triggers, the program is stuck with interrupts
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off and the CPU should panic. */
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rsr a0, EXCSAVE_4
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wsr a0, EXCSAVE_1 /* panic handler reads this register */
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call0 _xt_panic
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.align 4
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.L_xt_highint4_exit:
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rsr a0, EXCSAVE_4 /* restore a0 */
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