kopia lustrzana https://github.com/espressif/esp-idf
timer: remove check for POWERON_RESET in the test case
The test case may run after an RTC_WDT_RESET (if we are on rev. 0 ESP32), or software reset (when running test cases locally). Also moving the test case next to the other timer group driver tests.pull/4494/head
rodzic
ea99137e62
commit
ad986849a6
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@ -836,3 +836,56 @@ TEST_CASE("Timer interrupt register", "[hw_timer]")
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}
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TEST_ASSERT_INT_WITHIN(100, heap_size, esp_get_free_heap_size());
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}
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// The following test cases are used to check if the timer_group fix works.
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// Some applications use a software reset, at the reset time, timer_group happens to generate an interrupt.
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// but software reset does not clear interrupt status, this is not safe for application when enable the interrupt of timer_group.
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// This case will check under this fix, whether the interrupt status is cleared after timer_group initialization.
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static void timer_group_test_init(void)
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{
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static const uint32_t time_ms = 100; //Alarm value 100ms.
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static const uint16_t timer_div = 10; //Timer prescaler
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static const uint32_t ste_val = time_ms * (TIMER_BASE_CLK / timer_div / 1000);
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timer_config_t config = {
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.divider = timer_div,
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.counter_dir = TIMER_COUNT_UP,
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.counter_en = TIMER_PAUSE,
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.alarm_en = TIMER_ALARM_EN,
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.intr_type = TIMER_INTR_LEVEL,
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.auto_reload = true,
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};
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timer_init(TIMER_GROUP_0, TIMER_0, &config);
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timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
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timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, ste_val);
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//Now the timer is ready.
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//We only need to check the interrupt status and don't have to register a interrupt routine.
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}
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static void timer_group_test_first_stage(void)
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{
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static uint8_t loop_cnt = 0;
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timer_group_test_init();
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//Start timer
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timer_start(TIMER_GROUP_0, TIMER_0);
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//Waiting for timer_group to generate an interrupt
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while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
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loop_cnt++ < 100) {
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vTaskDelay(200);
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}
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//TIMERG0.int_raw.t0 == 1 means an interruption has occurred
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TEST_ASSERT(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
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esp_restart();
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}
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static void timer_group_test_second_stage(void)
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{
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TEST_ASSERT_EQUAL(ESP_RST_SW, esp_reset_reason());
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timer_group_test_init();
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//After the timer_group is initialized, TIMERG0.int_raw.t0 should be cleared.
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TEST_ASSERT_EQUAL(0, TIMERG0.int_raw.t0);
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}
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TEST_CASE_MULTIPLE_STAGES("timer_group software reset test",
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"[intr_status][intr_status = 0]",
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timer_group_test_first_stage,
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timer_group_test_second_stage);
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@ -244,66 +244,4 @@ TEST_CASE_MULTIPLE_STAGES("reset reason ESP_RST_BROWNOUT after brownout event",
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check_reset_reason_brownout);
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// The following test cases are used to check if the timer_group fix works.
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// Some applications use a software reset, at the reset time, timer_group happens to generate an interrupt.
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// but software reset does not clear interrupt status, this is not safe for application when enable the interrupt of timer_group.
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// This case will check under this fix, whether the interrupt status is cleared after timer_group initialization.
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static void timer_group_test_init(void)
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{
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static const uint32_t time_ms = 100; //Alarm value 100ms.
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static const uint16_t timer_div = 10; //Timer prescaler
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static const uint32_t ste_val = time_ms * (TIMER_BASE_CLK / timer_div / 1000);
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timer_config_t config = {
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.divider = timer_div,
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.counter_dir = TIMER_COUNT_UP,
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.counter_en = TIMER_PAUSE,
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.alarm_en = TIMER_ALARM_EN,
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.intr_type = TIMER_INTR_LEVEL,
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.auto_reload = true,
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};
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timer_init(TIMER_GROUP_0, TIMER_0, &config);
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timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
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timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, ste_val);
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//Now the timer is ready.
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//We only need to check the interrupt status and don't have to register a interrupt routine.
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}
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static void timer_group_test_first_stage(void)
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{
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RESET_REASON rst_res = rtc_get_reset_reason(0);
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if(rst_res != POWERON_RESET){
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printf("Not power on reset\n");
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}
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TEST_ASSERT_EQUAL(POWERON_RESET, rst_res);
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static uint8_t loop_cnt = 0;
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timer_group_test_init();
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//Start timer
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timer_start(TIMER_GROUP_0, TIMER_0);
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//Waiting for timer_group to generate an interrupt
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while( !(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0) &&
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loop_cnt++ < 100) {
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vTaskDelay(200);
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}
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//TIMERG0.int_raw.t0 == 1 means an interruption has occurred
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TEST_ASSERT(timer_group_get_intr_status_in_isr(TIMER_GROUP_0) & TIMER_INTR_T0);
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esp_restart();
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}
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static void timer_group_test_second_stage(void)
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{
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RESET_REASON rst_res = rtc_get_reset_reason(0);
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if(rst_res != SW_CPU_RESET){
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printf("Not software reset\n");
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}
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TEST_ASSERT_EQUAL(SW_CPU_RESET, rst_res);
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timer_group_test_init();
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//After the timer_group is initialized, TIMERG0.int_raw.t0 should be cleared.
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TEST_ASSERT_EQUAL(0, TIMERG0.int_raw.t0);
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}
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TEST_CASE_MULTIPLE_STAGES("timer_group software reset test",
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"[intr_status][intr_status = 0]",
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timer_group_test_first_stage,
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timer_group_test_second_stage);
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/* Not tested here: ESP_RST_SDIO */
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