Merge branch 'bugfix/fix_adc_oneshot_do_not_spilt_clk_v4.4' into 'release/v4.4'

fix(adc): fix ADC oneshot mod don't divide clk (v4.4)

See merge request espressif/esp-idf!26705

components/hal/adc_hal.c

@@ -491,6 +491,8 @@ static bool adc_hal_intr_get_raw(adc_hal_event_t event)
 //--------------------Single Read-------------------------------//
 static void adc_hal_onetime_start(void)
 {
+    adc_ll_digi_controller_clk_div(ADC_LL_CLKM_DIV_NUM_DEFAULT, ADC_LL_CLKM_DIV_B_DEFAULT, ADC_LL_CLKM_DIV_A_DEFAULT);
+    adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
     /**
      * There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the
      * ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller