Merge branch 'bugfix/spi_flash_unlock_once' into 'master'

components/spi_flash: call SPIUnlock once

This fixes the performance impact for spi_flash_write and spi_flash_erase.
With this change, NVS init in single core mode takes about 50ms (compared to >2seconds before that).

For dual core mode, we still spend on average 2ms for each spi_flash_ operation due to synchronization between CPUs, so NVS startup time is about 2 seconds in dual core mode.

See merge request !80

components/spi_flash/esp_spi_flash.c

@@ -178,11 +178,24 @@ static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
 #endif // CONFIG_FREERTOS_UNICORE
 
 
+SpiFlashOpResult IRAM_ATTR spi_flash_unlock()
+{
+    static bool unlocked = false;
+    if (!unlocked) {
+        SpiFlashOpResult rc = SPIUnlock();
+        if (rc != SPI_FLASH_RESULT_OK) {
+            return rc;
+        }
+        unlocked = true;
+    }
+    return SPI_FLASH_RESULT_OK;
+}
+
 esp_err_t IRAM_ATTR spi_flash_erase_sector(uint16_t sec)
 {
     spi_flash_disable_interrupts_caches_and_other_cpu();
     SpiFlashOpResult rc;
-    rc = SPIUnlock();
+    rc = spi_flash_unlock();
     if (rc == SPI_FLASH_RESULT_OK) {
         rc = SPIEraseSector(sec);
     }
@@ -194,7 +207,7 @@ esp_err_t IRAM_ATTR spi_flash_write(uint32_t dest_addr, const uint32_t *src, uin
 {
     spi_flash_disable_interrupts_caches_and_other_cpu();
     SpiFlashOpResult rc;
-    rc = SPIUnlock();
+    rc = spi_flash_unlock();
     if (rc == SPI_FLASH_RESULT_OK) {
         rc = SPIWrite(dest_addr, src, (int32_t) size);
     }