fix reboot or crash when enable lightsleep on esp32s2

components/esp_system/CMakeLists.txt

@@ -22,3 +22,8 @@ set_source_files_properties(
     startup.c
     PROPERTIES COMPILE_FLAGS
     -fno-stack-protector)
+
+if(NOT CMAKE_BUILD_EARLY_EXPANSION)
+    set_source_files_properties("${CMAKE_CURRENT_LIST_DIR}/sleep_modes.c" PROPERTIES
+                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
+endif()

components/esp_system/sleep_modes.c

@@ -71,10 +71,10 @@
 #endif
 
 #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS)
-#define LIGHT_SLEEP_TIME_OVERHEAD_US (650 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (1650 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #else
-#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
+#define LIGHT_SLEEP_TIME_OVERHEAD_US (1250 + 30 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #endif
 
@@ -232,11 +232,9 @@ static void IRAM_ATTR resume_uarts(void)
         REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
 #elif CONFIG_IDF_TARGET_ESP32S2
         if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
-            REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
-            REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XOFF);
-            while (REG_GET_FIELD(UART_FSM_STATUS_REG(i), UART_ST_UTX_OUT) != 0) {
-                ;
-            }
+            REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
+            REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XON);
+            REG_CLR_BIT(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | UART_FORCE_XON);
         }
 #endif
     }

components/esp_system/startup.c

@@ -370,10 +370,17 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
     esp_pm_impl_init();
 #ifdef CONFIG_PM_DFS_INIT_AUTO
     int xtal_freq = (int) rtc_clk_xtal_freq_get();
+#ifdef CONFIG_IDF_TARGET_ESP32
     esp_pm_config_esp32_t cfg = {
         .max_freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ,
         .min_freq_mhz = xtal_freq,
     };
+#else
+esp_pm_config_esp32s2_t cfg = {
+        .max_freq_mhz = CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ,
+        .min_freq_mhz = xtal_freq,
+    };
+#endif
     esp_pm_configure(&cfg);
 #endif //CONFIG_PM_DFS_INIT_AUTO
 #endif //CONFIG_PM_ENABLE

components/hal/esp32s2/include/hal/clk_gate_ll.h

@@ -274,7 +274,7 @@ static inline void periph_ll_reset(periph_module_t periph)
 
 static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
 {
-    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) != 0 &&
+    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
         DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
 }