kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'docs/provide_User_Guide_for_ESP32-Ethernet-Kit-V1.2' into 'master'
Provide getting started guide for ESP32-Ethernet-Kit-V1.2 based on V1.1 See merge request espressif/esp-idf!9786pull/5688/head
Krzysztof Budzynski
commit
a6c1834327
Plik binarny nie jest wyświetlany.
|
Po Szerokość: | Wysokość: | Rozmiar: 112 KiB |
Plik binarny nie jest wyświetlany.
|
Po Szerokość: | Wysokość: | Rozmiar: 526 KiB |
Plik binarny nie jest wyświetlany.
|
Po Szerokość: | Wysokość: | Rozmiar: 180 KiB |
|
|
@ -367,5 +367,7 @@ Related Documents
|
|||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
For other design documentation for the board, please contact us at sales@espressif.com.
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.0 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
|
|
|
|||
|
|
@ -0,0 +1,402 @@
|
|||
ESP32-Ethernet-Kit V1.1 Getting Started Guide
|
||||
=============================================
|
||||
|
||||
:link_to_translation:`zh_CN:[中文]`
|
||||
|
||||
This guide shows how to get started with the ESP32-Ethernet-Kit development board and also provides information about its functionality and configuration options.
|
||||
|
||||
The :ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.1>` is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE).
|
||||
|
||||
What You Need
|
||||
-------------
|
||||
|
||||
* :ref:`ESP32-Ethernet-Kit V1.1 board <get-started-esp32-ethernet-kit-v1.1>`
|
||||
* USB 2.0 A to Micro B Cable
|
||||
* Computer running Windows, Linux, or macOS
|
||||
|
||||
You can skip the introduction sections and go directly to Section `Start Application Development`_.
|
||||
|
||||
Overview
|
||||
--------
|
||||
|
||||
ESP32-Ethernet-Kit is an ESP32-based development board produced by `Espressif <https://espressif.com>`_.
|
||||
|
||||
It consists of two development boards, the Ethernet board A and the PoE board B. The :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` contains Bluetooth / Wi-Fi dual-mode ESP32-WROVER-B module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed.
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1.png
|
||||
:align: center
|
||||
:alt: ESP32-Ethernet-Kit V1.1
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.1
|
||||
|
||||
For the application loading and monitoring, the Ethernet board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger.
|
||||
|
||||
|
||||
Functionality Overview
|
||||
----------------------
|
||||
|
||||
The block diagram below shows the main components of ESP32-Ethernet-Kit and their interconnections.
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1-block-diagram.png
|
||||
:align: center
|
||||
:scale: 60%
|
||||
:alt: ESP32-Ethernet-Kit block diagram (click to enlarge)
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit block diagram (click to enlarge)
|
||||
|
||||
|
||||
Functional Description
|
||||
----------------------
|
||||
|
||||
The following figures and tables describe the key components, interfaces, and controls of the ESP32-Ethernet-Kit.
|
||||
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.1-layout:
|
||||
|
||||
Ethernet Board (A)
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.1-layout.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - Ethernet board (A) layout
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - Ethernet board (A) layout (click to enlarge)
|
||||
|
||||
The table below provides description starting from the picture's top right corner and going clockwise.
|
||||
|
||||
================== ===========================================================================
|
||||
Key Component Description
|
||||
================== ===========================================================================
|
||||
ESP32-WROVER-B This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities.
|
||||
|
||||
GPIO Header 2 Five unpopulated through-hole solder pads to provide access to selected GPIOs of ESP32. For details, see `GPIO Header 2`_.
|
||||
|
||||
Function Switch A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. Please note that placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. For details and correct pin allocation see `Function Switch`_.
|
||||
|
||||
Tx/Rx LEDs Two LEDs to show the status of UART transmission.
|
||||
|
||||
FT2232H The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
|
||||
|
||||
USB Port USB interface. Power supply for the board as well as the communication interface between a computer and the board.
|
||||
|
||||
Power Switch Power On/Off Switch. Toggling the switch to **5V0** position powers the board on, toggling to **GND** position powers the board off.
|
||||
|
||||
5V Input The 5V power supply interface can be more convenient when the board is operating autonomously (not connected to a computer).
|
||||
|
||||
5V Power On LED This red LED turns on when power is supplied to the board, either from USB or 5V Input.
|
||||
|
||||
DC/DC Converter Provided DC 5 V to 3.3 V conversion, output current up to 2A.
|
||||
|
||||
Board B Connectors A pair male and female header pins for mounting the `PoE board (B)`_.
|
||||
|
||||
IP101GRI (PHY) The physical layer (PHY) connection to the Ethernet cable is implemented using the `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ standard. The PHY supports the IEEE 802.3 / 802.3u standard of 10/100Mbps.
|
||||
|
||||
RJ45 Port Ethernet network data transmission port.
|
||||
|
||||
Magnetics Module The Magnetics are part of the Ethernet specification to protect against faults and transients, including rejection of common mode signals between the transceiver IC and the cable. The magnetics also provide galvanic isolation between the transceiver and the Ethernet device.
|
||||
|
||||
Link/Activity LEDs Two LEDs (green and red) that respectively indicate the "Link" and "Activity" statuses of the PHY.
|
||||
|
||||
BOOT Button Download button. Holding down **BOOT** and then pressing **EN** initiates Firmware Download mode for downloading firmware through the serial port.
|
||||
|
||||
EN Button Reset button.
|
||||
|
||||
GPIO Header 1 This header provides six unpopulated through-hole solder pads connected to spare GPIOs of ESP32. For details, see `GPIO Header 1`_.
|
||||
|
||||
================== ===========================================================================
|
||||
|
||||
PoE Board (B)
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
This board coverts power delivered over the Ethernet cable (PoE) to provide a power supply for the Ethernet board (A). The main components of the PoE board (B) are shown on the block diagram under `Functionality Overview`_.
|
||||
|
||||
The PoE board (B) has the following features:
|
||||
|
||||
* Support for IEEE 802.3at
|
||||
* Power output: 5 V, 1.4 A
|
||||
|
||||
To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet board (A) should be connected with an Ethernet cable to a switch that supports PoE. When the Ethernet board (A) detects 5 V power output from the PoE board (B), the USB power will be automatically cut off.
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-b-v1.0-layout.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - PoE board (B)
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - PoE board (B) layout (click to enlarge)
|
||||
|
||||
.. list-table:: Table PoE board (B)
|
||||
:widths: 40 150
|
||||
:header-rows: 1
|
||||
|
||||
* - Key Component
|
||||
- Description
|
||||
* - Board A Connector
|
||||
- Four female (left) and four male (right) header pins for connecting the PoE board (B) to :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>`. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the Ethernet board (A).
|
||||
* - External Power Terminals
|
||||
- Optional power supply (26.6 ~ 54 V) to the PoE board (B).
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1-setup-options:
|
||||
|
||||
Setup Options
|
||||
-------------
|
||||
|
||||
This section describes options to configure the ESP32-Ethernet-Kit hardware.
|
||||
|
||||
|
||||
Function Switch
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
When in On position, this DIP switch is routing listed GPIOs to FT2232H to provide JTAG functionality. When in Off position, the GPIOs may be used for other purposes.
|
||||
|
||||
======= ================
|
||||
DIP SW GPIO Pin
|
||||
======= ================
|
||||
1 GPIO13
|
||||
2 GPIO12
|
||||
3 GPIO15
|
||||
4 GPIO14
|
||||
======= ================
|
||||
|
||||
.. note::
|
||||
|
||||
Placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. Please use instead the pin order as in the table above.
|
||||
|
||||
|
||||
RMII Clock Selection
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e. RMII clock) that can be provided either externally, or generated from internal ESP32 APLL.
|
||||
|
||||
.. note::
|
||||
|
||||
For additional information on the RMII clock selection, please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2.
|
||||
|
||||
RMII Clock Sourced Externally by PHY
|
||||
""""""""""""""""""""""""""""""""""""
|
||||
|
||||
By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency multiplication of 25 MHz crystal connected to the PHY. For details, please see the figure below.
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-from-phy.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: RMII Clock from IP101GRI PHY
|
||||
:figclass: align-center
|
||||
|
||||
RMII Clock from IP101GRI PHY
|
||||
|
||||
Please note that the PHY is reset on power up by pulling the RESET_N signal down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter download mode (when the clock signal of REF_CLK_50M is at a high logic level during the GPIO0 power-up sampling phase).
|
||||
|
||||
RMII Clock Sourced Internally from ESP32's APLL
|
||||
"""""""""""""""""""""""""""""""""""""""""""""""
|
||||
|
||||
Another option is to source the RMII Clock from internal ESP32 APLL, see figure below. The clock signal coming from GPIO0 is first inverted, to account for transmission line delay, and then supplied to the PHY.
|
||||
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-to-phy.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: RMII Clock from ESP Internal APLL
|
||||
:figclass: align-center
|
||||
|
||||
RMII Clock from ESP Internal APLL
|
||||
|
||||
To implement this option, users need to remove or add some RC components on the board. For details please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock.
|
||||
|
||||
|
||||
GPIO Allocation
|
||||
---------------
|
||||
|
||||
This section describes allocation of ESP32 GPIOs to specific interfaces or functions of the ESP32-Ethernet-Kit.
|
||||
|
||||
|
||||
IP101GRI (PHY) Interface
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table below. Implementation of ESP32-Ethernet-Kit defaults to Reduced Media-Independent Interface (RMII).
|
||||
|
||||
==== ================ ===============
|
||||
. ESP32 Pin (MAC) IP101GRI (PHY)
|
||||
==== ================ ===============
|
||||
*RMII Interface*
|
||||
---------------------------------------
|
||||
1 GPIO21 TX_EN
|
||||
2 GPIO19 TXD[0]
|
||||
3 GPIO22 TXD[1]
|
||||
4 GPIO25 RXD[0]
|
||||
5 GPIO26 RXD[1]
|
||||
6 GPIO27 CRS_DV
|
||||
7 GPIO0 REF_CLK
|
||||
---- ---------------- ---------------
|
||||
*Serial Management Interface*
|
||||
---------------------------------------
|
||||
8 GPIO23 MDC
|
||||
9 GPIO18 MDIO
|
||||
---- ---------------- ---------------
|
||||
*PHY Reset*
|
||||
---------------------------------------
|
||||
10 GPIO5 Reset_N
|
||||
==== ================ ===============
|
||||
|
||||
.. note::
|
||||
|
||||
Except for REF_CLK, the allocation of all pins under the ESP32's *RMII Interface* is fixed and cannot be changed either through IOMUX or GPIO Matrix.
|
||||
|
||||
|
||||
GPIO Header 1
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
This header exposes some GPIOs that are not used elsewhere on the ESP32-Ethernet-Kit.
|
||||
|
||||
==== ================
|
||||
. ESP32 Pin
|
||||
==== ================
|
||||
1 GPIO32
|
||||
2 GPIO33
|
||||
3 GPIO34
|
||||
4 GPIO35
|
||||
5 GPIO36
|
||||
6 GPIO39
|
||||
==== ================
|
||||
|
||||
|
||||
GPIO Header 2
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
This header contains GPIOs that may be used for other purposes depending on scenarios described in column "Comments".
|
||||
|
||||
==== ========== ====================
|
||||
. ESP32 Pin Comments
|
||||
==== ========== ====================
|
||||
1 GPIO17 See note 1
|
||||
2 GPIO16 See note 1
|
||||
3 GPIO4
|
||||
4 GPIO2
|
||||
5 GPIO13 See note 2
|
||||
6 GPIO12 See note 2
|
||||
7 GPIO15 See note 2
|
||||
8 GPIO14 See note 2
|
||||
9 GND Ground
|
||||
10 3V3 3.3 V power supply
|
||||
==== ========== ====================
|
||||
|
||||
.. note::
|
||||
|
||||
1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
|
||||
2. Functionality depends on the settings of the `Function Switch`_.
|
||||
|
||||
|
||||
GPIO Allocation Summary
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. csv-table::
|
||||
:header: ESP32-WROVER-B,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
|
||||
S_VP,,,,IO36,
|
||||
S_VN,,,,IO39,
|
||||
IO34,,,,IO34,
|
||||
IO35,,,,IO35,
|
||||
IO32,,,,IO32,
|
||||
IO33,,,,IO33,
|
||||
IO25,RXD[0],,,,
|
||||
IO26,RXD[1],,,,
|
||||
IO27,CRS_DV,,,,
|
||||
IO14,,,TMS,IO14,
|
||||
IO12,,,TDI,IO12,
|
||||
IO13,,RTS,TCK,IO13,
|
||||
IO15,,CTS,TDO,IO15,
|
||||
IO2,,,,IO2,
|
||||
IO0,REF_CLK,,,,See note 1
|
||||
IO4,,,,IO4,
|
||||
IO16,,,,IO16 (NC),See note 2
|
||||
IO17,,,,IO17 (NC),See note 2
|
||||
IO5,Reset_N,,,,See note 1
|
||||
IO18,MDIO,,,,
|
||||
IO19,TXD[0],,,,
|
||||
IO21,TX_EN,,,,
|
||||
RXD0,,RXD,,,
|
||||
TXD0,,TXD,,,
|
||||
IO22,TXD[1],,,,
|
||||
IO23,MDC,,,,
|
||||
|
||||
.. note::
|
||||
|
||||
1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side, the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module that can be disabled / enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
|
||||
|
||||
2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
|
||||
|
||||
Start Application Development
|
||||
-----------------------------
|
||||
|
||||
Before powering up your ESP32-Ethernet-Kit, please make sure that the board is in good condition with no obvious signs of damage.
|
||||
|
||||
Initial Setup
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
1. Set the **Function Switch** on the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to its default position by turning all the switches to **ON**.
|
||||
2. To simplify flashing and testing of the application, do not input extra signals to the board headers.
|
||||
3. The `PoE board (B)`_ can now be plugged in, but do not connect external power to it.
|
||||
4. Connect the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to the PC with a USB cable.
|
||||
5. Turn the **Power Switch** from GND to 5V0 position, the **5V Power On LED** should light up.
|
||||
|
||||
|
||||
Now to Development
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Proceed to :doc:`../../get-started/index`, where Section :ref:`get-started-step-by-step` will quickly help you set up the development environment and then flash an example project onto your board.
|
||||
|
||||
Move on to the next section only if you have successfully completed all the above steps.
|
||||
|
||||
|
||||
Configure and Load the Ethernet Example
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
After setting up the development environment and testing the board, you can configure and flash the :example:`ethernet/basic` example. This example has been created for testing Ethernet functionality. It supports different PHY, including **IP101GRI** installed on :ref:`get-started-esp32-ethernet-kit-v1.1`.
|
||||
|
||||
|
||||
Summary of Changes from ESP32-Ethernet-Kit V1.0
|
||||
-----------------------------------------------
|
||||
|
||||
* The original inverted clock provided to the PHY by ESP32 using GPIO0 has been replaced by a clock generated on PHY side. The PHY's clock is connected to the ESP32 with same GPIO0. The GPIO2 which was originally used to control the active crystal oscillator on the PHY side, can now be used for other purposes.
|
||||
* On power up, the ESP32 boot strapping pin GPIO0 may be affected by clock generated on the PHY side. To resolve this issue the PHY's Reset-N signal is pulled low using resistor R17 and effectively turning off the PHY's clock output. The Reset-N signal can be then pulled high by ESP32 using GPIO5.
|
||||
* Removed FT2232H chip's external SPI Flash U6.
|
||||
* Removed flow control jumper header J4.
|
||||
* Removed nTRST JTAG signal. The corresponding GPIO4 can now be used for other purposes.
|
||||
* Pull-up resistor R68 on the GPIO15 line is moved to the MTDO side of JTAG.
|
||||
* To make the A and B board connections more foolproof (reduce chances of plugging in the B board in reverse orientation), the original two 4-pin male rows on board A were changed to one 4-pin female row and one 4-pin male row. Corresponding male and female 4-pins rows were installed on board B.
|
||||
|
||||
|
||||
Other Versions of ESP32-Ethernet-Kit
|
||||
------------------------------------
|
||||
|
||||
* :doc:`get-started-ethernet-kit-v1.0`
|
||||
|
||||
|
||||
Related Documents
|
||||
-----------------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 PoE board (B) schematic`_ (PDF)
|
||||
* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-B Datasheet <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_en.pdf>`_ (PDF)
|
||||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
For other design documentation for the board, please contact us at sales@espressif.com.
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
|
||||
get-started-ethernet-kit-v1.0.rst
|
||||
|
|
@ -1,16 +1,26 @@
|
|||
ESP32-Ethernet-Kit V1.1 Getting Started Guide
|
||||
ESP32-Ethernet-Kit V1.2 Getting Started Guide
|
||||
=============================================
|
||||
|
||||
:link_to_translation:`zh_CN:[中文]`
|
||||
|
||||
This guide shows how to get started with the ESP32-Ethernet-Kit development board and also provides information about its functionality and configuration options.
|
||||
|
||||
The :ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.1>` is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE).
|
||||
The :ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.2>` is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide more flexible power supply options, the ESP32-Ethernet-Kit also supports power over Ethernet (PoE).
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.2-overview:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.2-overview.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit V1.2
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.2 Overview (click to enlarge)
|
||||
|
||||
What You Need
|
||||
-------------
|
||||
|
||||
* :ref:`ESP32-Ethernet-Kit V1.1 board <get-started-esp32-ethernet-kit-v1.1>`
|
||||
* :ref:`ESP32-Ethernet-Kit V1.2 board <get-started-esp32-ethernet-kit-v1.2>`
|
||||
* USB 2.0 A to Micro B Cable
|
||||
* Computer running Windows, Linux, or macOS
|
||||
|
||||
|
|
@ -21,16 +31,17 @@ Overview
|
|||
|
||||
ESP32-Ethernet-Kit is an ESP32-based development board produced by `Espressif <https://espressif.com>`_.
|
||||
|
||||
It consists of two development boards, the Ethernet board A and the PoE board B. The :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` contains Bluetooth / Wi-Fi dual-mode ESP32-WROVER-B module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed.
|
||||
It consists of two development boards, the Ethernet board A and the PoE board B. The :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` contains Bluetooth/Wi-Fi dual-mode ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet functionality. The A board can work independently, without the board B installed.
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1:
|
||||
.. _get-started-esp32-ethernet-kit-v1.2:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1.png
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.2.jpg
|
||||
:align: center
|
||||
:alt: ESP32-Ethernet-Kit V1.1
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit V1.2
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.1
|
||||
ESP32-Ethernet-Kit V1.2 (click to enlarge)
|
||||
|
||||
For the application loading and monitoring, the Ethernet board (A) also features FTDI FT2232H chip - an advanced multi-interface USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface without a separate JTAG debugger.
|
||||
|
||||
|
|
@ -55,15 +66,15 @@ Functional Description
|
|||
The following figures and tables describe the key components, interfaces, and controls of the ESP32-Ethernet-Kit.
|
||||
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.1-layout:
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.2-layout:
|
||||
|
||||
Ethernet Board (A)
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.1-layout.png
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.2-layout.jpg
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - Ethernet board (A) layout
|
||||
:alt: ESP32-Ethernet-Kit V1.2 (click to enlarge)
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - Ethernet board (A) layout (click to enlarge)
|
||||
|
|
@ -73,15 +84,16 @@ The table below provides description starting from the picture's top right corne
|
|||
================== ===========================================================================
|
||||
Key Component Description
|
||||
================== ===========================================================================
|
||||
ESP32-WROVER-B This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities.
|
||||
ESP32-WROVER-E This ESP32 module features 64-Mbit PSRAM for flexible extended storage and data processing capabilities.
|
||||
|
||||
GPIO Header 2 Five unpopulated through-hole solder pads to provide access to selected GPIOs of ESP32. For details, see `GPIO Header 2`_.
|
||||
|
||||
Function Switch A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. Please note that placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. For details and correct pin allocation see `Function Switch`_.
|
||||
Function Switch A 4-bit DIP switch used to configure the functionality of selected GPIOs of ESP32. For details see `Function Switch`_.
|
||||
|
||||
|
||||
Tx/Rx LEDs Two LEDs to show the status of UART transmission.
|
||||
|
||||
FT2232H The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
|
||||
FT2232H The FT2232H chip serves as a multi-protocol USB-to-serial bridge which can be programmed and controlled via USB to provide communication with ESP32. FT2232H also features USB-to-JTAG interface which is available on channel A of the chip, while USB-to-serial is on channel B. The FT2232H chip enhances user-friendliness in terms of application development and debugging. See `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
|
||||
|
||||
USB Port USB interface. Power supply for the board as well as the communication interface between a computer and the board.
|
||||
|
||||
|
|
@ -91,11 +103,11 @@ Power Switch Power On/Off Switch. Toggling the switch to **5V0** position
|
|||
|
||||
5V Power On LED This red LED turns on when power is supplied to the board, either from USB or 5V Input.
|
||||
|
||||
DC/DC Converter Provided DC 5 V to 3.3 V conversion, output current up to 2A.
|
||||
DC/DC Converter Provided DC 5 V to 3.3 V conversion, output current up to 2 A.
|
||||
|
||||
Board B Connectors A pair male and female header pins for mounting the `PoE board (B)`_.
|
||||
|
||||
IP101GRI (PHY) The physical layer (PHY) connection to the Ethernet cable is implemented using the `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ standard. The PHY supports the IEEE 802.3 / 802.3u standard of 10/100Mbps.
|
||||
IP101GRI (PHY) The physical layer (PHY) connection to the Ethernet cable is implemented using the `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ chip. The connection between PHY and ESP32 is done through the reduced media-independent interface (RMII), a variant of the media-independent interface `(MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 Mbps.
|
||||
|
||||
RJ45 Port Ethernet network data transmission port.
|
||||
|
||||
|
|
@ -111,6 +123,10 @@ GPIO Header 1 This header provides six unpopulated through-hole solder pad
|
|||
|
||||
================== ===========================================================================
|
||||
|
||||
.. note::
|
||||
|
||||
Automatic firmware download is supported. If following steps and using software described in Section `Start Application Development`_, users don't need to do any operation with BOOT button or EN button.
|
||||
|
||||
PoE Board (B)
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
|
|
@ -138,11 +154,11 @@ To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet boa
|
|||
* - Key Component
|
||||
- Description
|
||||
* - Board A Connector
|
||||
- Four female (left) and four male (right) header pins for connecting the PoE board (B) to :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>`. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the Ethernet board (A).
|
||||
- Four female (left) and four male (right) header pins for connecting the PoE board (B) to :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>`. The pins on the left accept power coming from a PoE switch. The pins on the right deliver 5 V power supply to the Ethernet board (A).
|
||||
* - External Power Terminals
|
||||
- Optional power supply (26.6 ~ 54 V) to the PoE board (B).
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1-setup-options:
|
||||
.. _get-started-esp32-ethernet-kit-v1.2-setup-options:
|
||||
|
||||
Setup Options
|
||||
-------------
|
||||
|
|
@ -164,19 +180,15 @@ DIP SW GPIO Pin
|
|||
4 GPIO14
|
||||
======= ================
|
||||
|
||||
.. note::
|
||||
|
||||
Placement of GPIO pin number marking on the board's silkscreen besides the DIP switch is incorrect. Please use instead the pin order as in the table above.
|
||||
|
||||
|
||||
RMII Clock Selection
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e. RMII clock) that can be provided either externally, or generated from internal ESP32 APLL.
|
||||
The ethernet MAC and PHY under RMII working mode need a common 50 MHz reference clock (i.e. RMII clock) that can be provided either externally, or generated from internal ESP32 APLL (not recommended).
|
||||
|
||||
.. note::
|
||||
|
||||
For additional information on the RMII clock selection, please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2.
|
||||
For additional information on the RMII clock selection, please refer to `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_, sheet 2, location D2.
|
||||
|
||||
RMII Clock Sourced Externally by PHY
|
||||
""""""""""""""""""""""""""""""""""""
|
||||
|
|
@ -207,8 +219,7 @@ Another option is to source the RMII Clock from internal ESP32 APLL, see figure
|
|||
|
||||
RMII Clock from ESP Internal APLL
|
||||
|
||||
To implement this option, users need to remove or add some RC components on the board. For details please refer to `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock.
|
||||
|
||||
To implement this option, users need to remove or add some RC components on the board. For details please refer to `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_, sheet 2, location D2. Please note that if the APLL is already used for other purposes (e.g. I2S peripheral), then you have no choice but use an external RMII clock.
|
||||
|
||||
GPIO Allocation
|
||||
---------------
|
||||
|
|
@ -222,7 +233,7 @@ IP101GRI (PHY) Interface
|
|||
The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table below. Implementation of ESP32-Ethernet-Kit defaults to Reduced Media-Independent Interface (RMII).
|
||||
|
||||
==== ================ ===============
|
||||
. ESP32 Pin (MAC) IP101GRI (PHY)
|
||||
No. ESP32 Pin (MAC) IP101GRI (PHY)
|
||||
==== ================ ===============
|
||||
*RMII Interface*
|
||||
---------------------------------------
|
||||
|
|
@ -246,7 +257,7 @@ The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table b
|
|||
|
||||
.. note::
|
||||
|
||||
Except for REF_CLK, the allocation of all pins under the ESP32's *RMII Interface* is fixed and cannot be changed either through IOMUX or GPIO Matrix.
|
||||
The allocation of all pins under the ESP32's *RMII Interface* is fixed and cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through GPIO Matrix.
|
||||
|
||||
|
||||
GPIO Header 1
|
||||
|
|
@ -255,7 +266,7 @@ GPIO Header 1
|
|||
This header exposes some GPIOs that are not used elsewhere on the ESP32-Ethernet-Kit.
|
||||
|
||||
==== ================
|
||||
. ESP32 Pin
|
||||
No. ESP32 Pin
|
||||
==== ================
|
||||
1 GPIO32
|
||||
2 GPIO33
|
||||
|
|
@ -272,7 +283,7 @@ GPIO Header 2
|
|||
This header contains GPIOs that may be used for other purposes depending on scenarios described in column "Comments".
|
||||
|
||||
==== ========== ====================
|
||||
. ESP32 Pin Comments
|
||||
No. ESP32 Pin Comments
|
||||
==== ========== ====================
|
||||
1 GPIO17 See note 1
|
||||
2 GPIO16 See note 1
|
||||
|
|
@ -288,7 +299,7 @@ This header contains GPIOs that may be used for other purposes depending on scen
|
|||
|
||||
.. note::
|
||||
|
||||
1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
|
||||
2. Functionality depends on the settings of the `Function Switch`_.
|
||||
|
||||
|
|
@ -297,7 +308,7 @@ GPIO Allocation Summary
|
|||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. csv-table::
|
||||
:header: ESP32-WROVER-B,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
:header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
|
||||
S_VP,,,,IO36,
|
||||
S_VN,,,,IO39,
|
||||
|
|
@ -310,8 +321,8 @@ GPIO Allocation Summary
|
|||
IO27,CRS_DV,,,,
|
||||
IO14,,,TMS,IO14,
|
||||
IO12,,,TDI,IO12,
|
||||
IO13,,RTS,TCK,IO13,
|
||||
IO15,,CTS,TDO,IO15,
|
||||
IO13,,,TCK,IO13,
|
||||
IO15,,,TDO,IO15,
|
||||
IO2,,,,IO2,
|
||||
IO0,REF_CLK,,,,See note 1
|
||||
IO4,,,,IO4,
|
||||
|
|
@ -328,9 +339,9 @@ GPIO Allocation Summary
|
|||
|
||||
.. note::
|
||||
|
||||
1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side, the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module that can be disabled / enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_.
|
||||
1. To prevent the power-on state of the GPIO0 from being affected by the clock output on the PHY side, the RESET_N signal to PHY defaults to low, turning the clock output off. After power-on you can control RESET_N with GPIO5 to turn the clock output on. See also `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off the clock output through RESET_N, it is recommended to use a crystal module that can be disabled/enabled externally. Similarly like when using RESET_N, the oscillator module should be disabled by default and turned on by ESP32 after power-up. For a reference design please see `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
|
||||
|
||||
2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-B module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the ESP32-WROVER-E module and therefore not available for use. If you need to use these pins, please solder a module without PSRAM memory inside, e.g. the ESP32-WROOM-32D or ESP32-SOLO-1.
|
||||
|
||||
|
||||
Start Application Development
|
||||
|
|
@ -341,10 +352,10 @@ Before powering up your ESP32-Ethernet-Kit, please make sure that the board is i
|
|||
Initial Setup
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
1. Set the **Function Switch** on the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to its default position by turning all the switches to **ON**.
|
||||
1. Set the **Function Switch** on the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` to its default position by turning all the switches to **ON**.
|
||||
2. To simplify flashing and testing of the application, do not input extra signals to the board headers.
|
||||
3. The `PoE board (B)`_ can now be plugged in, but do not connect external power to it.
|
||||
4. Connect the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>` to the PC with a USB cable.
|
||||
4. Connect the :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>` to the PC with a USB cable.
|
||||
5. Turn the **Power Switch** from GND to 5V0 position, the **5V Power On LED** should light up.
|
||||
|
||||
|
||||
|
|
@ -359,42 +370,44 @@ Move on to the next section only if you have successfully completed all the abov
|
|||
Configure and Load the Ethernet Example
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
After setting up the development environment and testing the board, you can configure and flash the :example:`ethernet/basic` example. This example has been created for testing Ethernet functionality. It supports different PHY, including **IP101GRI** installed on :ref:`get-started-esp32-ethernet-kit-v1.1`.
|
||||
After setting up the development environment and testing the board, you can configure and flash the :example:`ethernet/basic` example. This example has been created for testing Ethernet functionality. It supports different PHY, including **IP101GRI** installed on :ref:`get-started-esp32-ethernet-kit-v1.2`.
|
||||
|
||||
|
||||
Summary of Changes from ESP32-Ethernet-Kit V1.0
|
||||
Summary of Changes from ESP32-Ethernet-Kit V1.1
|
||||
-----------------------------------------------
|
||||
|
||||
* The original inverted clock provided to the PHY by ESP32 using GPIO0 has been replaced by a clock generated on PHY side. The PHY's clock is connected to the ESP32 with same GPIO0. The GPIO2 which was originally used to control the active crystal oscillator on the PHY side, can now be used for other purposes.
|
||||
* On power up, the ESP32 boot strapping pin GPIO0 may be affected by clock generated on the PHY side. To resolve this issue the PHY's Reset-N signal is pulled low using resistor R17 and effectively turning off the PHY's clock output. The Reset-N signal can be then pulled high by ESP32 using GPIO5.
|
||||
* Removed FT2232H chip's external SPI Flash U6.
|
||||
* Removed flow control jumper header J4.
|
||||
* Removed nTRST JTAG signal. The corresponding GPIO4 can now be used for other purposes.
|
||||
* Pull-up resistor R68 on the GPIO15 line is moved to the MTDO side of JTAG.
|
||||
* To make the A and B board connections more foolproof (reduce chances of plugging in the B board in reverse orientation), the original two 4-pin male rows on board A were changed to one 4-pin female row and one 4-pin male row. Corresponding male and female 4-pins rows were installed on board B.
|
||||
* Correct the placement of GPIO pin number marking on the board’s silkscreen besides the DIP switch.
|
||||
* Values of C1, C2, C42, and C43 are updated to 20 pF. For more information, please check `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_.
|
||||
* Replace ESP32-WROVER-B with ESP32-WROVER-E.
|
||||
|
||||
|
||||
Other Versions of ESP32-Ethernet-Kit
|
||||
------------------------------------
|
||||
|
||||
* :doc:`get-started-ethernet-kit-v1.0`
|
||||
* :doc:`get-started-ethernet-kit-v1.1`
|
||||
|
||||
|
||||
Related Documents
|
||||
-----------------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 PoE board (B) schematic`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit PoE board (B) schematic`_ (PDF)
|
||||
* `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-B Datasheet <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_en.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-E Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf>`_ (PDF)
|
||||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
For other design documentation for the board, please contact us at sales@espressif.com.
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.1 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit PoE board (B) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.2 Ethernet board (A) schematic: https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
|
||||
get-started-ethernet-kit-v1.0.rst
|
||||
get-started-ethernet-kit-v1.1.rst
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ ESP32-Ethernet-Kit V1.0 入门指南
|
|||
概述
|
||||
--------
|
||||
|
||||
ESP32-Ethernet-Kit 是一款来自 `乐鑫 <https://espressif.com>`_ 的开发板，由以太网子板（A 板）和 PoE 子板（B 板）两部分组成。其中 :ref:`以太网子板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>` 贴蓝牙 / Wi-Fi 双模 ESP32-WROVER-B 模组和单端口 10/100 快速以太网收发器 (PHY) IP101GRI。:ref:`PoE 子板（B 板） <get-started-esp32-ethernet-kit-b-v1.0-layout>` 提供以太网供电功能。ESP32-Ethernet-Kit 的 A 板可在不连接 B 板的情况下独立工作。
|
||||
ESP32-Ethernet-Kit 是一款来自 `乐鑫 <https://espressif.com>`_ 的开发板，由以太网母板（A 板）和 PoE 子板（B 板）两部分组成。其中 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>` 贴蓝牙 / Wi-Fi 双模 ESP32-WROVER-B 模组和单端口 10/100 快速以太网收发器 (PHY) IP101GRI。:ref:`PoE 子板（B 板） <get-started-esp32-ethernet-kit-b-v1.0-layout>` 提供以太网供电功能。ESP32-Ethernet-Kit 的 A 板可在不连接 B 板的情况下独立工作。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-b-v1.0:
|
||||
|
||||
|
|
@ -56,16 +56,16 @@ ESP32-Ethernet-Kit 开发板的主要组件、接口及控制方式见下。
|
|||
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.0-layout:
|
||||
|
||||
以太网子板（A 板）
|
||||
以太网母板（A 板）
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.0-layout.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - 以太网子板（A 板）布局
|
||||
:alt: ESP32-Ethernet-Kit - 以太网母板（A 板）布局
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - 以太网子板（A 板）布局（点击放大）
|
||||
ESP32-Ethernet-Kit - 以太网母板（A 板）布局（点击放大）
|
||||
|
||||
下表将从图片右上角开始，以顺时针顺序介绍图中的主要组件。
|
||||
|
||||
|
|
@ -84,7 +84,7 @@ Tx/Rx LED 2 个 LED，可显示 UART 传输的状态。
|
|||
|
||||
GPIO Header 3 可连接至 ESP32 的部分 GPIO，根据 `功能选择开关`_ 的位置有不同功能。
|
||||
|
||||
FT2232H FT2232H 多协议 USB 转串口桥接器。开发人员可通过 USB 接口对 FT2232H 芯片进行控制和编程，与 ESP32 建立连接。FT2232H 芯片可在通道 A 提供 USB-to-JTAG 接口功能，并在通道 B 提供 USB-to-Serial 接口功能，便利开发人员的应用开发与调试。见 `ESP32-Ethernet-Kit V1.0 以太网子板（A 板）原理图`_。
|
||||
FT2232H FT2232H 多协议 USB 转串口桥接器。开发人员可通过 USB 接口对 FT2232H 芯片进行控制和编程，与 ESP32 建立连接。FT2232H 芯片可在通道 A 提供 USB-to-JTAG 接口功能，并在通道 B 提供 USB-to-Serial 接口功能，便利开发人员的应用开发与调试。见 `ESP32-Ethernet-Kit V1.0 以太网母板（A 板）原理图`_。
|
||||
|
||||
USB 端口 USB 接口。可用作开发板的供电电源，或连接 PC 和开发板的通信接口。
|
||||
|
||||
|
|
@ -100,7 +100,7 @@ B 板连接器 1 对 2 针排针，用于连接 :ref:`PoE 子板
|
|||
|
||||
IP101GRI (PHY) 物理层 (PHY) 单端口10/100 快速以太网收发器 `IP101GRI`_ ，允许开发人员实现与以太网线缆的物理层连接。PHY 与 ESP32 通过简化媒体独立接口 (RMII) 实现连接。RMII 是 `媒体独立接口 (MII)`_ 的简化版本。PHY 可在 10/100 Mbps 速率下支持 IEEE 802.3 / 802.3u 标准。
|
||||
|
||||
RJ45 端口 以太网数据传输断口。
|
||||
RJ45 端口 以太网数据传输端口。
|
||||
|
||||
网络变压器 网络变压器属于以太网物理层的一部分，可保护电路免受故障和电压瞬变影响，包括防止收发器芯片和线缆之间产生共模信号。同时它也可以在收发器与以太网设备之间提供电流隔绝。
|
||||
|
||||
|
|
@ -118,14 +118,14 @@ GPIO Header 1 由 6 个未引出通孔组成，可连接至 ESP32
|
|||
PoE 子板（B 板）
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
PoE 子板通过以太网电缆传输电能 (PoE)，为以太网子板（A 板）提供电源。PoE 子板（B 板）的主要组件见 `功能概述`_ 中的功能框图。
|
||||
PoE 子板通过以太网电缆传输电能 (PoE)，为以太网母板（A 板）提供电源。PoE 子板（B 板）的主要组件见 `功能概述`_ 中的功能框图。
|
||||
|
||||
PoE 子板（B 板）具有以下特性：
|
||||
|
||||
* 支持 IEEE 802.3at
|
||||
* 电源输出：5 V，1.4 A
|
||||
|
||||
如需使用 PoE 功能，请用以太网线缆将以太网子板（A 板）上的 **RJ45 端口** 连接至 PoE 的交换机。太网子板（A 板）检测到来自 PoE 子板（B 板）的 5 V 供电后，将从 USB 供电自动切换至 PoE 供电。
|
||||
如需使用 PoE 功能，请用以太网线缆将以太网母板（A 板）上的 **RJ45 端口** 连接至 PoE 的交换机。太网母板（A 板）检测到来自 PoE 子板（B 板）的 5 V 供电后，将从 USB 供电自动切换至 PoE 供电。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-b-v1.0-layout.png
|
||||
:align: center
|
||||
|
|
@ -138,7 +138,7 @@ PoE 子板（B 板）具有以下特性：
|
|||
========================== =================================================================================================================================
|
||||
主要组件 基本介绍
|
||||
========================== =================================================================================================================================
|
||||
A 板连接器 1 个 4 针排母，用于将 B 板连接至 :ref:`以太网子板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>`。
|
||||
A 板连接器 1 个 4 针排母，用于将 B 板连接至 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>`。
|
||||
外部电源终端 PoE 子板（B 板）备用电源。
|
||||
========================== =================================================================================================================================
|
||||
|
||||
|
|
@ -260,13 +260,13 @@ GPIO Header 2
|
|||
.. note::
|
||||
|
||||
1. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-B 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 SPIRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
2. 具体功能取决与 `功能选择开关`_ 的设置。
|
||||
2. 具体功能取决于 `功能选择开关`_ 的设置。
|
||||
|
||||
|
||||
GPIO Header 3
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
本连接器中 GPIO 的功能取决与 `功能选择开关`_ 的设置。
|
||||
本连接器中 GPIO 的功能取决于 `功能选择开关`_ 的设置。
|
||||
|
||||
==== ===========
|
||||
. ESP32 管脚
|
||||
|
|
@ -330,10 +330,10 @@ ESP32-Ethernet-Kit 上电前，请首先确认开发板完好无损。
|
|||
初始设置
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
1. 首先，请将 :ref:`以太网子板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>` 上的所有开关均拨至 **ON** 状态，即使 **功能选择开关** 处于默认状态。
|
||||
2. 为了方便应用程序的下载和测试，此时请不要在开发板安装任何条线帽，也不要为开发板接入任何信号。
|
||||
1. 首先，请将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.0-layout>` 上的所有开关均拨至 **ON** 状态，即使 **功能选择开关** 处于默认状态。
|
||||
2. 为了方便应用程序的下载和测试，此时请不要在开发板安装任何跳线帽，也不要为开发板接入任何信号。
|
||||
3. 此时可以连接 :ref:`PoE 子板（B 板） <get-started-esp32-ethernet-kit-b-v1.0-layout>`，但不要向 B 板连接任何外部电源。
|
||||
4. 使用 USB 数据线将 :ref:`以太网子板（A 板） <get-started-esp32-ethernet-kit-a-v1.0-layout>` 连接至 PC。
|
||||
4. 使用 USB 数据线将 :ref:`以太网母板（A 板） <get-started-esp32-ethernet-kit-a-v1.0-layout>` 连接至 PC。
|
||||
5. 将 **电源开关** 从 GND 拨至 5V0 一侧。此时，**5V Power On LED** 应点亮。
|
||||
|
||||
|
||||
|
|
@ -356,14 +356,16 @@ ESP32-Ethernet-Kit 上电前，请首先确认开发板完好无损。
|
|||
相关文档
|
||||
-----------------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.0 以太网子板（A 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 以太网母板（A 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图`_ (PDF)
|
||||
* `《ESP32 技术规格书》 <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_cn.pdf>`_ (PDF)
|
||||
* `《ESP32-WROVER-B 技术规格书》 <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_cn.pdf>`_ (PDF)
|
||||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.0 以太网子板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
有关本开发板的更多设计文档，请联系我们的商务部门 sales@espressif.com。
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.0 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _IP101GRI: http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf
|
||||
.. _媒体独立接口 (MII): https://en.wikipedia.org/wiki/Media-independent_interface
|
||||
|
|
|
|||
|
|
@ -0,0 +1,411 @@
|
|||
ESP32-Ethernet-Kit V1.1 入门指南
|
||||
=================================
|
||||
|
||||
:link_to_translation:`en:[English]`
|
||||
|
||||
本指南将介绍 ESP32-Ethernet-Kit 开发板的配置以及相关功能的使用。
|
||||
|
||||
:ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.1>` 是一款以太网转 Wi-Fi 开发板，可为以太网设备赋予 Wi-Fi 连接功能。为了提供更灵活的电源选项，ESP32-Ethernet-Kit 同时也支持以太网供电 (PoE)。
|
||||
|
||||
|
||||
准备工作
|
||||
--------
|
||||
|
||||
* :ref:`ESP32-Ethernet-Kit V1.1 开发板 <get-started-esp32-ethernet-kit-v1.1>`
|
||||
* USB 数据线（A 转 Micro-B）
|
||||
* PC（Windows、Linux 或 Mac OS）
|
||||
|
||||
您可以跳过介绍部分，直接前往 `应用程序开发`_ 章节。
|
||||
|
||||
|
||||
概述
|
||||
----
|
||||
|
||||
ESP32-Ethernet-Kit 是一款来自 `乐鑫 <https://espressif.com>`_ 的开发板。
|
||||
|
||||
它由 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 和 `PoE 子板（B 板）`_ 两部分组成。其中 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 集成蓝牙 / Wi-Fi 双模 ESP32-WROVER-B 模组和单端口 10/100 Mbps 快速以太网收发器 (PHY) IP101GRI。`PoE 子板（B 板）`_ 提供以太网供电功能。ESP32-Ethernet-Kit 的 A 板可在不连接 B 板的情况下独立工作。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1.png
|
||||
:align: center
|
||||
:alt: ESP32-Ethernet-Kit V1.1
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.1
|
||||
|
||||
为了实现程序下载和监控，A 板还集成了一款先进多协议 USB 桥接器（FTDI FT2232H 芯片）。FTDI FT2232H 芯片使得开发人员无需额外的 JTAG 适配器，通过 USB 桥接器使用 JTAG 接口便可对 ESP32 直接进行调试。
|
||||
|
||||
|
||||
功能概述
|
||||
---------
|
||||
|
||||
ESP32-Ethernet-Kit 开发板的主要组件和连接方式如下。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1-block-diagram.png
|
||||
:align: center
|
||||
:scale: 60%
|
||||
:alt: ESP32-Ethernet-Kit 功能框图（点击放大）
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit 功能框图（点击放大）
|
||||
|
||||
|
||||
功能说明
|
||||
--------
|
||||
|
||||
有关 ESP32-Ethernet-Kit 开发板的主要组件、接口及控制方式，请见下方的图片和表格。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.1-layout:
|
||||
|
||||
|
||||
以太网母板（A 板）
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.1-layout.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - Ethernet board (A) layout
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - 以太网母板（A 板）布局（点击放大）（请更新图片）
|
||||
|
||||
下表将从图片右上角开始，以顺时针顺序介绍图中的主要组件。
|
||||
|
||||
.. list-table:: 表格1 组件介绍
|
||||
:widths: 40 150
|
||||
:header-rows: 1
|
||||
|
||||
* - 主要组件
|
||||
- 基本介绍
|
||||
* - ESP32-WROVER-B 模组
|
||||
- 这款 ESP32 模组内置 64-Mbit PSRAM，可提供灵活的额外存储空间和数据处理能力。
|
||||
* - GPIO Header 2
|
||||
- 由 5 个未引出通孔组成，可连接至 ESP32 的部分 GPIO。具体介绍，请见 `GPIO Header 2`_。
|
||||
* - 功能选择开关
|
||||
- 一个 4 位拨码开关，可配置 ESP32 部分 GPIO 的功能。请注意，拨码开关旁边开发板的丝印层上的 GPIO 管脚标记的位置是不正确的。有关详细信息和正确的管脚分配，请见 `功能选择开关`_。
|
||||
* - Tx/Rx LEDs
|
||||
- 2 个 LED，可显示 UART 传输的状态。
|
||||
* - FT2232H
|
||||
- FT2232H 多协议 USB 转串口桥接器。开发人员可通过 USB 接口对 FT2232H 芯片进行控制和编程，与 ESP32 建立连接。FT2232H 芯片可在通道 A 提供 USB-to-JTAG 接口功能，并在通道 B 提供 USB-to-Serial 接口功能，便利开发人员的应用开发与调试。见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_。
|
||||
* - USB 端口
|
||||
- USB 接口。可用作开发板的供电电源，或连接 PC 和开发板的通信接口。
|
||||
* - 电源开关
|
||||
- 电源开关。拨向 **5V0** 按键侧，开发板上电；拨向 **GND** 按键一侧，开发板掉电。
|
||||
* - 5V Input
|
||||
- 5V 电源接口建议仅在开发板自动运行（未连接 PC）时使用。
|
||||
* - 5V Power On LED
|
||||
- 当开发板通电后（USB 或外部 5V 供电），该红色指示灯将亮起。
|
||||
* - DC/DC 转换器
|
||||
- 直流 5 V 转 3.3 V，输出电流最高可达 2 A。
|
||||
* - Board B 连接器
|
||||
- 1 对 排针和排母，用于连接 `PoE 子板（B 板）`_。
|
||||
* - IP101GRI (PHY)
|
||||
- 物理层 (PHY) 单端口 10/100 快速以太网收发器 `IP101GRI <http://www.bdtic.com/DataSheet/ICplus/IP101G_DS_R01_20121224.pdf>`_ 芯片，允许开发人员实现与以太网线缆的物理层连接。PHY 与 ESP32 通过简化媒体独立接口 (RMII) 实现连接。RMII 是 `媒体独立接口 (MII) <https://en.wikipedia.org/wiki/Media-independent_interface>`_ 的标准简化版本。PHY 可在 10/100 Mbps 速率下支持 IEEE 802.3 / 802.3u 标准。
|
||||
* - RJ45 端口
|
||||
- 以太网数据传输端口。
|
||||
* - 网络变压器
|
||||
- 网络变压器属于以太网物理层的一部分，可保护电路，使其免受故障和电压瞬变影响，包括防止收发器芯片和线缆之间产生共模信号。同时它也可以在收发器与以太网设备之间提供电流隔绝。
|
||||
* - Link/Activity LED
|
||||
- 2 个 LED（绿色和红色），可分别显示 PHY 处于 “Link” 状态或 “Activity” 状态。
|
||||
* - BOOT Button
|
||||
- 下载按键。按下 **BOOT** 键并保持，同时按一下 **EN** 键（此时不要松开 **BOOT** 键）进入“固件下载”模式，通过串口下载固件。
|
||||
* - EN 按键
|
||||
- 复位按键。
|
||||
* - GPIO Header 1
|
||||
- 由 6 个未引出通孔组成，可连接至 ESP32 的备用 GPIO。具体介绍，请见 `GPIO Header 1`_。
|
||||
|
||||
|
||||
PoE 子板（B 板）
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
PoE 子板转换以太网电缆传输的电能 (PoE)，为以太网母板（A 板）提供电源。PoE 子板（B 板）的主要组件见 `功能概述`_ 中的功能框图。
|
||||
|
||||
PoE 子板（B 板）具有以下特性：
|
||||
|
||||
* 支持 IEEE 802.3at 标准
|
||||
* 电源输出：5 V，1.4 A
|
||||
|
||||
如需使用 PoE 功能，请用以太网线缆将以太网母板（A 板）上的 **RJ45 Port** 连接至 PoE 的交换机。以太网母板（A 板）检测到来自 PoE 子板（B 板）的 5 V 供电后，将从 USB 供电自动切换至 PoE 供电。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-b-v1.0-layout.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - PoE board (B)
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - PoE 子板（B 板）布局（点击放大）
|
||||
|
||||
.. list-table:: 表格2 PoE 子板（B 板）
|
||||
:widths: 40 150
|
||||
:header-rows: 1
|
||||
|
||||
* - 主要组件
|
||||
- 基本介绍
|
||||
* - A 板连接器
|
||||
- 4 个排针（左侧）和排母（右侧），用于将 PoE 子板（B 板）连接至 :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>`。左侧的管脚接受来自 PoE 交换机的电源。右侧的管脚为 以太网母板（A 板）提供 5 V 电源。
|
||||
* - 外部电源终端
|
||||
- PoE 子板（B 板）可选电源 (26.6 ~ 54 V)。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1-setup-options:
|
||||
|
||||
|
||||
设置选项
|
||||
--------
|
||||
|
||||
本节介绍用于 ESP32-Ethernet-Kit 开发板的硬件配置选项。
|
||||
|
||||
|
||||
功能选择开关
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
拨码开关打开时，拨码开关将列出的 GPIO 路由到 FT2232H 以提供JTAG功能。拨码开关关闭时，GPIO 可以用于其他目的。
|
||||
|
||||
========= ==========
|
||||
拨码开关 GPIO 管脚
|
||||
========= ==========
|
||||
1 GPIO13
|
||||
2 GPIO12
|
||||
3 GPIO15
|
||||
4 GPIO14
|
||||
========= ==========
|
||||
|
||||
.. note::
|
||||
|
||||
拨码开关旁边开发板的丝印层上的 GPIO 管脚标记的位置是不正确的。请以表格中的顺序为准。
|
||||
|
||||
|
||||
RMII 时钟源选择
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
RMII 工作模式下的以太网 MAC 和 PHY 需要一个公共的 50MHz 同步时钟（即 RMII 时钟），它既可以由外部提供，也可以由内部的 ESP32 APLL 产生。
|
||||
|
||||
.. note::
|
||||
|
||||
有关 RMII 时钟源选择的更多信息，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_，第 2 页的位置 D2。
|
||||
|
||||
|
||||
PHY 侧提供 RMII 时钟
|
||||
"""""""""""""""""""""""""""""
|
||||
|
||||
ESP32-Ethernet-Kit 默认配置为 IP101GRI 的 50M_CLKO 信号线提供 RMII 时钟，该时钟信号由 PHY 外侧连接的 25MHz 无源晶振经过倍频产生。详情请参见下图。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-from-phy.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: RMII Clock from IP101GRI PHY
|
||||
:figclass: align-center
|
||||
|
||||
PHY 侧提供 RMII 时钟
|
||||
|
||||
请注意，系统上电时 RESET_N 旁的下拉电阻会将 PHY 置于复位状态，ESP32 需要通过 GPIO5 将 RESET_N 拉高才能启动 PHY，只有这样才能保证系统的正常上电，否则 ESP32 会存在一定几率进入下载模式（当 REF_CLK_50M 时钟信号在 GPIO0 上电采样阶段刚好处于高电平）。
|
||||
|
||||
|
||||
ESP32 APLL 内部提供的 RMII 时钟
|
||||
""""""""""""""""""""""""""""""""""""
|
||||
|
||||
另一种选择是从 ESP32 APLL 内部获取 RMII 时钟，请参见下图。来自 GPIO0 的时钟信号首先被反相，以解决传输线延迟的问题，然后提供给 PHY。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-to-phy.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: RMII Clock from ESP Internal APLL
|
||||
:figclass: align-center
|
||||
|
||||
ESP32 APLL 内部提供的 RMII 时钟
|
||||
|
||||
要实现此选项，用户需要在板子上移除或添加一些阻容元器件。有关详细信息，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_，第 2 页，位置 D2。请注意，如果 APLL 已经用于其他用途（如 I2S 外设），那么只能使用外部 RMII 时钟。
|
||||
|
||||
|
||||
GPIO 分配
|
||||
---------
|
||||
|
||||
本节介绍了 ESP32-Ethernet-Kit 开发板特定接口或功能的 GPIO 分配情况。
|
||||
|
||||
|
||||
IP101GRI (PHY) 接口
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
下表显示了 ESP32 (MAC) 与 IP101GRI (PHY) 的管脚对应关系。ESP32-Ethernet-Kit 的实现默认设置为简化媒体独立接口。
|
||||
|
||||
==== ================ ===============
|
||||
. ESP32 管脚 (MAC) IP101GRI (PHY)
|
||||
==== ================ ===============
|
||||
*RMII 接口*
|
||||
---------------------------------------
|
||||
1 GPIO21 TX_EN
|
||||
2 GPIO19 TXD[0]
|
||||
3 GPIO22 TXD[1]
|
||||
4 GPIO25 RXD[0]
|
||||
5 GPIO26 RXD[1]
|
||||
6 GPIO27 CRS_DV
|
||||
7 GPIO0 REF_CLK
|
||||
---- ---------------- ---------------
|
||||
*串行管理接口*
|
||||
---------------------------------------
|
||||
8 GPIO23 MDC
|
||||
9 GPIO18 MDIO
|
||||
---- ---------------- ---------------
|
||||
*PHY 复位*
|
||||
---------------------------------------
|
||||
10 GPIO5 Reset_N
|
||||
==== ================ ===============
|
||||
|
||||
.. Note::
|
||||
|
||||
除了 REF_CLK 之外，ESP32 的 *RMII 接口* 下的所有管脚分配都是固定的，不能通过 IOMUX 或 GPIO 矩阵进行更改。
|
||||
|
||||
|
||||
GPIO Header 1
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
本连接器包括 ESP32-Ethernet-Kit 开发板上部分不用做他用的 GPIO。
|
||||
|
||||
==== ================
|
||||
. ESP32 管脚
|
||||
==== ================
|
||||
1 GPIO32
|
||||
2 GPIO33
|
||||
3 GPIO34
|
||||
4 GPIO35
|
||||
5 GPIO36
|
||||
6 GPIO39
|
||||
==== ================
|
||||
|
||||
|
||||
GPIO Header 2
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
根据“说明"描述的不同情形，本连接器包含可用做他用的 GPIO。
|
||||
|
||||
==== ========== ====================
|
||||
. ESP32 管脚 说明
|
||||
==== ========== ====================
|
||||
1 GPIO17 见下方说明 1
|
||||
2 GPIO16 见下方说明 1
|
||||
3 GPIO4
|
||||
4 GPIO2
|
||||
5 GPIO13 见下方说明 2
|
||||
6 GPIO12 见下方说明 2
|
||||
7 GPIO15 见下方说明 2
|
||||
8 GPIO14 见下方说明 2
|
||||
9 GND Ground
|
||||
10 3V3 3.3 V 电源
|
||||
==== ========== ====================
|
||||
|
||||
.. note::
|
||||
|
||||
1. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-B 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
|
||||
|
||||
2. 具体功能取决于 `功能选择开关`_ 的设置。
|
||||
|
||||
|
||||
GPIO 管脚分配总结
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. csv-table::
|
||||
:header: ESP32-WROVER-B,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
|
||||
S_VP,,,,IO36,
|
||||
S_VN,,,,IO39,
|
||||
IO34,,,,IO34,
|
||||
IO35,,,,IO35,
|
||||
IO32,,,,IO32,
|
||||
IO33,,,,IO33,
|
||||
IO25,RXD[0],,,,
|
||||
IO26,RXD[1],,,,
|
||||
IO27,CRS_DV,,,,
|
||||
IO14,,,TMS,IO14,
|
||||
IO12,,,TDI,IO12,
|
||||
IO13,,RTS,TCK,IO13,
|
||||
IO15,,CTS,TDO,IO15,
|
||||
IO2,,,,IO2,
|
||||
IO0,REF_CLK,,,,See note 1
|
||||
IO4,,,,IO4,
|
||||
IO16,,,,IO16 (NC),See note 2
|
||||
IO17,,,,IO17 (NC),See note 2
|
||||
IO5,Reset_N,,,,See note 1
|
||||
IO18,MDIO,,,,
|
||||
IO19,TXD[0],,,,
|
||||
IO21,TX_EN,,,,
|
||||
RXD0,,RXD,,,
|
||||
TXD0,,TXD,,,
|
||||
IO22,TXD[1],,,,
|
||||
IO23,MDC,,,,
|
||||
|
||||
.. note::
|
||||
|
||||
1. 为防止 ESP32 侧 GPIO0 的上电状态受 PHY 侧时钟输出的影响，PHY 侧 RESET_N 默认为低，以关闭 PHY 侧时钟输出。上电后，您可通过 GPIO5 控制 RESET_N 以打开该时钟输出。参见 `PHY 侧提供 RMII 时钟`_。对于无法通过 RESET_N 关闭时钟输出的 PHY，PHY 侧建议使用可在外部禁用/使能的有源晶振。与使用 RESET_N 类似，默认情况下晶振模块应禁用，并在上电后由 ESP32 开启。有关参考设计，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_。
|
||||
|
||||
|
||||
2. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-B 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
|
||||
|
||||
应用程序开发
|
||||
-------------
|
||||
|
||||
ESP32-Ethernet-Kit 上电前，请首先确认开发板完好无损。
|
||||
|
||||
|
||||
初始设置
|
||||
^^^^^^^^^^
|
||||
|
||||
1. 首先，请将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 上的所有开关均拨至 **ON** 状态，使 **功能选择开关** 处于默认状态。
|
||||
2. 为了方便应用程序的下载和测试，不要为开发板输入任何信号。
|
||||
3. 此时可以连接 `PoE 子板（B 板）`_ ，但不要向 B 板连接任何外部电源。
|
||||
4. 使用 USB 数据线将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 连接至 PC。
|
||||
5. 将 **电源开关** 从 GND 拨至 5V0 一侧。此时，**5V Power On LED** 应点亮。
|
||||
|
||||
|
||||
正式开始开发
|
||||
^^^^^^^^^^^^^
|
||||
|
||||
现在，请前往 :doc:`../../get-started/index` 中的 :ref:`get-started-step-by-step` 章节，查看如何设置开发环境，并尝试将示例项目烧录至您的开发板。
|
||||
|
||||
请务必在进入下一步前，确保您已完成上述所有步骤。
|
||||
|
||||
|
||||
配置与加载以太网示例
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
在完成开发环境设置和开发板测试后，您可以配置并烧录 :example:`ethernet/basic` 示例。本示例专门用于测试以太网功能，支持不同 PHY，包括 :ref:`get-started-esp32-ethernet-kit-v1.1` 开发板使用的 **IP101GRI** 。
|
||||
|
||||
|
||||
针对 ESP32-Ethernet-Kit V1.0 的主要修改：
|
||||
-----------------------------------------
|
||||
|
||||
* 原 GPIO0 反相后时钟提供给 PHY 方案改为由 PHY 侧外接无源晶振，提供时钟给 GPIO0。原用于控制有源晶振的 OSC_EN 的 IO2 释放，可用作其他用途。
|
||||
* 为防止 ESP32 侧 GPIO0 的上电状态受到 PHY 侧时钟输出的影响，PHY 侧 RESET_N 默认为低，关闭 PHY 侧时钟输出。而后可通过 GPIO5 控制 RESET_N 打开该时钟输出。
|
||||
* 移除 FT2232H 芯片的外部 SPI Flash U6。
|
||||
* 移除流控的测试排针 J4。
|
||||
* 移除 nTRST JTAG信号，相应的 GPIO4 可用作其他用途。
|
||||
* GPIO15 线上的上拉电阻 R68 移至 JTAG 的 MTDO 侧。
|
||||
* 为了加强 A 板和 B 板连接间的防呆设计（减少反向插入 B 板的机会），将原先 A 板上的 2 排 4 针排针改为 1 排 4 针排母和 1 排 4 针排针。相应的 4 针排针排和排母排则安装在 B 板上。
|
||||
|
||||
ESP32-Ethernet-Kit 的其他版本
|
||||
-------------------------------
|
||||
|
||||
* :doc:`get-started-ethernet-kit-v1.0`
|
||||
|
||||
|
||||
相关文档
|
||||
----------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图`_ (PDF)
|
||||
* `ESP32 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_cn.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-B 技术规格书 <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_cn.pdf>`_ (PDF)
|
||||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
有关本开发板的更多设计文档，请联系我们的商务部门 sales@espressif.com。
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
|
||||
get-started-ethernet-kit-v1.0.rst
|
||||
|
|
@ -1,17 +1,26 @@
|
|||
ESP32-Ethernet-Kit V1.1 入门指南
|
||||
ESP32-Ethernet-Kit V1.2 入门指南
|
||||
=================================
|
||||
|
||||
:link_to_translation:`en:[English]`
|
||||
|
||||
本指南将介绍 ESP32-Ethernet-Kit 开发板的配置以及相关功能的使用。
|
||||
|
||||
:ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.1>` 是一款以太网转 Wi-Fi 开发板，可为以太网设备赋予 Wi-Fi 连接功能。为了提供更灵活的电源选项，ESP32-Ethernet-Kit 同时也支持以太网供电 (PoE)。
|
||||
:ref:`ESP32-Ethernet-Kit <get-started-esp32-ethernet-kit-v1.2>` 是一款以太网转 Wi-Fi 开发板，可为以太网设备赋予 Wi-Fi 连接功能。为了提供更灵活的电源选项，ESP32-Ethernet-Kit 同时也支持以太网供电 (PoE)。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.2-overview:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.2-overview.png
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit V1.2
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.2 概图（点击放大）
|
||||
|
||||
准备工作
|
||||
--------
|
||||
|
||||
* :ref:`ESP32-Ethernet-Kit V1.1 开发板 <get-started-esp32-ethernet-kit-v1.1>`
|
||||
* :ref:`ESP32-Ethernet-Kit V1.2 开发板 <get-started-esp32-ethernet-kit-v1.2>`
|
||||
* USB 数据线（A 转 Micro-B）
|
||||
* PC（Windows、Linux 或 Mac OS）
|
||||
|
||||
|
|
@ -23,18 +32,19 @@ ESP32-Ethernet-Kit V1.1 入门指南
|
|||
|
||||
ESP32-Ethernet-Kit 是一款来自 `乐鑫 <https://espressif.com>`_ 的开发板。
|
||||
|
||||
它由 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 和 `PoE 子板（B 板）`_ 两部分组成。其中 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 集成蓝牙 / Wi-Fi 双模 ESP32-WROVER-B 模组和单端口 10/100 Mbps 快速以太网收发器 (PHY) IP101GRI。`PoE 子板（B 板）`_ 提供以太网供电功能。ESP32-Ethernet-Kit 的 A 板可在不连接 B 板的情况下独立工作。
|
||||
它由 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.2-layout>` 和 `PoE 子板（B 板）`_ 两部分组成。其中 :ref:`以太网母板（A板）<get-started-esp32-ethernet-kit-a-v1.2-layout>` 集成蓝牙/Wi-Fi 双模 ESP32-WROVER-E 模组和单端口 10/100 Mbps 快速以太网收发器 (PHY) IP101GRI。`PoE 子板（B 板）`_ 提供以太网供电功能。ESP32-Ethernet-Kit 的 A 板可在不连接 B 板的情况下独立工作。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1:
|
||||
.. _get-started-esp32-ethernet-kit-v1.2:
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.1.png
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-v1.2.jpg
|
||||
:align: center
|
||||
:alt: ESP32-Ethernet-Kit V1.1
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit V1.2
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit V1.1
|
||||
ESP32-Ethernet-Kit V1.2（点击放大）
|
||||
|
||||
为了实现程序下载和监控，A 板还集成了一款先进多协议 USB 桥接器（FTDI FT2232H 芯片）。FTDI FT2232H 芯片使得开发人员无需额外的 JTAG 适配器，通过 USB 桥接器使用 JTAG 接口便可对 ESP32 直接进行调试。
|
||||
为了实现程序下载和监控，A 板还集成了一款先进多协议 USB 桥接器（FT2232H 芯片）。FT2232H 芯片使得开发人员无需额外的 JTAG 适配器，通过 USB 桥接器使用 JTAG 接口便可对 ESP32 直接进行调试。
|
||||
|
||||
|
||||
功能概述
|
||||
|
|
@ -56,19 +66,19 @@ ESP32-Ethernet-Kit 开发板的主要组件和连接方式如下。
|
|||
|
||||
有关 ESP32-Ethernet-Kit 开发板的主要组件、接口及控制方式，请见下方的图片和表格。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.1-layout:
|
||||
.. _get-started-esp32-ethernet-kit-a-v1.2-layout:
|
||||
|
||||
|
||||
以太网母板（A 板）
|
||||
^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.1-layout.png
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-a-v1.2-layout.jpg
|
||||
:align: center
|
||||
:scale: 80%
|
||||
:alt: ESP32-Ethernet-Kit - Ethernet board (A) layout
|
||||
:alt: ESP32-Ethernet-Kit V1.2
|
||||
:figclass: align-center
|
||||
|
||||
ESP32-Ethernet-Kit - 以太网母板（A 板）布局（点击放大）（请更新图片）
|
||||
ESP32-Ethernet-Kit - 以太网母板（A 板）布局（点击放大）
|
||||
|
||||
下表将从图片右上角开始，以顺时针顺序介绍图中的主要组件。
|
||||
|
||||
|
|
@ -78,16 +88,16 @@ ESP32-Ethernet-Kit 开发板的主要组件和连接方式如下。
|
|||
|
||||
* - 主要组件
|
||||
- 基本介绍
|
||||
* - ESP32-WROVER-B 模组
|
||||
* - ESP32-WROVER-E 模组
|
||||
- 这款 ESP32 模组内置 64-Mbit PSRAM，可提供灵活的额外存储空间和数据处理能力。
|
||||
* - GPIO Header 2
|
||||
- 由 5 个未引出通孔组成，可连接至 ESP32 的部分 GPIO。具体介绍，请见 `GPIO Header 2`_。
|
||||
* - 功能选择开关
|
||||
- 一个 4 位拨码开关，可配置 ESP32 部分 GPIO 的功能。请注意，拨码开关旁边开发板的丝印层上的 GPIO 管脚标记的位置是不正确的。有关详细信息和正确的管脚分配，请见 `功能选择开关`_。
|
||||
- 一个 4 位拨码开关，可配置 ESP32 部分 GPIO 的功能。具体介绍，请见 `功能选择开关`_。
|
||||
* - Tx/Rx LEDs
|
||||
- 2 个 LED，可显示 UART 传输的状态。
|
||||
* - FT2232H
|
||||
- FT2232H 多协议 USB 转串口桥接器。开发人员可通过 USB 接口对 FT2232H 芯片进行控制和编程，与 ESP32 建立连接。FT2232H 芯片可在通道 A 提供 USB-to-JTAG 接口功能，并在通道 B 提供 USB-to-Serial 接口功能，便利开发人员的应用开发与调试。见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_。
|
||||
- FT2232H 多协议 USB 转串口桥接器。开发人员可通过 USB 接口对 FT2232H 芯片进行控制和编程，与 ESP32 建立连接。FT2232H 芯片可在通道 A 提供 USB-to-JTAG 接口功能，并在通道 B 提供 USB-to-Serial 接口功能，便利开发人员的应用开发与调试。见 `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_。
|
||||
* - USB 端口
|
||||
- USB 接口。可用作开发板的供电电源，或连接 PC 和开发板的通信接口。
|
||||
* - 电源开关
|
||||
|
|
@ -115,6 +125,9 @@ ESP32-Ethernet-Kit 开发板的主要组件和连接方式如下。
|
|||
* - GPIO Header 1
|
||||
- 由 6 个未引出通孔组成，可连接至 ESP32 的备用 GPIO。具体介绍，请见 `GPIO Header 1`_。
|
||||
|
||||
.. note::
|
||||
|
||||
如果采用了固件自动下载模式，则无需对 BOOT 或 EN 按键进行任何操作。
|
||||
|
||||
PoE 子板（B 板）
|
||||
^^^^^^^^^^^^^^^^^^^
|
||||
|
|
@ -143,11 +156,11 @@ PoE 子板（B 板）具有以下特性：
|
|||
* - 主要组件
|
||||
- 基本介绍
|
||||
* - A 板连接器
|
||||
- 4 个排针（左侧）和排母（右侧），用于将 PoE 子板（B 板）连接至 :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.1-layout>`。左侧的管脚接受来自 PoE 交换机的电源。右侧的管脚为 以太网母板（A 板）提供 5 V 电源。
|
||||
- 4 个排针（左侧）和排母（右侧），用于将 PoE 子板（B 板）连接至 :ref:`Ethernet board (A) <get-started-esp32-ethernet-kit-a-v1.2-layout>`。左侧的管脚接受来自 PoE 交换机的电源。右侧的管脚为 以太网母板（A 板）提供 5 V 电源。
|
||||
* - 外部电源终端
|
||||
- PoE 子板（B 板）可选电源 (26.6 ~ 54 V)。
|
||||
|
||||
.. _get-started-esp32-ethernet-kit-v1.1-setup-options:
|
||||
.. _get-started-esp32-ethernet-kit-v1.2-setup-options:
|
||||
|
||||
|
||||
设置选项
|
||||
|
|
@ -170,25 +183,21 @@ PoE 子板（B 板）具有以下特性：
|
|||
4 GPIO14
|
||||
========= ==========
|
||||
|
||||
.. note::
|
||||
|
||||
拨码开关旁边开发板的丝印层上的 GPIO 管脚标记的位置是不正确的。请以表格中的顺序为准。
|
||||
|
||||
|
||||
RMII 时钟源选择
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
RMII 工作模式下的以太网 MAC 和 PHY 需要一个公共的 50MHz 同步时钟（即 RMII 时钟），它既可以由外部提供，也可以由内部的 ESP32 APLL 产生。
|
||||
RMII 工作模式下的以太网 MAC 和 PHY 需要一个公共的 50MHz 同步时钟（即 RMII 时钟），它既可以由外部提供，也可以由内部的 ESP32 APLL 产生（不推荐）。
|
||||
|
||||
.. note::
|
||||
|
||||
有关 RMII 时钟源选择的更多信息，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_，第 2 页的位置 D2。
|
||||
有关 RMII 时钟源选择的更多信息，请参见 `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_，第 2 页的位置 D2。
|
||||
|
||||
|
||||
PHY 侧提供 RMII 时钟
|
||||
"""""""""""""""""""""""""""""
|
||||
|
||||
ESP32-Ethernet-Kit 默认配置为 IP101GRI 的 50M_CLKO 信号线提供 RMII 时钟，该时钟信号由 PHY 外侧连接的 25MHz 无源晶振经过倍频产生。详情请参见下图。
|
||||
ESP32-Ethernet-Kit 默认配置为 IP101GRI 的 50M_CLKO 信号线提供 RMII 时钟，该时钟信号由 PHY 外侧连接的 25 MHz 无源晶振经过倍频产生。详情请参见下图。
|
||||
|
||||
.. figure:: ../../../_static/esp32-ethernet-kit-rmii-clk-from-phy.png
|
||||
:align: center
|
||||
|
|
@ -214,7 +223,7 @@ ESP32 APLL 内部提供的 RMII 时钟
|
|||
|
||||
ESP32 APLL 内部提供的 RMII 时钟
|
||||
|
||||
要实现此选项，用户需要在板子上移除或添加一些阻容元器件。有关详细信息，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_，第 2 页，位置 D2。请注意，如果 APLL 已经用于其他用途（如 I2S 外设），那么只能使用外部 RMII 时钟。
|
||||
要实现此选项，用户需要在板子上移除或添加一些阻容元器件。有关详细信息，请参见 `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_，第 2 页，位置 D2。请注意，如果 APLL 已经用于其他用途（如 I2S 外设），那么只能使用外部 RMII 时钟。
|
||||
|
||||
|
||||
GPIO 分配
|
||||
|
|
@ -229,7 +238,7 @@ IP101GRI (PHY) 接口
|
|||
下表显示了 ESP32 (MAC) 与 IP101GRI (PHY) 的管脚对应关系。ESP32-Ethernet-Kit 的实现默认设置为简化媒体独立接口。
|
||||
|
||||
==== ================ ===============
|
||||
. ESP32 管脚 (MAC) IP101GRI (PHY)
|
||||
No. ESP32 管脚 (MAC) IP101GRI (PHY)
|
||||
==== ================ ===============
|
||||
*RMII 接口*
|
||||
---------------------------------------
|
||||
|
|
@ -253,7 +262,7 @@ IP101GRI (PHY) 接口
|
|||
|
||||
.. Note::
|
||||
|
||||
除了 REF_CLK 之外，ESP32 的 *RMII 接口* 下的所有管脚分配都是固定的，不能通过 IOMUX 或 GPIO 矩阵进行更改。
|
||||
ESP32 的 *RMII 接口* 下的所有管脚分配都是固定的，不能通过 IOMUX 或 GPIO 矩阵进行更改。REF_CLK 仅可选择 GPIO0、GPIO16 或 GPIO17，且不可通过 GPIO 矩阵进行更改。
|
||||
|
||||
|
||||
GPIO Header 1
|
||||
|
|
@ -262,7 +271,7 @@ GPIO Header 1
|
|||
本连接器包括 ESP32-Ethernet-Kit 开发板上部分不用做他用的 GPIO。
|
||||
|
||||
==== ================
|
||||
. ESP32 管脚
|
||||
No. ESP32 管脚
|
||||
==== ================
|
||||
1 GPIO32
|
||||
2 GPIO33
|
||||
|
|
@ -279,7 +288,7 @@ GPIO Header 2
|
|||
根据“说明"描述的不同情形，本连接器包含可用做他用的 GPIO。
|
||||
|
||||
==== ========== ====================
|
||||
. ESP32 管脚 说明
|
||||
No. ESP32 管脚 说明
|
||||
==== ========== ====================
|
||||
1 GPIO17 见下方说明 1
|
||||
2 GPIO16 见下方说明 1
|
||||
|
|
@ -295,7 +304,7 @@ GPIO Header 2
|
|||
|
||||
.. note::
|
||||
|
||||
1. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-B 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
1. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-E 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
|
||||
|
||||
2. 具体功能取决与 `功能选择开关`_ 的设置。
|
||||
|
|
@ -305,7 +314,7 @@ GPIO 管脚分配总结
|
|||
^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. csv-table::
|
||||
:header: ESP32-WROVER-B,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
:header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments
|
||||
|
||||
S_VP,,,,IO36,
|
||||
S_VN,,,,IO39,
|
||||
|
|
@ -318,8 +327,8 @@ GPIO 管脚分配总结
|
|||
IO27,CRS_DV,,,,
|
||||
IO14,,,TMS,IO14,
|
||||
IO12,,,TDI,IO12,
|
||||
IO13,,RTS,TCK,IO13,
|
||||
IO15,,CTS,TDO,IO15,
|
||||
IO13,,,TCK,IO13,
|
||||
IO15,,,TDO,IO15,
|
||||
IO2,,,,IO2,
|
||||
IO0,REF_CLK,,,,See note 1
|
||||
IO4,,,,IO4,
|
||||
|
|
@ -336,10 +345,10 @@ GPIO 管脚分配总结
|
|||
|
||||
.. note::
|
||||
|
||||
1. 为防止 ESP32 侧 GPIO0 的上电状态受 PHY 侧时钟输出的影响，PHY 侧 RESET_N 默认为低，以关闭 PHY 侧时钟输出。上电后，您可通过 GPIO5 控制 RESET_N 以打开该时钟输出。参见 `PHY 侧提供 RMII 时钟`_。对于无法通过 RESET_N 关闭时钟输出的 PHY，PHY 侧建议使用可在外部禁用/使能的有源晶振。与使用 RESET_N 类似，默认情况下晶振模块应禁用，并在上电后由 ESP32 开启。有关参考设计，请参见 `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_。
|
||||
1. 为防止 ESP32 侧 GPIO0 的上电状态受 PHY 侧时钟输出的影响，PHY 侧 RESET_N 默认为低，以关闭 PHY 侧时钟输出。上电后，您可通过 GPIO5 控制 RESET_N 以打开该时钟输出。参见 `PHY 侧提供 RMII 时钟`_。对于无法通过 RESET_N 关闭时钟输出的 PHY，PHY 侧建议使用可在外部禁用/使能的有源晶振。与使用 RESET_N 类似，默认情况下晶振模块应禁用，并在上电后由 ESP32 开启。有关参考设计，请参见 `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_。
|
||||
|
||||
|
||||
2. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-B 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
2. ESP32 芯片的 GPIO16 和 GPIO17 管脚没有引出至 ESP32-WROVER-E 模组的管脚，因此无法使用。如需使用 ESP32 的 GP1016 和 GPIO17 管脚，建议更换其他不含 PSRAM 的模组，比如 ESP32-WROOM-32D 或 ESP32-SOLO-1。
|
||||
|
||||
|
||||
应用程序开发
|
||||
|
|
@ -351,10 +360,10 @@ ESP32-Ethernet-Kit 上电前，请首先确认开发板完好无损。
|
|||
初始设置
|
||||
^^^^^^^^^^
|
||||
|
||||
1. 首先，请将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 上的所有开关均拨至 **ON** 状态，使 **功能选择开关** 处于默认状态。
|
||||
1. 首先，请将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.2-layout>` 上的所有开关均拨至 **ON** 状态，使 **功能选择开关** 处于默认状态。
|
||||
2. 为了方便应用程序的下载和测试，不要为开发板输入任何信号。
|
||||
3. 此时可以连接 `PoE 子板（B 板）`_ ，但不要向 B 板连接任何外部电源。
|
||||
4. 使用 USB 数据线将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.1-layout>` 连接至 PC。
|
||||
4. 使用 USB 数据线将 :ref:`以太网母板（A 板）<get-started-esp32-ethernet-kit-a-v1.2-layout>` 连接至 PC。
|
||||
5. 将 **电源开关** 从 GND 拨至 5V0 一侧。此时，**5V Power On LED** 应点亮。
|
||||
|
||||
|
||||
|
|
@ -369,41 +378,43 @@ ESP32-Ethernet-Kit 上电前，请首先确认开发板完好无损。
|
|||
配置与加载以太网示例
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
在完成开发环境设置和开发板测试后，您可以配置并烧录 :example:`ethernet/basic` 示例。本示例专门用于测试以太网功能，支持不同 PHY，包括 :ref:`get-started-esp32-ethernet-kit-v1.1` 开发板使用的 **IP101GRI** 。
|
||||
在完成开发环境设置和开发板测试后，您可以配置并烧录 :example:`ethernet/basic` 示例。本示例专门用于测试以太网功能，支持不同 PHY，包括 :ref:`get-started-esp32-ethernet-kit-v1.2` 开发板使用的 **IP101GRI** 。
|
||||
|
||||
|
||||
针对 ESP32-Ethernet-Kit V1.0 的主要修改：
|
||||
针对 ESP32-Ethernet-Kit V1.1 的主要修改：
|
||||
-----------------------------------------
|
||||
|
||||
* 原 GPIO0 反相后时钟提供给 PHY 方案改为由 PHY 侧外接无源晶振，提供时钟给 GPIO0。原用于控制有源晶振的 OSC_EN 的 IO2 释放，可用作其他用途。
|
||||
* 为防止 ESP32 侧 GPIO0 的上电状态受到 PHY 侧时钟输出的影响，PHY 侧 RESET_N 默认为低，关闭 PHY 侧时钟输出。而后可通过 GPIO5 控制 RESET_N 打开该时钟输出。
|
||||
* 移除 FT2232H 芯片的外部 SPI Flash U6。
|
||||
* 移除流控的测试排针 J4。
|
||||
* 移除 nTRST JTAG信号，相应的 GPIO4 可用作其他用途。
|
||||
* GPIO15 线上的上拉电阻 R68 移至 JTAG 的 MTDO 侧。
|
||||
* 为了加强 A 板和 B 板连接间的防呆设计（减少反向插入 B 板的机会），将原先 A 板上的 2 排 4 针排针改为 1 排 4 针排母和 1 排 4 针排针。相应的 4 针排针排和排母排则安装在 B 板上。
|
||||
* 更正拨码开关周围 GPIO 编号丝印。
|
||||
* C1、C2、C42 和 C43 更新为 20 pF。详细信息见 `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_。
|
||||
* 模组 ESP32-WROVER-B 替换为 ESP32-WROVER-E。
|
||||
|
||||
ESP32-Ethernet-Kit 的其他版本
|
||||
-------------------------------
|
||||
|
||||
* :doc:`get-started-ethernet-kit-v1.0`
|
||||
* :doc:`get-started-ethernet-kit-v1.1`
|
||||
|
||||
|
||||
相关文档
|
||||
----------
|
||||
|
||||
* `ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图`_ (PDF)
|
||||
* `ESP32-Ethernet-Kit PoE 子板（B 板）原理图`_ (PDF)
|
||||
* `ESP32 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_cn.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-B 技术规格书 <https://espressif.com/sites/default/files/documentation/esp32-wrover-b_datasheet_cn.pdf>`_ (PDF)
|
||||
* `ESP32-WROVER-E 技术规格书 <https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_cn.pdf>`_ (PDF)
|
||||
* :doc:`../../api-guides/jtag-debugging/index`
|
||||
* :doc:`../../hw-reference/index`
|
||||
|
||||
有关本开发板的更多设计文档，请联系我们的商务部门 sales@espressif.com。
|
||||
|
||||
.. _ESP32-Ethernet-Kit V1.1 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.1_20190711.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 PoE 子板（B 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit PoE 子板（B 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_B_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.0 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-ETHERNET-KIT_A_V1.0_20190517.pdf
|
||||
.. _ESP32-Ethernet-Kit V1.2 以太网母板（A 板）原理图: https://dl.espressif.com/dl/schematics/SCH_ESP32-Ethernet-Kit_A_V1.2_20200528.pdf
|
||||
|
||||
.. toctree::
|
||||
:hidden:
|
||||
|
||||
get-started-ethernet-kit-v1.0.rst
|
||||
get-started-ethernet-kit-v1.0.rst
|
||||
get-started-ethernet-kit-v1.1.rst
|
||||
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue