kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/efuse_using_rom_set_timing_func' into 'master'
(S2) efuse: Using a ROM function for set_timing Closes IDF-990 See merge request espressif/esp-idf!7594pull/4797/head
commit
a6066c801d
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@ -63,48 +63,8 @@ const esp_efuse_range_addr_t range_write_addr_blocks[] = {
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// Update Efuse timing configuration
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static esp_err_t esp_efuse_set_timing(void)
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{
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uint32_t clock = esp_clk_apb_freq();
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// ets_efuse_set_timing(clock);
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uint32_t clk_div, power_on;
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//uint32_t power_off; // Support for 7.2.3 chip
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uint32_t tsup_a = 1, thp_a = 1, tpgm, tpgm_inact;
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uint32_t tsur_a = 1, thr_a = 1, trd;
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if (clock == 20000000 || clock == 5000000 || clock == 10000000) {
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clk_div = 0x28;
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power_on = 0x2880;
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//power_off = 0x40;
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tpgm = 0xc8;
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tpgm_inact = 1;
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trd = 1;
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} else if (clock == 40000000) {
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clk_div = 0x50;
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power_on = 0x5100;
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//power_off = 0x80;
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tpgm = 0x190;
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tpgm_inact = 2;
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trd = 2;
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} else if (clock == 80000000) {
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clk_div = 0xa0;
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power_on = 0xa200;
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//power_off = 0x100;
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tpgm = 0x320;
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tpgm_inact = 3;
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trd = 3;
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} else {
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ESP_LOGE(TAG, "Efuse does not support this %d Hz APB clock", clock);
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return ESP_ERR_NOT_SUPPORTED;
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}
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REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
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//REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
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return ESP_OK;
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uint32_t clock_hz = esp_clk_apb_freq();
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return ets_efuse_set_timing(clock_hz) ? ESP_FAIL : ESP_OK;
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}
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#endif // ifndef CONFIG_EFUSE_VIRTUAL
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