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esp32c3: format and clean up interrupt and os port code

pull/6416/head
morris 2020-12-29 12:31:54 +08:00
rodzic 72e4655d4e
commit 9e7d2c0065
12 zmienionych plików z 111 dodań i 110 usunięć
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62
components/esp_common/src/int_wdt.c
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@ -1,9 +1,9 @@
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
// You may obtain a copy of the License at // You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
@ -12,14 +12,14 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#include "sdkconfig.h"
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
#include <stdbool.h> #include <stdbool.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include <esp_types.h> #include "esp_types.h"
#include "esp_err.h" #include "esp_err.h"
#include "esp_intr_alloc.h" #include "esp_intr_alloc.h"
#include "esp_attr.h" #include "esp_attr.h"
@ -29,6 +29,7 @@
#include "driver/periph_ctrl.h" #include "driver/periph_ctrl.h"
#include "esp_int_wdt.h" #include "esp_int_wdt.h"
#include "esp_private/system_internal.h" #include "esp_private/system_internal.h"
#include "hal/cpu_hal.h"
#include "hal/timer_types.h" #include "hal/timer_types.h"
#include "hal/wdt_hal.h" #include "hal/wdt_hal.h"
#include "hal/interrupt_controller_hal.h" #include "hal/interrupt_controller_hal.h"
@ -45,7 +46,7 @@ static wdt_hal_context_t iwdt_context;
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
/* /*
* This parameter is indicates the response time of Interrupt watchdog to * This parameter is used to indicate the response time of Interrupt watchdog to
* identify the live lock. * identify the live lock.
*/ */
#define IWDT_LIVELOCK_TIMEOUT_MS (20) #define IWDT_LIVELOCK_TIMEOUT_MS (20)
@ -58,8 +59,9 @@ extern uint32_t _l4_intr_livelock_counter, _l4_intr_livelock_max;
//Not static; the ISR assembly checks this. //Not static; the ISR assembly checks this.
bool int_wdt_app_cpu_ticked = false; bool int_wdt_app_cpu_ticked = false;
static void IRAM_ATTR tick_hook(void) { static void IRAM_ATTR tick_hook(void)
if (xPortGetCoreID()!=0) { {
if (cpu_hal_get_core_id() != 0) {
int_wdt_app_cpu_ticked = true; int_wdt_app_cpu_ticked = true;
} else { } else {
//Only feed wdt if app cpu also ticked. //Only feed wdt if app cpu also ticked.
@ -70,11 +72,11 @@ static void IRAM_ATTR tick_hook(void) {
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
_l4_intr_livelock_counter = 0; _l4_intr_livelock_counter = 0;
wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, wdt_hal_config_stage(&iwdt_context, WDT_STAGE0,
CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US/(_l4_intr_livelock_max+1), WDT_STAGE_ACTION_INT); //Set timeout before interrupt CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_l4_intr_livelock_max + 1), WDT_STAGE_ACTION_INT); //Set timeout before interrupt
#else #else
wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
#endif #endif
wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
wdt_hal_feed(&iwdt_context); wdt_hal_feed(&iwdt_context);
wdt_hal_write_protect_enable(&iwdt_context); wdt_hal_write_protect_enable(&iwdt_context);
int_wdt_app_cpu_ticked = false; int_wdt_app_cpu_ticked = false;
@ -82,32 +84,31 @@ static void IRAM_ATTR tick_hook(void) {
} }
} }
#else #else
static void IRAM_ATTR tick_hook(void) { static void IRAM_ATTR tick_hook(void)
{
#if !CONFIG_FREERTOS_UNICORE #if !CONFIG_FREERTOS_UNICORE
if (xPortGetCoreID()!=0) { if (cpu_hal_get_core_id() != 0) {
return; return;
} }
#endif #endif
//Todo: Check if there's a way to avoid reconfiguring the stages on each feed. //Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
wdt_hal_write_protect_disable(&iwdt_context); wdt_hal_write_protect_disable(&iwdt_context);
//Reconfigure stage timeouts //Reconfigure stage timeouts
wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
wdt_hal_feed(&iwdt_context); wdt_hal_feed(&iwdt_context);
wdt_hal_write_protect_enable(&iwdt_context); wdt_hal_write_protect_enable(&iwdt_context);
} }
#endif #endif
void esp_int_wdt_init(void) { void esp_int_wdt_init(void)
{
periph_module_enable(PERIPH_TIMG1_MODULE); periph_module_enable(PERIPH_TIMG1_MODULE);
//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
//it to their actual value. //it to their actual value.
wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true); wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
wdt_hal_write_protect_disable(&iwdt_context); wdt_hal_write_protect_disable(&iwdt_context);
//The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
//it to their actual value.
//1st stage timeout: interrupt //1st stage timeout: interrupt
wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
//2nd stage timeout: reset system //2nd stage timeout: reset system
@ -119,17 +120,14 @@ void esp_int_wdt_init(void) {
void esp_int_wdt_cpu_init(void) void esp_int_wdt_cpu_init(void)
{ {
assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS<<1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!"); assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID()); esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
ESP_INTR_DISABLE(WDT_INT_NUM); ESP_INTR_DISABLE(WDT_INT_NUM);
intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM); intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
/* Set the type and priority to cache error interrupts, if supported. */ /* Set the type and priority to watch dog interrupts */
#if SOC_INTERRUPT_TYPE_CAN_SET #if SOC_CPU_HAS_FLEXIBLE_INTC
interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL); interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
#endif
#if SOC_INTERRUPT_LEVEL_CAN_SET
interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM); interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
#endif #endif
@ -140,15 +138,15 @@ void esp_int_wdt_cpu_init(void)
*/ */
_l4_intr_livelock_counter = 0; _l4_intr_livelock_counter = 0;
if (soc_has_cache_lock_bug()) { if (soc_has_cache_lock_bug()) {
assert((portTICK_PERIOD_MS<<1) <= IWDT_LIVELOCK_TIMEOUT_MS); assert((portTICK_PERIOD_MS << 1) <= IWDT_LIVELOCK_TIMEOUT_MS);
assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS*3)); assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS * 3));
_l4_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS/IWDT_LIVELOCK_TIMEOUT_MS - 1; _l4_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1;
} }
#endif #endif
//We do not register a handler for the interrupt because it is interrupt level 4 which // We do not register a handler for the watchdog interrupt because:
//is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for // 1. Interrupt level 4 on Xtensa architecture is not servicable from C
//this interrupt. // 2. Instead, we set the entry of watchdog interrupt to the panic handler, see riscv/vector.S and xtensa_vectors.S
ESP_INTR_ENABLE(WDT_INT_NUM); ESP_INTR_ENABLE(WDT_INT_NUM);
} }

18
components/esp_system/include/esp_intr_alloc.h
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@ -1,4 +1,4 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
@ -12,8 +12,7 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#ifndef __ESP_INTR_ALLOC_H__ #pragma once
#define __ESP_INTR_ALLOC_H__
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
@ -93,7 +92,7 @@ typedef void (*intr_handler_t)(void *arg);
typedef struct intr_handle_data_t intr_handle_data_t; typedef struct intr_handle_data_t intr_handle_data_t;
/** Handle to an interrupt handler */ /** Handle to an interrupt handler */
typedef intr_handle_data_t* intr_handle_t ; typedef intr_handle_data_t *intr_handle_t ;
/** /**
* @brief Mark an interrupt as a shared interrupt * @brief Mark an interrupt as a shared interrupt
@ -306,11 +305,18 @@ void esp_intr_enable_source(int inum);
*/ */
void esp_intr_disable_source(int inum); void esp_intr_disable_source(int inum);
/**
* @brief Get the lowest interrupt level from the flags
* @param flags The same flags that pass to `esp_intr_alloc_intrstatus` API
*/
static inline int esp_intr_flags_to_level(int flags)
{
return __builtin_ffs((flags & ESP_INTR_FLAG_LEVELMASK) >> 1) + 1;
}
/**@}*/ /**@}*/
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif

21
components/esp_system/intr_alloc.c
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@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
// You may obtain a copy of the License at // You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
@ -12,7 +12,6 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#include "sdkconfig.h"
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
@ -21,6 +20,7 @@
#include <esp_types.h> #include <esp_types.h>
#include <limits.h> #include <limits.h>
#include <assert.h> #include <assert.h>
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "esp_err.h" #include "esp_err.h"
@ -48,7 +48,8 @@ Define this to debug the choices made when allocating the interrupt. This leads
output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
being triggered, that is why it is separate from the normal LOG* scheme. being triggered, that is why it is separate from the normal LOG* scheme.
*/ */
//#define DEBUG_INT_ALLOC_DECISIONS // #define DEBUG_INT_ALLOC_DECISIONS
#ifdef DEBUG_INT_ALLOC_DECISIONS #ifdef DEBUG_INT_ALLOC_DECISIONS
# define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__) # define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
#else #else
@ -246,7 +247,8 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
} }
//check if edge/level type matches what we want //check if edge/level type matches what we want
if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) || if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
(((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) { ALCHLOG("....Unusable: incompatible trigger type"); (((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {
ALCHLOG("....Unusable: incompatible trigger type");
return false; return false;
} }
#endif #endif
@ -587,14 +589,13 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC #ifdef SOC_CPU_HAS_FLEXIBLE_INTC
//Extract the level from the interrupt passed flags //Extract the level from the interrupt passed flags
int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1; int level = esp_intr_flags_to_level(flags);
interrupt_controller_hal_set_int_level(intr, level);
interrupt_controller_hal_set_int_level(intr,level);
if (flags & ESP_INTR_FLAG_EDGE) { if (flags & ESP_INTR_FLAG_EDGE) {
interrupt_controller_hal_set_int_type(intr,INTTP_EDGE); interrupt_controller_hal_set_int_type(intr, INTTP_EDGE);
} else { } else {
interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL); interrupt_controller_hal_set_int_type(intr, INTTP_LEVEL);
} }
#endif #endif

7
components/freertos/port/riscv/port.c
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@ -124,7 +124,6 @@ void vPortEnterCritical(void)
uxCriticalNesting++; uxCriticalNesting++;
if (uxCriticalNesting == 1) { if (uxCriticalNesting == 1) {
//portDISABLE_INTERRUPTS();
uxSavedInterruptState = state; uxSavedInterruptState = state;
} }
} }
@ -135,7 +134,6 @@ void vPortExitCritical(void)
uxCriticalNesting--; uxCriticalNesting--;
if (uxCriticalNesting == 0) { if (uxCriticalNesting == 0) {
portEXIT_CRITICAL_NESTED(uxSavedInterruptState); portEXIT_CRITICAL_NESTED(uxSavedInterruptState);
//portENABLE_INTERRUPTS();
} }
} }
} }
@ -169,8 +167,7 @@ void prvTaskExitError(void)
defined, then stop here so application writers can catch the error. */ defined, then stop here so application writers can catch the error. */
configASSERT(uxCriticalNesting == ~0UL); configASSERT(uxCriticalNesting == ~0UL);
portDISABLE_INTERRUPTS(); portDISABLE_INTERRUPTS();
for (;;) abort();
;
} }
/* Clear current interrupt mask and set given mask */ /* Clear current interrupt mask and set given mask */
@ -277,7 +274,7 @@ void vPortYield(void)
for an instant yield, and if that happens then the WFI would be for an instant yield, and if that happens then the WFI would be
waiting for the next interrupt to occur...) waiting for the next interrupt to occur...)
*/ */
while(uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) { } while (uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) {}
} }
} }

6
components/hal/esp32/include/hal/interrupt_controller_ll.h
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@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
* @param handler handler invoked when an interrupt occurs * @param handler handler invoked when an interrupt occurs
* @param arg optional argument to pass to the handler * @param arg optional argument to pass to the handler
*/ */
static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
{ {
xt_set_interrupt_handler(intr, (xt_handler)handler, arg); xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
} }
@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
* *
* @return argument used by handler of passed interrupt number * @return argument used by handler of passed interrupt number
*/ */
static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
{ {
return xt_get_interrupt_handler_arg(intr); return xt_get_interrupt_handler_arg(intr);
} }
@ -105,7 +105,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
* *
* @param intr interrupt number ranged from 0 to 31 * @param intr interrupt number ranged from 0 to 31
*/ */
static inline void intr_cntrl_ll_edge_int_acknowledge (int intr) static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
{ {
xthal_set_intclear(1 << intr); xthal_set_intclear(1 << intr);
} }

6
components/hal/esp32c3/include/hal/interrupt_controller_ll.h
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@ -68,7 +68,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
* @param handler handler invoked when an interrupt occurs * @param handler handler invoked when an interrupt occurs
* @param arg optional argument to pass to the handler * @param arg optional argument to pass to the handler
*/ */
static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
{ {
intr_handler_set(intr, (void *)handler, arg); intr_handler_set(intr, (void *)handler, arg);
} }
@ -80,7 +80,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
* *
* @return argument used by handler of passed interrupt number * @return argument used by handler of passed interrupt number
*/ */
static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
{ {
return intr_handler_get_arg(intr); return intr_handler_get_arg(intr);
} }
@ -120,7 +120,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
* *
* @param intr interrupt number ranged from 0 to 31 * @param intr interrupt number ranged from 0 to 31
*/ */
static inline void intr_cntrl_ll_edge_int_acknowledge (int intr) static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
{ {
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr); REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
} }

4
components/hal/esp32s2/include/hal/interrupt_controller_ll.h
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@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
* @param handler handler invoked when an interrupt occurs * @param handler handler invoked when an interrupt occurs
* @param arg optional argument to pass to the handler * @param arg optional argument to pass to the handler
*/ */
static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
{ {
xt_set_interrupt_handler(intr, (xt_handler)handler, arg); xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
} }
@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
* *
* @return argument used by handler of passed interrupt number * @return argument used by handler of passed interrupt number
*/ */
static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
{ {
return xt_get_interrupt_handler_arg(intr); return xt_get_interrupt_handler_arg(intr);
} }

4
components/hal/esp32s3/include/hal/interrupt_controller_ll.h
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@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
* @param handler handler invoked when an interrupt occurs * @param handler handler invoked when an interrupt occurs
* @param arg optional argument to pass to the handler * @param arg optional argument to pass to the handler
*/ */
static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg) static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
{ {
xt_set_interrupt_handler(intr, (xt_handler)handler, arg); xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
} }
@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
* *
* @return argument used by handler of passed interrupt number * @return argument used by handler of passed interrupt number
*/ */
static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr) static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
{ {
return xt_get_interrupt_handler_arg(intr); return xt_get_interrupt_handler_arg(intr);
} }

1
components/soc/esp32c3/include/soc/soc_caps.h
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@ -43,7 +43,6 @@
#include "rmt_caps.h" #include "rmt_caps.h"
#include "spi_caps.h" #include "spi_caps.h"
#include "uart_caps.h" #include "uart_caps.h"
#include "int_caps.h"
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */ #define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */