kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/rmt_struct_bad_addressing' into 'master'
removed possible uint16 access to 32bit register, noted fifo use not recommended See merge request idf/esp-idf!2821pull/2237/head
commit
9d2f7c60d9
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@ -19,7 +19,9 @@ extern "C" {
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#endif
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typedef volatile struct {
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.*/
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
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Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
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and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
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struct{
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union {
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struct {
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@ -39,7 +41,7 @@ typedef volatile struct {
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uint32_t rx_en: 1; /*Set this bit to enable receiving data for channel0-7.*/
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uint32_t mem_wr_rst: 1; /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
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uint32_t mem_rd_rst: 1; /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
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uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
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uint32_t apb_mem_rst: 1; /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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uint32_t mem_owner: 1; /*This is the mark of channel0-7's ram usage right.1'b1:receiver uses the ram 0:transmitter uses the ram*/
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uint32_t tx_conti_mode: 1; /*Set this bit to continue sending from the first data to the last data in channel0-7 again and again.*/
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uint32_t rx_filter_en: 1; /*This is the receive filter enable bit for channel0-7.*/
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@ -54,7 +56,7 @@ typedef volatile struct {
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} conf1;
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} conf_ch[8];
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uint32_t status_ch[8]; /*The status for channel0-7*/
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uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access*/
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uint32_t apb_mem_addr_ch[8]; /*The ram relative address in channel0-7 by apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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union {
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struct {
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uint32_t ch0_tx_end: 1; /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
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@ -219,7 +221,7 @@ typedef volatile struct {
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} tx_lim_ch[8];
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union {
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struct {
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uint32_t fifo_mask: 1; /*Set this bit to disable apb fifo access*/
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uint32_t fifo_mask: 1; /*Set this bit to enable RMTMEM and disable apb fifo access (using fifo is discouraged, please see the note above at data_ch[] item)*/
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uint32_t mem_tx_wrap_en: 1; /*when data need to be send is more than channel's mem can store then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
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uint32_t reserved2: 30;
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};
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@ -243,22 +245,11 @@ typedef struct {
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};
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} rmt_item32_t;
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typedef struct {
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union {
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struct {
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uint16_t duration :15;
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uint16_t level :1;
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};
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uint16_t val;
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};
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} rmt_item16_t;
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//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
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typedef volatile struct {
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struct {
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union {
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rmt_item32_t data32[64];
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rmt_item16_t data16[128];
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};
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} chan[8];
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} rmt_mem_t;
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