kopia lustrzana https://github.com/espressif/esp-idf
esp_system: Do not rely on bootloader cache settings, do cache settings unconditionally at startup app
It makes multicore app runnable by unicore bootloader Closes https://github.com/espressif/esp-idf/issues/10714pull/11112/head
rodzic
37ac0ad851
commit
975c138fad
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@ -96,4 +96,12 @@ void bootloader_print_banner(void)
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#ifndef CONFIG_APP_REPRODUCIBLE_BUILD
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ESP_EARLY_LOGI(TAG, "compile time " __DATE__ " " __TIME__);
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#endif
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#if CONFIG_FREERTOS_UNICORE
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#if (SOC_CPU_CORES_NUM > 1)
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ESP_EARLY_LOGW(TAG, "Unicore bootloader");
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#endif
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#else
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ESP_EARLY_LOGI(TAG, "Multicore bootloader");
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#endif
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}
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@ -42,6 +42,7 @@
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#include "soc/assist_debug_reg.h"
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#include "soc/system_reg.h"
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#include "esp32s3/rom/opi_flash.h"
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#include "hal/cache_hal.h"
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#elif CONFIG_IDF_TARGET_ESP32C3
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#include "esp32c3/rtc.h"
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#include "esp32c3/rom/cache.h"
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@ -84,6 +85,7 @@
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#include "esp_private/sleep_gpio.h"
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#include "hal/wdt_hal.h"
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#include "soc/rtc.h"
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#include "hal/cache_ll.h"
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#include "hal/efuse_ll.h"
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#include "soc/periph_defs.h"
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#include "esp_cpu.h"
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@ -256,6 +258,37 @@ static void start_other_core(void)
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esp_rom_delay_us(100);
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}
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}
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// This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
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// It does some cache settings for other CPUs.
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void IRAM_ATTR do_multicore_settings(void)
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{
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// We intentionally do not check the cache settings before changing them,
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// because it helps to get the application to run on older bootloaders.
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#ifdef CONFIG_IDF_TARGET_ESP32
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if (!efuse_ll_get_disable_app_cpu()) {
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Cache_Read_Disable(1);
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Cache_Flush(1);
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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// We do not enable cache for CPU1 now because it will be done later in start_other_core().
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}
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#endif
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cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 1. disable the cache before changing its settings.
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cache_hal_disable(CACHE_TYPE_ALL);
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#endif
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for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) {
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// 2. change cache settings. All cores must have the same settings.
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cache_ll_l1_enable_bus(core, cache_bus_mask_core0);
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}
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 3. enable the cache after changing its settings.
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cache_hal_enable(CACHE_TYPE_ALL);
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#endif
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}
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/*
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@ -312,6 +345,16 @@ void IRAM_ATTR call_start_cpu0(void)
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}
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#endif
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#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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ESP_EARLY_LOGI(TAG, "Unicore app");
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#else
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ESP_EARLY_LOGI(TAG, "Multicore app");
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// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
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do_multicore_settings();
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#endif
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#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
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// When the APP is loaded into ram for execution, some hardware initialization behaviors
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// in the bootloader are still necessary
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#if CONFIG_APP_BUILD_TYPE_RAM
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@ -99,6 +99,38 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
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}
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = 0;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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if (cache_id == 0) {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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} else {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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}
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return mask;
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}
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/**
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* Disable the Cache Buses
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*
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -100,6 +100,37 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = 0;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
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if (cache_id == 0) {
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mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0;
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} else {
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mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0;
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}
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uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG);
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if (cache_id == 1) {
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mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0;
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} else {
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mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0;
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}
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return mask;
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}
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/**
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* Disable the Cache Buses
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*
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