kopia lustrzana https://github.com/espressif/esp-idf
lcd: split gpio check for de and hv mode
rodzic
09f5c1d32e
commit
8ea1c12d80
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
|
@ -64,7 +64,7 @@ typedef struct {
|
||||||
unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
|
unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
|
||||||
unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
|
unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
|
||||||
unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
|
unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
|
||||||
unsigned int pclk_active_neg: 1; /*!< The display will write data lines when there's a falling edge on PCLK */
|
unsigned int pclk_active_neg: 1; /*!< Whether the display data is clocked out at the falling edge of PCLK */
|
||||||
unsigned int pclk_idle_high: 1; /*!< The PCLK stays at high level in IDLE phase */
|
unsigned int pclk_idle_high: 1; /*!< The PCLK stays at high level in IDLE phase */
|
||||||
} flags;
|
} flags;
|
||||||
} esp_lcd_rgb_timing_t;
|
} esp_lcd_rgb_timing_t;
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
|
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
*/
|
*/
|
||||||
|
@ -379,8 +379,11 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_
|
||||||
{
|
{
|
||||||
int panel_id = panel->panel_id;
|
int panel_id = panel->panel_id;
|
||||||
// check validation of GPIO number
|
// check validation of GPIO number
|
||||||
bool valid_gpio = (panel_config->hsync_gpio_num >= 0) && (panel_config->vsync_gpio_num >= 0) &&
|
bool valid_gpio = (panel_config->pclk_gpio_num >= 0);
|
||||||
(panel_config->pclk_gpio_num >= 0);
|
if (panel_config->de_gpio_num < 0) {
|
||||||
|
// Hsync and Vsync are required in HV mode
|
||||||
|
valid_gpio = valid_gpio && (panel_config->hsync_gpio_num >= 0) && (panel_config->vsync_gpio_num >= 0);
|
||||||
|
}
|
||||||
for (size_t i = 0; i < panel_config->data_width; i++) {
|
for (size_t i = 0; i < panel_config->data_width; i++) {
|
||||||
valid_gpio = valid_gpio && (panel_config->data_gpio_nums[i] >= 0);
|
valid_gpio = valid_gpio && (panel_config->data_gpio_nums[i] >= 0);
|
||||||
}
|
}
|
||||||
|
@ -394,14 +397,18 @@ static esp_err_t lcd_rgb_panel_configure_gpio(esp_rgb_panel_t *panel, const esp_
|
||||||
esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i],
|
esp_rom_gpio_connect_out_signal(panel_config->data_gpio_nums[i],
|
||||||
lcd_periph_signals.panels[panel_id].data_sigs[i], false, false);
|
lcd_periph_signals.panels[panel_id].data_sigs[i], false, false);
|
||||||
}
|
}
|
||||||
|
if (panel_config->hsync_gpio_num >= 0) {
|
||||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->hsync_gpio_num], PIN_FUNC_GPIO);
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->hsync_gpio_num], PIN_FUNC_GPIO);
|
||||||
gpio_set_direction(panel_config->hsync_gpio_num, GPIO_MODE_OUTPUT);
|
gpio_set_direction(panel_config->hsync_gpio_num, GPIO_MODE_OUTPUT);
|
||||||
esp_rom_gpio_connect_out_signal(panel_config->hsync_gpio_num,
|
esp_rom_gpio_connect_out_signal(panel_config->hsync_gpio_num,
|
||||||
lcd_periph_signals.panels[panel_id].hsync_sig, false, false);
|
lcd_periph_signals.panels[panel_id].hsync_sig, false, false);
|
||||||
|
}
|
||||||
|
if (panel_config->vsync_gpio_num >= 0) {
|
||||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->vsync_gpio_num], PIN_FUNC_GPIO);
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->vsync_gpio_num], PIN_FUNC_GPIO);
|
||||||
gpio_set_direction(panel_config->vsync_gpio_num, GPIO_MODE_OUTPUT);
|
gpio_set_direction(panel_config->vsync_gpio_num, GPIO_MODE_OUTPUT);
|
||||||
esp_rom_gpio_connect_out_signal(panel_config->vsync_gpio_num,
|
esp_rom_gpio_connect_out_signal(panel_config->vsync_gpio_num,
|
||||||
lcd_periph_signals.panels[panel_id].vsync_sig, false, false);
|
lcd_periph_signals.panels[panel_id].vsync_sig, false, false);
|
||||||
|
}
|
||||||
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->pclk_gpio_num], PIN_FUNC_GPIO);
|
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[panel_config->pclk_gpio_num], PIN_FUNC_GPIO);
|
||||||
gpio_set_direction(panel_config->pclk_gpio_num, GPIO_MODE_OUTPUT);
|
gpio_set_direction(panel_config->pclk_gpio_num, GPIO_MODE_OUTPUT);
|
||||||
esp_rom_gpio_connect_out_signal(panel_config->pclk_gpio_num,
|
esp_rom_gpio_connect_out_signal(panel_config->pclk_gpio_num,
|
||||||
|
|
Ładowanie…
Reference in New Issue