diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index fa151f0e73..951145e85f 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -338,7 +338,7 @@ static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint */ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->channel[channel].in.wight.rx_weight = weight; + dev->channel[channel].in.weight.rx_weight = weight; } /** @@ -597,7 +597,7 @@ static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint */ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->channel[channel].out.wight.tx_weight = weight; + dev->channel[channel].out.weight.tx_weight = weight; } /** diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/include/soc/gdma_reg.h index 62b3402947..53e76bdc6f 100644 --- a/components/soc/esp32s3/include/soc/gdma_reg.h +++ b/components/soc/esp32s3/include/soc/gdma_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,8 +14,7 @@ extern "C" { #define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0) /* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA..*/ #define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH0_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH0_V 0x1 @@ -28,8 +27,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH0_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH0_S 3 /* GDMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH0_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH0_V 0x1 @@ -62,8 +61,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH0_V 0x1 #define GDMA_IN_CHECK_OWNER_CH0_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 0 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 0 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH0 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH0_M ((GDMA_DMA_INFIFO_FULL_THRS_CH0_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH0_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH0_V 0xFFF @@ -99,15 +98,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0..*/ #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 0..*/ #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(4)) @@ -115,23 +114,23 @@ el 0..*/ #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 0..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 0..*/ #define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt b +/*description: The raw interrupt bit turns to high level when the last data pointed by +oneinlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt b it turns to high level when the last data pointed by one inlink descriptor has b een received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) @@ -139,8 +138,8 @@ een received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 /* GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 0..*/ #define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH0_INT_RAW_V 0x1 @@ -459,15 +458,15 @@ nk descriptor has been received for Rx channel 0..*/ #define GDMA_INLINK_STOP_CH0_V 0x1 #define GDMA_INLINK_STOP_CH0_S 21 /* GDMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH0_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH0_V 0x1 #define GDMA_INLINK_AUTO_RET_CH0_S 20 /* GDMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH0 0x000FFFFF #define GDMA_INLINK_ADDR_CH0_M ((GDMA_INLINK_ADDR_CH0_V)<<(GDMA_INLINK_ADDR_CH0_S)) #define GDMA_INLINK_ADDR_CH0_V 0xFFFFF @@ -495,8 +494,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x28) /* GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -504,8 +503,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x2C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -535,7 +534,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH0_S 0 -#define GDMA_IN_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) +#define GDMA_IN_WEIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) /* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 0. .*/ #define GDMA_RX_WEIGHT_CH0 0x0000000F @@ -545,8 +544,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x44) /* GDMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 0. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 0. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH0 0x0000000F #define GDMA_RX_PRI_CH0_M ((GDMA_RX_PRI_CH0_V)<<(GDMA_RX_PRI_CH0_S)) #define GDMA_RX_PRI_CH0_V 0xF @@ -563,15 +562,15 @@ y..*/ #define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x60) /* GDMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH0_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH0_S 5 /* GDMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH0_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH0_V 0x1 @@ -584,8 +583,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH0_V 0x1 #define GDMA_OUT_EOF_MODE_CH0_S 3 /* GDMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH0_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH0_V 0x1 @@ -648,31 +647,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 0..*/ #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 0..*/ #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 /* GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 0. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 0. .*/ #define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH0_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH0_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH0_INT_RAW_S 1 /* GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 0..*/ #define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH0_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH0_INT_RAW_V 0x1 @@ -924,8 +923,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 0..*/ #define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) /* GDMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH0 (BIT(23)) #define GDMA_OUTLINK_PARK_CH0_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH0_V 0x1 @@ -949,8 +948,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH0_V 0x1 #define GDMA_OUTLINK_STOP_CH0_S 20 /* GDMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH0 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH0_M ((GDMA_OUTLINK_ADDR_CH0_V)<<(GDMA_OUTLINK_ADDR_CH0_S)) #define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFF @@ -978,8 +977,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) /* GDMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH0_M ((GDMA_OUT_EOF_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_DES_ADDR_CH0_S)) #define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -987,8 +986,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF @@ -1018,7 +1017,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 -#define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) +#define GDMA_OUT_WEIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) /* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 0. .*/ #define GDMA_TX_WEIGHT_CH0 0x0000000F @@ -1047,8 +1046,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0xC0) /* GDMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH1_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH1_V 0x1 @@ -1061,8 +1060,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH1_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH1_S 3 /* GDMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH1_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH1_V 0x1 @@ -1095,8 +1094,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH1_V 0x1 #define GDMA_IN_CHECK_OWNER_CH1_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 0 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 0 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH1 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH1_M ((GDMA_DMA_INFIFO_FULL_THRS_CH1_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH1_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH1_V 0xFFF @@ -1132,15 +1131,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1..*/ #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 1..*/ #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(4)) @@ -1148,32 +1147,32 @@ el 1..*/ #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 1..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 1..*/ #define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /* GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 1..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 1..*/ #define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH1_INT_RAW_V 0x1 @@ -1492,15 +1491,15 @@ nk descriptor has been received for Rx channel 1..*/ #define GDMA_INLINK_STOP_CH1_V 0x1 #define GDMA_INLINK_STOP_CH1_S 21 /* GDMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH1_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH1_V 0x1 #define GDMA_INLINK_AUTO_RET_CH1_S 20 /* GDMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH1 0x000FFFFF #define GDMA_INLINK_ADDR_CH1_M ((GDMA_INLINK_ADDR_CH1_V)<<(GDMA_INLINK_ADDR_CH1_S)) #define GDMA_INLINK_ADDR_CH1_V 0xFFFFF @@ -1528,8 +1527,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xE8) /* GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH1_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -1537,8 +1536,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xEC) /* GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH1_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -1568,7 +1567,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH1_S 0 -#define GDMA_IN_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) +#define GDMA_IN_WEIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) /* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 1. .*/ #define GDMA_RX_WEIGHT_CH1 0x0000000F @@ -1578,8 +1577,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x104) /* GDMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 1. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 1. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH1 0x0000000F #define GDMA_RX_PRI_CH1_M ((GDMA_RX_PRI_CH1_V)<<(GDMA_RX_PRI_CH1_S)) #define GDMA_RX_PRI_CH1_V 0xF @@ -1596,15 +1595,15 @@ y..*/ #define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x120) /* GDMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH1_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH1_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH1_S 5 /* GDMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH1_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH1_V 0x1 @@ -1617,8 +1616,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH1_V 0x1 #define GDMA_OUT_EOF_MODE_CH1_S 3 /* GDMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH1_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH1_V 0x1 @@ -1681,31 +1680,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink ' +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 1..*/ #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 1..*/ #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 /* GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 1. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 1. .*/ #define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH1_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH1_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH1_INT_RAW_S 1 /* GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 1..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +ouink descriptor has been transmitted to peripherals for Tx channel 1..*/ #define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH1_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH1_INT_RAW_V 0x1 @@ -1957,8 +1956,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 1..*/ #define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) /* GDMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH1 (BIT(23)) #define GDMA_OUTLINK_PARK_CH1_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH1_V 0x1 @@ -1982,8 +1981,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH1_V 0x1 #define GDMA_OUTLINK_STOP_CH1_S 20 /* GDMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH1 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH1_M ((GDMA_OUTLINK_ADDR_CH1_V)<<(GDMA_OUTLINK_ADDR_CH1_S)) #define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFF @@ -2011,8 +2010,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) /* GDMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH1_M ((GDMA_OUT_EOF_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_DES_ADDR_CH1_S)) #define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -2020,8 +2019,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF @@ -2051,7 +2050,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 -#define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) +#define GDMA_OUT_WEIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) /* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 1. .*/ #define GDMA_TX_WEIGHT_CH1 0x0000000F @@ -2061,8 +2060,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x164) /* GDMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 1. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 1. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH1 0x0000000F #define GDMA_TX_PRI_CH1_M ((GDMA_TX_PRI_CH1_V)<<(GDMA_TX_PRI_CH1_S)) #define GDMA_TX_PRI_CH1_V 0xF @@ -2080,8 +2079,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x180) /* GDMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH2_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH2_V 0x1 @@ -2094,8 +2093,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH2_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH2_S 3 /* GDMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH2_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH2_V 0x1 @@ -2128,8 +2127,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH2_V 0x1 #define GDMA_IN_CHECK_OWNER_CH2_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 2 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 2 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH2 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH2_M ((GDMA_DMA_INFIFO_FULL_THRS_CH2_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH2_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH2_V 0xFFF @@ -2165,15 +2164,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2..*/ #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 2..*/ #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(4)) @@ -2181,16 +2180,16 @@ el 2..*/ #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 2..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 2..*/ #define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 @@ -2525,14 +2524,14 @@ nk descriptor has been received for Rx channel 2..*/ #define GDMA_INLINK_STOP_CH2_V 0x1 #define GDMA_INLINK_STOP_CH2_S 21 /* GDMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH2_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH2_V 0x1 #define GDMA_INLINK_AUTO_RET_CH2_S 20 /* GDMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto +/*description: This register stores the 20 least significant bits of the first inlink descriptor r's address..*/ #define GDMA_INLINK_ADDR_CH2 0x000FFFFF #define GDMA_INLINK_ADDR_CH2_M ((GDMA_INLINK_ADDR_CH2_V)<<(GDMA_INLINK_ADDR_CH2_S)) @@ -2561,8 +2560,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1A8) /* GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH2_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -2570,8 +2569,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1AC) /* GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH2_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -2601,7 +2600,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH2_S 0 -#define GDMA_IN_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) +#define GDMA_IN_WEIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) /* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 2. .*/ #define GDMA_RX_WEIGHT_CH2 0x0000000F @@ -2611,8 +2610,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x1C4) /* GDMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 2. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 2. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH2 0x0000000F #define GDMA_RX_PRI_CH2_M ((GDMA_RX_PRI_CH2_V)<<(GDMA_RX_PRI_CH2_S)) #define GDMA_RX_PRI_CH2_V 0xF @@ -2629,15 +2628,15 @@ y..*/ #define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1E0) /* GDMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH2_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH2_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH2_S 5 /* GDMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH2_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH2_V 0x1 @@ -2650,8 +2649,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH2_V 0x1 #define GDMA_OUT_EOF_MODE_CH2_S 3 /* GDMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH2_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH2_V 0x1 @@ -2714,31 +2713,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 2..*/ #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 2..*/ #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 /* GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 2. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 2. .*/ #define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH2_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH2_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH2_INT_RAW_S 1 /* GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 2..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 2..*/ #define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH2_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH2_INT_RAW_V 0x1 @@ -2990,8 +2989,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 2..*/ #define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) /* GDMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH2 (BIT(23)) #define GDMA_OUTLINK_PARK_CH2_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH2_V 0x1 @@ -3015,8 +3014,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH2_V 0x1 #define GDMA_OUTLINK_STOP_CH2_S 20 /* GDMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH2 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH2_M ((GDMA_OUTLINK_ADDR_CH2_V)<<(GDMA_OUTLINK_ADDR_CH2_S)) #define GDMA_OUTLINK_ADDR_CH2_V 0xFFFFF @@ -3044,8 +3043,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) /* GDMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH2_M ((GDMA_OUT_EOF_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_DES_ADDR_CH2_S)) #define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -3053,8 +3052,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF @@ -3084,7 +3083,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 -#define GDMA_OUT_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) +#define GDMA_OUT_WEIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) /* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 2. .*/ #define GDMA_TX_WEIGHT_CH2 0x0000000F @@ -3094,8 +3093,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x224) /* GDMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 2. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 2. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH2 0x0000000F #define GDMA_TX_PRI_CH2_M ((GDMA_TX_PRI_CH2_V)<<(GDMA_TX_PRI_CH2_S)) #define GDMA_TX_PRI_CH2_V 0xF @@ -3113,8 +3112,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x240) /* GDMA_MEM_TRANS_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH3 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH3_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH3_V 0x1 @@ -3127,8 +3126,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH3_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH3_S 3 /* GDMA_INDSCR_BURST_EN_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH3 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH3_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH3_V 0x1 @@ -3161,8 +3160,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH3_V 0x1 #define GDMA_IN_CHECK_OWNER_CH3_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH3 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 3 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 3 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH3 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH3_M ((GDMA_DMA_INFIFO_FULL_THRS_CH3_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH3_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH3_V 0xFFF @@ -3198,15 +3197,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH3_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3..*/ #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 3..*/ #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_M (BIT(4)) @@ -3214,32 +3213,32 @@ el 3..*/ #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 3..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 3..*/ #define GDMA_IN_DSCR_ERR_CH3_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 3. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 3. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH3_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH3_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH3_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH3_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 3. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 3. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH3_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH3_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH3_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH3_INT_RAW_S 1 /* GDMA_IN_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 3..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 3..*/ #define GDMA_IN_DONE_CH3_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH3_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH3_INT_RAW_V 0x1 @@ -3558,15 +3557,15 @@ nk descriptor has been received for Rx channel 3..*/ #define GDMA_INLINK_STOP_CH3_V 0x1 #define GDMA_INLINK_STOP_CH3_S 21 /* GDMA_INLINK_AUTO_RET_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH3 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH3_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH3_V 0x1 #define GDMA_INLINK_AUTO_RET_CH3_S 20 /* GDMA_INLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH3 0x000FFFFF #define GDMA_INLINK_ADDR_CH3_M ((GDMA_INLINK_ADDR_CH3_V)<<(GDMA_INLINK_ADDR_CH3_S)) #define GDMA_INLINK_ADDR_CH3_V 0xFFFFF @@ -3594,8 +3593,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x268) /* GDMA_IN_SUC_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH3_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -3603,8 +3602,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x26C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH3_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -3634,7 +3633,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH3_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH3_S 0 -#define GDMA_IN_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) +#define GDMA_IN_WEIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) /* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 3. .*/ #define GDMA_RX_WEIGHT_CH3 0x0000000F @@ -3644,8 +3643,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x284) /* GDMA_RX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 3. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 3. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH3 0x0000000F #define GDMA_RX_PRI_CH3_M ((GDMA_RX_PRI_CH3_V)<<(GDMA_RX_PRI_CH3_S)) #define GDMA_RX_PRI_CH3_V 0xF @@ -3662,15 +3661,15 @@ y..*/ #define GDMA_OUT_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x2A0) /* GDMA_OUT_DATA_BURST_EN_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH3 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH3_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH3_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH3_S 5 /* GDMA_OUTDSCR_BURST_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH3 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH3_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH3_V 0x1 @@ -3683,8 +3682,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH3_V 0x1 #define GDMA_OUT_EOF_MODE_CH3_S 3 /* GDMA_OUT_AUTO_WRBACK_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH3 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH3_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH3_V 0x1 @@ -3747,15 +3746,15 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 3..*/ #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor error r, including owner error, the second and third word error of outlink descriptor for Tx channel 3..*/ #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) @@ -3763,15 +3762,15 @@ for Tx channel 3..*/ #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_S 2 /* GDMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 3. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 3. .*/ #define GDMA_OUT_EOF_CH3_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH3_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH3_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH3_INT_RAW_S 1 /* GDMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 3..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 3..*/ #define GDMA_OUT_DONE_CH3_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH3_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH3_INT_RAW_V 0x1 @@ -4023,8 +4022,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 3..*/ #define GDMA_OUT_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x2C0) /* GDMA_OUTLINK_PARK_CH3 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH3 (BIT(23)) #define GDMA_OUTLINK_PARK_CH3_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH3_V 0x1 @@ -4048,8 +4047,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH3_V 0x1 #define GDMA_OUTLINK_STOP_CH3_S 20 /* GDMA_OUTLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH3 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH3_M ((GDMA_OUTLINK_ADDR_CH3_V)<<(GDMA_OUTLINK_ADDR_CH3_S)) #define GDMA_OUTLINK_ADDR_CH3_V 0xFFFFF @@ -4077,8 +4076,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2C8) /* GDMA_OUT_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH3_M ((GDMA_OUT_EOF_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_DES_ADDR_CH3_S)) #define GDMA_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -4086,8 +4085,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2CC) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V 0xFFFFFFFF @@ -4117,7 +4116,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH3_S 0 -#define GDMA_OUT_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) +#define GDMA_OUT_WEIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) /* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 3. .*/ #define GDMA_TX_WEIGHT_CH3 0x0000000F @@ -4127,8 +4126,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x2E4) /* GDMA_TX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 3. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 3. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH3 0x0000000F #define GDMA_TX_PRI_CH3_M ((GDMA_TX_PRI_CH3_V)<<(GDMA_TX_PRI_CH3_S)) #define GDMA_TX_PRI_CH3_V 0xF @@ -4146,8 +4145,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x300) /* GDMA_MEM_TRANS_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH4 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH4_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH4_V 0x1 @@ -4160,8 +4159,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH4_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH4_S 3 /* GDMA_INDSCR_BURST_EN_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH4 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH4_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH4_V 0x1 @@ -4194,8 +4193,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH4_V 0x1 #define GDMA_IN_CHECK_OWNER_CH4_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH4 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 4 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 4 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH4 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH4_M ((GDMA_DMA_INFIFO_FULL_THRS_CH4_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH4_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH4_V 0xFFF @@ -4231,48 +4230,48 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH4_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4..*/ #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann -el 4..*/ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx +channel 4..*/ #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_M (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_V 0x1 #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 4..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 4..*/ #define GDMA_IN_DSCR_ERR_CH4_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 4. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 4. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH4_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH4_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH4_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH4_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 4. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 4. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH4_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH4_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH4_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH4_INT_RAW_S 1 /* GDMA_IN_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 4..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 4..*/ #define GDMA_IN_DONE_CH4_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH4_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH4_INT_RAW_V 0x1 @@ -4591,15 +4590,15 @@ nk descriptor has been received for Rx channel 4..*/ #define GDMA_INLINK_STOP_CH4_V 0x1 #define GDMA_INLINK_STOP_CH4_S 21 /* GDMA_INLINK_AUTO_RET_CH4 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH4 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH4_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH4_V 0x1 #define GDMA_INLINK_AUTO_RET_CH4_S 20 /* GDMA_INLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH4 0x000FFFFF #define GDMA_INLINK_ADDR_CH4_M ((GDMA_INLINK_ADDR_CH4_V)<<(GDMA_INLINK_ADDR_CH4_S)) #define GDMA_INLINK_ADDR_CH4_V 0xFFFFF @@ -4627,8 +4626,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x328) /* GDMA_IN_SUC_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH4_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -4636,8 +4635,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x32C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH4_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -4667,7 +4666,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH4_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH4_S 0 -#define GDMA_IN_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) +#define GDMA_IN_WEIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) /* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 4. .*/ #define GDMA_RX_WEIGHT_CH4 0x0000000F @@ -4695,15 +4694,15 @@ y..*/ #define GDMA_OUT_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x360) /* GDMA_OUT_DATA_BURST_EN_CH4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH4 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH4_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH4_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH4_S 5 /* GDMA_OUTDSCR_BURST_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH4 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH4_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH4_V 0x1 @@ -4716,8 +4715,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH4_V 0x1 #define GDMA_OUT_EOF_MODE_CH4_S 3 /* GDMA_OUT_AUTO_WRBACK_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH4 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH4_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH4_V 0x1 @@ -4780,15 +4779,15 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 4..*/ #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor error r, including owner error, the second and third word error of outlink descriptor for Tx channel 4..*/ #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW (BIT(2)) @@ -4796,15 +4795,15 @@ for Tx channel 4..*/ #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_S 2 /* GDMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 4. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 4. .*/ #define GDMA_OUT_EOF_CH4_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH4_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH4_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH4_INT_RAW_S 1 /* GDMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 4..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 4..*/ #define GDMA_OUT_DONE_CH4_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH4_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH4_INT_RAW_V 0x1 @@ -5056,8 +5055,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 4..*/ #define GDMA_OUT_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x380) /* GDMA_OUTLINK_PARK_CH4 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH4 (BIT(23)) #define GDMA_OUTLINK_PARK_CH4_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH4_V 0x1 @@ -5081,8 +5080,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH4_V 0x1 #define GDMA_OUTLINK_STOP_CH4_S 20 /* GDMA_OUTLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH4 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH4_M ((GDMA_OUTLINK_ADDR_CH4_V)<<(GDMA_OUTLINK_ADDR_CH4_S)) #define GDMA_OUTLINK_ADDR_CH4_V 0xFFFFF @@ -5110,8 +5109,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x388) /* GDMA_OUT_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH4_M ((GDMA_OUT_EOF_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_DES_ADDR_CH4_S)) #define GDMA_OUT_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -5119,8 +5118,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x38C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V 0xFFFFFFFF @@ -5150,7 +5149,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH4_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH4_S 0 -#define GDMA_OUT_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) +#define GDMA_OUT_WEIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) /* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 4. .*/ #define GDMA_TX_WEIGHT_CH4 0x0000000F @@ -5160,8 +5159,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH4_REG (DR_REG_GDMA_BASE + 0x3A4) /* GDMA_TX_PRI_CH4 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 4. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 4. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH4 0x0000000F #define GDMA_TX_PRI_CH4_M ((GDMA_TX_PRI_CH4_V)<<(GDMA_TX_PRI_CH4_S)) #define GDMA_TX_PRI_CH4_V 0xF @@ -5193,8 +5192,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PD_CONF_REG (DR_REG_GDMA_BASE + 0x3C4) /* GDMA_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Force to open the clock and bypass the gate-clock when accessing the RAM in D -MA. 0: A gate-clock will be used when accessing the RAM in DMA..*/ +/*description: 1: Force to open the clock and bypass the gate-clock when accessing the RAM in +DMA. 0: A gate-clock will be used when accessing the RAM in DMA..*/ #define GDMA_DMA_RAM_CLK_FO (BIT(6)) #define GDMA_DMA_RAM_CLK_FO_M (BIT(6)) #define GDMA_DMA_RAM_CLK_FO_V 0x1 @@ -5340,8 +5339,8 @@ s. 7: 72 bytes. 8: 80 bytes..*/ #define GDMA_EXTMEM_REJECT_ADDR_REG (DR_REG_GDMA_BASE + 0x3F4) /* GDMA_EXTMEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: This register store the first address rejected by permission control when access -ing external RAM..*/ +/*description: This register store the first address rejected by permission control when +accessing external RAM..*/ #define GDMA_EXTMEM_REJECT_ADDR 0xFFFFFFFF #define GDMA_EXTMEM_REJECT_ADDR_M ((GDMA_EXTMEM_REJECT_ADDR_V)<<(GDMA_EXTMEM_REJECT_ADDR_S)) #define GDMA_EXTMEM_REJECT_ADDR_V 0xFFFFFFFF @@ -5361,8 +5360,8 @@ ing external RAM..*/ #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_V 0xF #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_S 2 /* GDMA_EXTMEM_REJECT_ATTR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. B -it 1: if this bit is 1, the rejected accessing is WRITE..*/ +/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. +Bit 1: if this bit is 1, the rejected accessing is WRITE..*/ #define GDMA_EXTMEM_REJECT_ATTR 0x00000003 #define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S)) #define GDMA_EXTMEM_REJECT_ATTR_V 0x3 @@ -5370,8 +5369,8 @@ it 1: if this bit is 1, the rejected accessing is WRITE..*/ #define GDMA_EXTMEM_REJECT_INT_RAW_REG (DR_REG_GDMA_BASE + 0x3FC) /* GDMA_EXTMEM_REJECT_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when accessing external RAM is rejecte -d by permission control..*/ +/*description: The raw interrupt bit turns to high level when accessing external RAM is +rejected by permission control..*/ #define GDMA_EXTMEM_REJECT_INT_RAW (BIT(0)) #define GDMA_EXTMEM_REJECT_INT_RAW_M (BIT(0)) #define GDMA_EXTMEM_REJECT_INT_RAW_V 0x1 diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/include/soc/gdma_struct.h index 1a9b3ccf91..680a1cccf1 100644 --- a/components/soc/esp32s3/include/soc/gdma_struct.h +++ b/components/soc/esp32s3/include/soc/gdma_struct.h @@ -161,7 +161,7 @@ typedef volatile struct gdma_dev_s { uint32_t reserved12 : 20; }; uint32_t val; - } wight; + } weight; uint32_t reserved_40; union { struct { @@ -321,7 +321,7 @@ typedef volatile struct gdma_dev_s { uint32_t reserved12 : 20; }; uint32_t val; - } wight; + } weight; uint32_t reserved_a0; union { struct {