gpio: Clean up unit tests and enable ci ut on some previously disabled test cases

Eliminate UT_T1_GPIO runner requirement by routing internally through gpio matrix and by setting gpio pins to GPIO_MODE_INPUT_OUTPUT mode for all interrupt related test cases.
2022-03-09 14:37:41 +08:00 · 2022-03-09 14:37:41 +08:00 · 8d84033b8c
commit 8d84033b8c
--- a/components/driver/Kconfig
+++ b/components/driver/Kconfig
@ -185,6 +185,13 @@ menu "Driver configurations"
                pullup/pulldown mode in sleep.
                If this option is selected, chip will automatically emulate the behaviour of switching,
                and about 450B of source codes would be placed into IRAM.
+
+        config GPIO_CTRL_FUNC_IN_IRAM
+            bool "Place GPIO control functions into IRAM"
+            default n
+            help
+                Place GPIO control functions (like intr_disable/set_level) into IRAM,
+                so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
    endmenu # GPIO Configuration

    menu "GDMA Configuration"
--- a/components/driver/include/driver/gpio.h
+++ b/components/driver/include/driver/gpio.h
@ -94,6 +94,8 @@ esp_err_t gpio_intr_enable(gpio_num_t gpio_num);
 /**
 * @brief  Disable GPIO module interrupt signal
 *
+ * @note This function is allowed to be executed when Cache is disabled within ISR context, by enabling `CONFIG_GPIO_CTRL_FUNC_IN_IRAM`
+ *
 * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
 *
 * @return
@ -106,6 +108,8 @@ esp_err_t gpio_intr_disable(gpio_num_t gpio_num);
 /**
 * @brief  GPIO set output level
 *
+ * @note This function is allowed to be executed when Cache is disabled within ISR context, by enabling `CONFIG_GPIO_CTRL_FUNC_IN_IRAM`
+ *
 * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
 * @param  level Output level. 0: low ; 1: high
 *
--- a/components/driver/linker.lf
+++ b/components/driver/linker.lf
@ -23,3 +23,6 @@ entries:
        pulse_cnt: pcnt_unit_stop (noflash)
        pulse_cnt: pcnt_unit_clear_count (noflash)
        pulse_cnt: pcnt_unit_get_count (noflash)
+    if GPIO_CTRL_FUNC_IN_IRAM = y:
+        gpio: gpio_set_level (noflash)
+        gpio: gpio_intr_disable (noflash)
--- a/components/driver/test_apps/gpio/main/test_gpio.c
+++ b/components/driver/test_apps/gpio/main/test_gpio.c
--- a/components/driver/test_apps/gpio/main/test_gpio.h
+++ b/components/driver/test_apps/gpio/main/test_gpio.h
@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "soc/gpio_sig_map.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// GPIO self-test pins (GPIO_MODE_INPUT_OUTPUT)
+#define TEST_GPIO_INPUT_OUTPUT_IO1         (4)
+#define TEST_GPIO_INPUT_OUTPUT_IO2         (5)
+
+#if CONFIG_IDF_TARGET_ESP32
+#define TEST_GPIO_EXT_OUT_IO               (18)
+#define TEST_GPIO_EXT_IN_IO                (19)
+#define TEST_GPIO_INPUT_ONLY_PIN           (34)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (4)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC224_IDX)
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define TEST_GPIO_EXT_OUT_IO               (17)
+#define TEST_GPIO_EXT_IN_IO                (21)
+#define TEST_GPIO_INPUT_ONLY_PIN           (46)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC223_IDX)
+#elif CONFIG_IDF_TARGET_ESP32S3
+#define TEST_GPIO_EXT_OUT_IO               (17)
+#define TEST_GPIO_EXT_IN_IO                (21)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC208_IDX)
+#elif CONFIG_IDF_TARGET_ESP32C3
+#define TEST_GPIO_EXT_OUT_IO               (2)
+#define TEST_GPIO_EXT_IN_IO                (3)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC97_IDX)
+#elif CONFIG_IDF_TARGET_ESP32C2
+#define TEST_GPIO_EXT_OUT_IO               (2)
+#define TEST_GPIO_EXT_IN_IO                (3)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC97_IDX)
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define TEST_GPIO_EXT_OUT_IO               (6)
+#define TEST_GPIO_EXT_IN_IO                (7)
+#define TEST_GPIO_INPUT_LEVEL_LOW_PIN      (1)
+#define TEST_GPIO_SIGNAL_IDX               (SIG_IN_FUNC97_IDX)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe
+++ b/components/driver/test_apps/gpio/sdkconfig.ci.iram_safe
@ -1,4 +1,4 @@
 CONFIG_COMPILER_DUMP_RTL_FILES=y
-
+CONFIG_GPIO_CTRL_FUNC_IN_IRAM=y
 # silent the error check, as the error string are stored in rodata, causing RTL check failure
 CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
--- a/components/esp_rom/include/esp32h2/rom/gpio.h
+++ b/components/esp_rom/include/esp32h2/rom/gpio.h
@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef _ROM_GPIO_H_
 #define _ROM_GPIO_H_
@ -20,6 +12,7 @@

 #include "esp_attr.h"
 #include "soc/gpio_reg.h"
+#include "sdkconfig.h"

 #ifdef __cplusplus
 extern "C" {
@ -39,8 +32,13 @@ extern "C" {
 #define GPIO_ID_PIN(n)                  (GPIO_ID_PIN0+(n))
 #define GPIO_PIN_ADDR(i)                (GPIO_PIN0_REG + i*4)

+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
 #define GPIO_FUNC_IN_HIGH               0x38
 #define GPIO_FUNC_IN_LOW                0x3C
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
+#define GPIO_FUNC_IN_HIGH               0x1E
+#define GPIO_FUNC_IN_LOW                0x1F
+#endif

 #define GPIO_ID_IS_PIN_REGISTER(reg_id) \
    ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
--- a/components/hal/gpio_hal.c
+++ b/components/hal/gpio_hal.c
@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 // The HAL layer for GPIO (common part)

--- a/components/hal/linker.lf
+++ b/components/hal/linker.lf
@ -24,3 +24,5 @@ entries:
        systimer_hal (noflash)
    if GPTIMER_CTRL_FUNC_IN_IRAM = y:
        timer_hal_iram (noflash)
+    if GPIO_CTRL_FUNC_IN_IRAM = y:
+        gpio_hal: gpio_hal_intr_disable (noflash)
--- a/components/soc/esp32c3/include/soc/io_mux_reg.h
+++ b/components/soc/esp32c3/include/soc/io_mux_reg.h
@ -130,6 +130,9 @@
 #define SD_DATA2_GPIO_NUM 9
 #define SD_DATA3_GPIO_NUM 10

+#define USB_DM_GPIO_NUM   18
+#define USB_DP_GPIO_NUM   19
+
 #define MAX_RTC_GPIO_NUM 5
 #define MAX_PAD_GPIO_NUM 21
 #define MAX_GPIO_NUM    25
--- a/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h
+++ b/components/soc/esp32h2/include/rev1/soc/io_mux_reg.h
@ -149,6 +149,9 @@
 #define SD_DATA2_GPIO_NUM 9
 #define SD_DATA3_GPIO_NUM 10

+#define USB_DM_GPIO_NUM   18
+#define USB_DP_GPIO_NUM   19
+
 #define MAX_RTC_GPIO_NUM 5
 #define MAX_PAD_GPIO_NUM 40
 #define MAX_GPIO_NUM    44
--- a/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h
+++ b/components/soc/esp32h2/include/rev2/soc/io_mux_reg.h
@ -124,6 +124,9 @@
 #define SPI_D_GPIO_NUM               18
 #define SPI_Q_GPIO_NUM               14

+#define USB_DM_GPIO_NUM              24
+#define USB_DP_GPIO_NUM              25
+
 #define MAX_RTC_GPIO_NUM             12            // GPIO7~12 are the rtc_io pads
 #define MAX_PAD_GPIO_NUM             25
 #define MAX_GPIO_NUM                 29
--- a/components/soc/esp32h2/include/soc/gpio_pins.h
+++ b/components/soc/esp32h2/include/soc/gpio_pins.h
@ -1,26 +1,25 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */


 #pragma once

+#include "sdkconfig.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif

+#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
+#define GPIO_MATRIX_CONST_ONE_INPUT   (0x38)
+#define GPIO_MATRIX_CONST_ZERO_INPUT  (0x3C)
+#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
 #define GPIO_MATRIX_CONST_ONE_INPUT   (0x1E)
 #define GPIO_MATRIX_CONST_ZERO_INPUT  (0x1F)
+#endif

 #ifdef __cplusplus
 }
--- a/components/soc/esp32s3/include/soc/io_mux_reg.h
+++ b/components/soc/esp32s3/include/soc/io_mux_reg.h
@ -154,6 +154,8 @@
 #define SD_DATA1_GPIO_NUM 14
 #define SD_DATA2_GPIO_NUM 9
 #define SD_DATA3_GPIO_NUM 10
+#define USB_DM_GPIO_NUM   19
+#define USB_DP_GPIO_NUM   20

 #define MAX_RTC_GPIO_NUM 21
 #define MAX_PAD_GPIO_NUM 48
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@ -580,7 +580,6 @@ components/esp_rom/include/esp32h2/rom/digital_signature.h
 components/esp_rom/include/esp32h2/rom/efuse.h
 components/esp_rom/include/esp32h2/rom/esp_flash.h
 components/esp_rom/include/esp32h2/rom/ets_sys.h
-components/esp_rom/include/esp32h2/rom/gpio.h
 components/esp_rom/include/esp32h2/rom/hmac.h
 components/esp_rom/include/esp32h2/rom/libc_stubs.h
 components/esp_rom/include/esp32h2/rom/lldesc.h
@ -906,7 +905,6 @@ components/hal/esp32s3/include/hal/uhci_ll.h
 components/hal/esp32s3/include/hal/usb_ll.h
 components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h
 components/hal/esp32s3/interrupt_descriptor_table.c
-components/hal/gpio_hal.c
 components/hal/include/hal/aes_hal.h
 components/hal/include/hal/aes_types.h
 components/hal/include/hal/brownout_hal.h
@ -1384,7 +1382,6 @@ components/soc/esp32h2/include/soc/efuse_reg.h
 components/soc/esp32h2/include/soc/efuse_struct.h
 components/soc/esp32h2/include/soc/extmem_reg.h
 components/soc/esp32h2/include/soc/fe_reg.h
-components/soc/esp32h2/include/soc/gpio_pins.h
 components/soc/esp32h2/include/soc/gpio_sd_reg.h
 components/soc/esp32h2/include/soc/gpio_sd_struct.h
 components/soc/esp32h2/include/soc/hwcrypto_reg.h