kopia lustrzana https://github.com/espressif/esp-idf
freertos: Disable portUSING_MPU_WRAPPERS in FreeRTOS SMP Xtensa port
This commit disables portUSING_MPU_WRAPPERS for the FreeRTOS SMP xtensa port. This was previously enabled due to the need to keep a CPSA (coprocessor save area pointer) in the TCB. The CPSA pointer is now calculated at run time.pull/8812/head
rodzic
8b4e032255
commit
8c92d0b2af
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@ -196,7 +196,7 @@ This file get's pulled into assembly sources. Therefore, some includes need to b
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#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY
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#elif CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#define configCHECK_FOR_STACK_OVERFLOW 2
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#endif
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#endif
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#define configRECORD_STACK_HIGH_ADDRESS 1
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#define configRECORD_STACK_HIGH_ADDRESS 1 // This must be set as the port requires TCB.pxEndOfStack
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// ------------------- Run-time Stats ----------------------
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// ------------------- Run-time Stats ----------------------
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@ -247,54 +247,6 @@ static inline BaseType_t __attribute__((always_inline)) xPortGetCoreID( void )
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return (BaseType_t) cpu_hal_get_core_id();
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return (BaseType_t) cpu_hal_get_core_id();
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}
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}
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/* ------------------------------------------------------ Misc ---------------------------------------------------------
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* - Miscellaneous porting macros
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* - These are not part of the FreeRTOS porting interface, but are used by other FreeRTOS dependent components
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* - [refactor-todo] Remove dependency on MPU wrappers by modifying TCB
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* ------------------------------------------------------------------------------------------------------------------ */
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// -------------------- Co-Processor -----------------------
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// When coprocessors are defined, we maintain a pointer to coprocessors area.
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// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
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// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
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// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
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typedef struct {
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#if XCHAL_CP_NUM > 0
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volatile StackType_t *coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
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#endif
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#if portUSING_MPU_WRAPPERS
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// Define here mpu_settings, which is port dependent
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int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
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#endif
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} xMPU_SETTINGS;
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// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
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#if (XCHAL_CP_NUM > 0) && !portUSING_MPU_WRAPPERS // If MPU wrappers not used, we still need to allocate coproc area
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#undef portUSING_MPU_WRAPPERS
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#define portUSING_MPU_WRAPPERS 1 // Enable it to allocate coproc area
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#define MPU_WRAPPERS_H // Override mpu_wrapper.h to disable unwanted code
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#define PRIVILEGED_FUNCTION
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#define PRIVILEGED_DATA
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#endif
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void _xt_coproc_release(volatile void *coproc_sa_base);
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/*
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* The structures and methods of manipulating the MPU are contained within the
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* port layer.
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*
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* Fills the xMPUSettings structure with the memory region information
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* contained in xRegions.
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*/
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#if( portUSING_MPU_WRAPPERS == 1 )
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struct xMEMORY_REGION;
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void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION *const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
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void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings );
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#endif
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/* ------------------------------------------------ IDF Compatibility --------------------------------------------------
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/* ------------------------------------------------ IDF Compatibility --------------------------------------------------
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* - These macros and functions need to be defined for IDF to compile
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* - These macros and functions need to be defined for IDF to compile
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* ------------------------------------------------------------------------------------------------------------------ */
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* ------------------------------------------------------------------------------------------------------------------ */
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@ -437,17 +437,19 @@ static void vPortTaskWrapper(TaskFunction_t pxCode, void *pvParameters)
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}
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}
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#endif
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#endif
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const DRAM_ATTR uint32_t offset_pxEndOfStack = offsetof(StaticTask_t, pxDummy8);
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const DRAM_ATTR uint32_t offset_uxCoreAffinityMask = offsetof(StaticTask_t, uxDummy25);
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const DRAM_ATTR uint32_t offset_cpsa = XT_CP_SIZE;
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#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
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#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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StackType_t * pxEndOfStack,
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StackType_t * pxEndOfStack,
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TaskFunction_t pxCode,
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TaskFunction_t pxCode,
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void * pvParameters,
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void * pvParameters )
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BaseType_t xRunPrivileged )
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#else
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#else
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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TaskFunction_t pxCode,
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void * pvParameters,
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void * pvParameters )
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BaseType_t xRunPrivileged )
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#endif
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#endif
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{
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{
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StackType_t *sp, *tp;
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StackType_t *sp, *tp;
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@ -624,34 +626,3 @@ void vApplicationMinimalIdleHook( void )
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esp_vApplicationIdleHook(); //Run IDF style hooks
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esp_vApplicationIdleHook(); //Run IDF style hooks
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}
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}
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#endif // CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
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#endif // CONFIG_FREERTOS_USE_MINIMAL_IDLE_HOOK
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/* ---------------------------------------------- Misc Implementations -------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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// -------------------- Co-Processor -----------------------
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/*
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* Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
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*/
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#if portUSING_MPU_WRAPPERS
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void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION *const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth )
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{
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#if XCHAL_CP_NUM > 0
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
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xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
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/* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
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* clear the stack area after we return. This is done in pxPortInitialiseStack().
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*/
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#endif
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}
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void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings )
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{
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/* If task has live floating point registers somewhere, release them */
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_xt_coproc_release( xMPUSettings->coproc_area );
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}
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#endif /* portUSING_MPU_WRAPPERS */
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@ -32,9 +32,34 @@
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#include "sdkconfig.h"
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#include "sdkconfig.h"
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#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */
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#define TOPOFSTACK_OFFS 0x00 /* StackType_t *pxTopOfStack */
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#define CP_TOPOFSTACK_OFFS 0x04 /* xMPU_SETTINGS.coproc_area */
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.extern pxCurrentTCBs
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.extern pxCurrentTCBs
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.extern offset_pxEndOfStack
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.extern offset_cpsa
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/*
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Macro to get a task's coprocessor save area (CPSA) from its TCB
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Entry:
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- reg_A contains a pointer to the TCB
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Exit:
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- reg_A contains a pointer to the CPSA
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- reg_B destroyed
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*/
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.macro get_cpsa_from_tcb reg_A reg_B
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// Get TCB.pxEndOfStack from reg_A
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movi \reg_B, offset_pxEndOfStack /* Move &offset_pxEndOfStack into reg_B */
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l32i \reg_B, \reg_B, 0 /* Load offset_pxEndOfStack into reg_B */
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add \reg_A, \reg_A, \reg_B /* Calculate &pxEndOfStack to reg_A (&TCB + offset_pxEndOfStack) */
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l32i \reg_A, \reg_A, 0 /* Load TCB.pxEndOfStack into reg_A */
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//Offset to start of coproc save area
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movi \reg_B, offset_cpsa /* Move &offset_cpsa into reg_B */
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l32i \reg_B, \reg_B, 0 /* Load offset_cpsa into reg_B */
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sub \reg_A, \reg_A, \reg_B /* Subtract offset_cpsa from pxEndOfStack to get to start of CP save area (unaligned) */
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//Align down start of CP save area to 16 byte boundary
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movi \reg_B, ~(0xF)
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and \reg_A, \reg_A, \reg_B /* Align CPSA pointer to 16 bytes */
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.endm
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/*
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/*
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*******************************************************************************
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*******************************************************************************
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@ -135,23 +160,19 @@ _frxt_int_enter:
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mull a2, a4, a2
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mull a2, a4, a2
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add a1, a1, a2 /* for current proc */
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add a1, a1, a2 /* for current proc */
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#ifdef CONFIG_FREERTOS_FPU_IN_ISR
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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rsr a3, CPENABLE /* Restore thread scope CPENABLE */
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rsr a3, CPENABLE /* Restore thread scope CPENABLE */
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addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */
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addi sp, sp,-4 /* ISR will manage FPU coprocessor by forcing */
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s32i a3, a1, 0 /* its trigger */
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s32i a3, a1, 0 /* its trigger */
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#endif
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#endif
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#endif
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.Lnested:
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.Lnested:
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1:
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1:
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#ifdef CONFIG_FREERTOS_FPU_IN_ISR
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */
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movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */
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wsr a3, CPENABLE
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wsr a3, CPENABLE
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rsync
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rsync
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#endif
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#endif
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#endif
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mov a0, a12 /* restore return addr and return */
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mov a0, a12 /* restore return addr and return */
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ret
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ret
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@ -189,14 +210,12 @@ _frxt_int_exit:
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s32i a2, a3, 0 /* save nesting count */
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s32i a2, a3, 0 /* save nesting count */
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bnez a2, .Lnesting /* !=0 after decr so still nested */
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bnez a2, .Lnesting /* !=0 after decr so still nested */
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#ifdef CONFIG_FREERTOS_FPU_IN_ISR
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#if CONFIG_FREERTOS_FPU_IN_ISR && XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */
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l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */
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addi sp, sp, 4
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addi sp, sp, 4
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wsr a3, CPENABLE
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wsr a3, CPENABLE
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rsync /* ensure CPENABLE was modified */
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rsync /* ensure CPENABLE was modified */
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#endif
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#endif
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#endif
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movi a2, pxCurrentTCBs
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movi a2, pxCurrentTCBs
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addx4 a2, a4, a2
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addx4 a2, a4, a2
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@ -474,11 +493,11 @@ _frxt_dispatch:
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#if XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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/* Restore CPENABLE from task's co-processor save area. */
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/* Restore CPENABLE from task's co-processor save area. */
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movi a3, pxCurrentTCBs /* cp_state = */
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movi a2, pxCurrentTCBs /* cp_state = */
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getcoreid a2
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getcoreid a3
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addx4 a3, a2, a3
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addx4 a2, a3, a2
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l32i a3, a3, 0
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l32i a2, a2, 0
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l32i a2, a3, CP_TOPOFSTACK_OFFS /* StackType_t *pxStack; */
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get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
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l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */
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l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */
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wsr a3, CPENABLE
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wsr a3, CPENABLE
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#endif
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#endif
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@ -573,7 +592,7 @@ vPortYield:
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#if XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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/* Clear CPENABLE, also in task's co-processor state save area. */
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/* Clear CPENABLE, also in task's co-processor state save area. */
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l32i a2, a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCBs->cp_state */
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get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
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movi a3, 0
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movi a3, 0
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wsr a3, CPENABLE
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wsr a3, CPENABLE
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beqz a2, 1f
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beqz a2, 1f
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@ -614,12 +633,12 @@ vPortYieldFromInt:
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#if XCHAL_CP_NUM > 0
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#if XCHAL_CP_NUM > 0
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/* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */
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/* Save CPENABLE in task's co-processor save area, and clear CPENABLE. */
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movi a3, pxCurrentTCBs /* cp_state = */
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movi a2, pxCurrentTCBs /* cp_state = */
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getcoreid a2
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getcoreid a3
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addx4 a3, a2, a3
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addx4 a2, a3, a2
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l32i a3, a3, 0
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l32i a2, a2, 0
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l32i a2, a3, CP_TOPOFSTACK_OFFS
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get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */
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rsr a3, CPENABLE
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rsr a3, CPENABLE
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s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */
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s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */
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@ -673,7 +692,7 @@ _frxt_task_coproc_state:
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l32i a15, a15, 0 /* && pxCurrentTCBs != 0) { */
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l32i a15, a15, 0 /* && pxCurrentTCBs != 0) { */
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beqz a15, 2f
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beqz a15, 2f
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l32i a15, a15, CP_TOPOFSTACK_OFFS
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get_cpsa_from_tcb a15, a3 /* After this, pointer to CP save area is in a15, a3 is destroyed */
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ret
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ret
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1: movi a15, 0
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1: movi a15, 0
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@ -107,8 +107,8 @@
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Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
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Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
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Please change this when the tcb structure is changed
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Please change this when the tcb structure is changed
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*/
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*/
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#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3
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.extern pxCurrentTCBs
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.extern pxCurrentTCBs
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.extern offset_uxCoreAffinityMask
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/*
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/*
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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@ -908,35 +908,34 @@ _xt_coproc_exc:
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/* Get co-processor state save area of new owner thread. */
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/* Get co-processor state save area of new owner thread. */
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call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
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call0 XT_RTOS_CP_STATE /* a15 = new owner's save area */
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#if CONFIG_FREERTOS_FPU_IN_ISR
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#ifndef CONFIG_FREERTOS_FPU_IN_ISR
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beqz a15, .L_skip_core_pin /* CP used in ISR, skip task pinning */
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beqz a15, .L_goto_invalid
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#else
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beqz a15, .L_goto_invalid /* not in a thread (invalid) */
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#endif
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#endif
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/*When FPU in ISR is enabled we could deal with zeroed a15 */
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/* CP operations are incompatible with unpinned tasks. Thus we pin the task
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to the current running core. */
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movi a2, pxCurrentTCBs
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getcoreid a3 /* a3 = current core ID */
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addx4 a2, a3, a2
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l32i a2, a2, 0 /* a2 = start of pxCurrentTCBs[cpuid] */
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movi a4, offset_uxCoreAffinityMask
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l32i a4, a4, 0 /* a4 = offset_uxCoreAffinityMask */
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add a2, a2, a4 /* a2 = &TCB.uxCoreAffinityMask */
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ssl a3 /* Use core ID as shift amount */
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movi a4, 1
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sll a4, a4 /* a4 = uxCoreAffinityMask = (1 << core ID) */
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s32i a4, a2, 0 /* Store affinity mask to TCB.uxCoreAffinityMask */
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#if CONFIG_FREERTOS_FPU_IN_ISR
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||||||
|
.L_skip_core_pin:
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Enable the co-processor's bit in CPENABLE. */
|
/* Enable the co-processor's bit in CPENABLE. */
|
||||||
movi a0, _xt_coproc_mask
|
movi a0, _xt_coproc_mask
|
||||||
rsr a4, CPENABLE /* a4 = CPENABLE */
|
rsr a4, CPENABLE /* a4 = CPENABLE */
|
||||||
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
|
addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */
|
||||||
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
|
l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */
|
||||||
|
|
||||||
/* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
|
|
||||||
here, to keep the entire thing from crashing, it's better to pin the task to whatever
|
|
||||||
core we're running on now. */
|
|
||||||
movi a2, pxCurrentTCBs
|
|
||||||
getcoreid a3
|
|
||||||
addx4 a2, a3, a2
|
|
||||||
l32i a2, a2, 0 /* a2 = start of pxCurrentTCBs[cpuid] */
|
|
||||||
addi a2, a2, TASKTCB_XCOREID_OFFSET /* offset to xCoreID in tcb struct */
|
|
||||||
s32i a3, a2, 0 /* store current cpuid */
|
|
||||||
|
|
||||||
/* Grab correct xt_coproc_owner_sa for this core */
|
|
||||||
movi a2, XCHAL_CP_MAX << 2
|
|
||||||
mull a2, a2, a3 /* multiply by current processor id */
|
|
||||||
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
|
|
||||||
add a3, a3, a2 /* a3 = owner area needed for this processor */
|
|
||||||
|
|
||||||
extui a2, a0, 0, 16 /* coprocessor bitmask portion */
|
extui a2, a0, 0, 16 /* coprocessor bitmask portion */
|
||||||
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
|
or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */
|
||||||
wsr a4, CPENABLE
|
wsr a4, CPENABLE
|
||||||
|
@ -946,7 +945,12 @@ Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
|
||||||
everywhere): _xt_coproc_release assumes it works like this in order not to need
|
everywhere): _xt_coproc_release assumes it works like this in order not to need
|
||||||
locking.
|
locking.
|
||||||
*/
|
*/
|
||||||
|
/* Grab correct xt_coproc_owner_sa for this core */
|
||||||
|
getcoreid a3 /* a3 = current core ID */
|
||||||
|
movi a2, XCHAL_CP_MAX << 2
|
||||||
|
mull a2, a2, a3 /* multiply by current processor id */
|
||||||
|
movi a3, _xt_coproc_owner_sa /* a3 = base of owner array */
|
||||||
|
add a3, a3, a2 /* a3 = owner area needed for this processor */
|
||||||
|
|
||||||
/* Get old coprocessor owner thread (save area ptr) and assign new one. */
|
/* Get old coprocessor owner thread (save area ptr) and assign new one. */
|
||||||
addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */
|
addx4 a3, a5, a3 /* a3 = &_xt_coproc_owner_sa[n] */
|
||||||
|
|
|
@ -2835,13 +2835,6 @@ static BaseType_t prvCreateIdleTasks( void )
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||||||
|
|
||||||
#ifdef ESP_PLATFORM
|
|
||||||
#if ( configUSE_CORE_AFFINITY == 1 && configNUM_CORES > 1 )
|
|
||||||
//Don't forget to pin the created IDLE tasks
|
|
||||||
vTaskCoreAffinitySet(xIdleTaskHandle[ xCoreID ], (1 << xCoreID) );
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
}
|
}
|
||||||
|
|
||||||
return xReturn;
|
return xReturn;
|
||||||
|
|
Ładowanie…
Reference in New Issue