ulp-riscv: enable ULP-RISCV ADC example for esp32s2

ADC can now be used from the ULP-RISCV on S2 after the RTC power parameters were
fixed in a624d8d061

Closes https://github.com/espressif/esp-idf/issues/11052
Closes https://github.com/espressif/esp-idf/issues/11040

examples/system/.build-test-rules.yml

@@ -197,7 +197,7 @@ examples/system/ulp_fsm/ulp_adc:
 
 examples/system/ulp_riscv/adc:
   enable:
-    - if: IDF_TARGET in ["esp32s3"]
+    - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       temporary: true
       reason: the other targets are not tested yet
 

examples/system/ulp_riscv/adc/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-S3 |
-| ----------------- | -------- |
+| Supported Targets | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- |
 
 # ULP-RISC-V ADC Example