From 8ad3f2ba57af9cdca05cd9f7350dec8676bb9f9f Mon Sep 17 00:00:00 2001 From: Sachin Parekh Date: Tue, 17 May 2022 14:49:43 +0530 Subject: [PATCH] esp32c2: Add support for RNG --- .../src/bootloader_random_esp32c2.c | 48 ++- .../soc/esp32c2/include/soc/apb_saradc_reg.h | 312 +++++++++--------- 2 files changed, 202 insertions(+), 158 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random_esp32c2.c b/components/bootloader_support/src/bootloader_random_esp32c2.c index 9254c167ae..6efe296244 100644 --- a/components/bootloader_support/src/bootloader_random_esp32c2.c +++ b/components/bootloader_support/src/bootloader_random_esp32c2.c @@ -11,13 +11,57 @@ #include "soc/apb_saradc_reg.h" #include "soc/system_reg.h" #include "esp_private/regi2c_ctrl.h" +#include "regi2c_saradc.h" void bootloader_random_enable(void) { - // TODO: IDF-4021 + /* RNG module is always clock enabled */ + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0x3); + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_PU_M); + + // Bridging sar2 internal reference voltage + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0); + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_TSENS_ADDR, 0); + + // Enable SAR ADC2 internal channel to read adc2 ref voltage for additional entropy + SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_APB_SARADC_CLK_EN_M); + CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_APB_SARADC_RST_M); + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLK_SEL, 0x2); + SET_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); + SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_GATED_M); + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0x3); + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 1); + + REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_RSTB_WAIT, 8); + REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_XPD_WAIT, 5); + REG_SET_FIELD(APB_SARADC_FSM_WAIT_REG, APB_SARADC_STANDBY_WAIT, 100); + + SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_P_CLEAR_M); + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR_PATT_LEN, 0); + REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1, 0x9cffff);// Set adc2 internal channel & atten + REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2, 0xffffff); + // Set ADC sampling frequency + REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_REG_CLKM_DIV_NUM, 15); + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_MEAS_NUM_LIMIT); + SET_PERI_REG_MASK(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M); + SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); } void bootloader_random_disable(void) { - // TODO: IDF-4021 + /* Restore internal I2C bus state */ + REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0); + + /* Restore SARADC to default mode */ + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); + CLEAR_PERI_REG_MASK(APB_SARADC_DMA_CONF_REG, APB_SARADC_APB_ADC_TRANS_M); + REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB1_REG, APB_SARADC_SAR_PATT_TAB1, 0xffffff); + REG_SET_FIELD(APB_SARADC_SAR_PATT_TAB2_REG, APB_SARADC_SAR_PATT_TAB2, 0xffffff); + CLEAR_PERI_REG_MASK(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_EN_M); + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_XPD_SAR_FORCE, 0); + REG_SET_FIELD(RTC_CNTL_SENSOR_CTRL_REG, RTC_CNTL_FORCE_XPD_SAR, 0); } diff --git a/components/soc/esp32c2/include/soc/apb_saradc_reg.h b/components/soc/esp32c2/include/soc/apb_saradc_reg.h index 48da47ee50..2122cd8d9a 100644 --- a/components/soc/esp32c2/include/soc/apb_saradc_reg.h +++ b/components/soc/esp32c2/include/soc/apb_saradc_reg.h @@ -14,115 +14,115 @@ extern "C" { /** APB_SARADC_CTRL_REG register * register description */ -#define APB_SARADC_CTRL_REG (DR_REG_APB_BASE + 0x0) -/** APB_SARADC_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0) +/** APB_SARADC_START_FORCE : R/W; bitpos: [0]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_START_FORCE (BIT(0)) -#define APB_SARADC_SARADC_START_FORCE_M (APB_SARADC_SARADC_START_FORCE_V << APB_SARADC_SARADC_START_FORCE_S) -#define APB_SARADC_SARADC_START_FORCE_V 0x00000001U -#define APB_SARADC_SARADC_START_FORCE_S 0 -/** APB_SARADC_SARADC_START : R/W; bitpos: [1]; default: 0; +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (APB_SARADC_START_FORCE_V << APB_SARADC_START_FORCE_S) +#define APB_SARADC_START_FORCE_V 0x00000001U +#define APB_SARADC_START_FORCE_S 0 +/** APB_SARADC_START : R/W; bitpos: [1]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_START (BIT(1)) -#define APB_SARADC_SARADC_START_M (APB_SARADC_SARADC_START_V << APB_SARADC_SARADC_START_S) -#define APB_SARADC_SARADC_START_V 0x00000001U -#define APB_SARADC_SARADC_START_S 1 -/** APB_SARADC_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (APB_SARADC_START_V << APB_SARADC_START_S) +#define APB_SARADC_START_V 0x00000001U +#define APB_SARADC_START_S 1 +/** APB_SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1; * Need add description */ -#define APB_SARADC_SARADC_SAR_CLK_GATED (BIT(6)) -#define APB_SARADC_SARADC_SAR_CLK_GATED_M (APB_SARADC_SARADC_SAR_CLK_GATED_V << APB_SARADC_SARADC_SAR_CLK_GATED_S) -#define APB_SARADC_SARADC_SAR_CLK_GATED_V 0x00000001U -#define APB_SARADC_SARADC_SAR_CLK_GATED_S 6 -/** APB_SARADC_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (APB_SARADC_SAR_CLK_GATED_V << APB_SARADC_SAR_CLK_GATED_S) +#define APB_SARADC_SAR_CLK_GATED_V 0x00000001U +#define APB_SARADC_SAR_CLK_GATED_S 6 +/** APB_SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4; * SAR clock divider */ -#define APB_SARADC_SARADC_SAR_CLK_DIV 0x000000FFU -#define APB_SARADC_SARADC_SAR_CLK_DIV_M (APB_SARADC_SARADC_SAR_CLK_DIV_V << APB_SARADC_SARADC_SAR_CLK_DIV_S) -#define APB_SARADC_SARADC_SAR_CLK_DIV_V 0x000000FFU -#define APB_SARADC_SARADC_SAR_CLK_DIV_S 7 -/** APB_SARADC_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; +#define APB_SARADC_SAR_CLK_DIV 0x000000FFU +#define APB_SARADC_SAR_CLK_DIV_M (APB_SARADC_SAR_CLK_DIV_V << APB_SARADC_SAR_CLK_DIV_S) +#define APB_SARADC_SAR_CLK_DIV_V 0x000000FFU +#define APB_SARADC_SAR_CLK_DIV_S 7 +/** APB_SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7; * 0 ~ 15 means length 1 ~ 16 */ -#define APB_SARADC_SARADC_SAR_PATT_LEN 0x00000007U -#define APB_SARADC_SARADC_SAR_PATT_LEN_M (APB_SARADC_SARADC_SAR_PATT_LEN_V << APB_SARADC_SARADC_SAR_PATT_LEN_S) -#define APB_SARADC_SARADC_SAR_PATT_LEN_V 0x00000007U -#define APB_SARADC_SARADC_SAR_PATT_LEN_S 15 -/** APB_SARADC_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; +#define APB_SARADC_SAR_PATT_LEN 0x00000007U +#define APB_SARADC_SAR_PATT_LEN_M (APB_SARADC_SAR_PATT_LEN_V << APB_SARADC_SAR_PATT_LEN_S) +#define APB_SARADC_SAR_PATT_LEN_V 0x00000007U +#define APB_SARADC_SAR_PATT_LEN_S 15 +/** APB_SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0; * clear the pointer of pattern table for DIG ADC1 CTRL */ -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR (BIT(23)) -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S) -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U -#define APB_SARADC_SARADC_SAR_PATT_P_CLEAR_S 23 -/** APB_SARADC_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; +#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR_PATT_P_CLEAR_M (APB_SARADC_SAR_PATT_P_CLEAR_V << APB_SARADC_SAR_PATT_P_CLEAR_S) +#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x00000001U +#define APB_SARADC_SAR_PATT_P_CLEAR_S 23 +/** APB_SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0; * force option to xpd sar blocks */ -#define APB_SARADC_SARADC_XPD_SAR_FORCE 0x00000003U -#define APB_SARADC_SARADC_XPD_SAR_FORCE_M (APB_SARADC_SARADC_XPD_SAR_FORCE_V << APB_SARADC_SARADC_XPD_SAR_FORCE_S) -#define APB_SARADC_SARADC_XPD_SAR_FORCE_V 0x00000003U -#define APB_SARADC_SARADC_XPD_SAR_FORCE_S 27 -/** APB_SARADC_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; +#define APB_SARADC_XPD_SAR_FORCE 0x00000003U +#define APB_SARADC_XPD_SAR_FORCE_M (APB_SARADC_XPD_SAR_FORCE_V << APB_SARADC_XPD_SAR_FORCE_S) +#define APB_SARADC_XPD_SAR_FORCE_V 0x00000003U +#define APB_SARADC_XPD_SAR_FORCE_S 27 +/** APB_SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1; * wait arbit signal stable after sar_done */ -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE 0x00000003U -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_SARADC_WAIT_ARB_CYCLE_S) -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_V 0x00000003U -#define APB_SARADC_SARADC_WAIT_ARB_CYCLE_S 30 +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003U +#define APB_SARADC_WAIT_ARB_CYCLE_M (APB_SARADC_WAIT_ARB_CYCLE_V << APB_SARADC_WAIT_ARB_CYCLE_S) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x00000003U +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 /** APB_SARADC_CTRL2_REG register * register description */ -#define APB_SARADC_CTRL2_REG (DR_REG_APB_BASE + 0x4) -/** APB_SARADC_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4) +/** APB_SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT (BIT(0)) -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_SARADC_MEAS_NUM_LIMIT_S) -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_V 0x00000001U -#define APB_SARADC_SARADC_MEAS_NUM_LIMIT_S 0 -/** APB_SARADC_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (APB_SARADC_MEAS_NUM_LIMIT_V << APB_SARADC_MEAS_NUM_LIMIT_S) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x00000001U +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 +/** APB_SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255; * max conversion number */ -#define APB_SARADC_SARADC_MAX_MEAS_NUM 0x000000FFU -#define APB_SARADC_SARADC_MAX_MEAS_NUM_M (APB_SARADC_SARADC_MAX_MEAS_NUM_V << APB_SARADC_SARADC_MAX_MEAS_NUM_S) -#define APB_SARADC_SARADC_MAX_MEAS_NUM_V 0x000000FFU -#define APB_SARADC_SARADC_MAX_MEAS_NUM_S 1 -/** APB_SARADC_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; +#define APB_SARADC_MAX_MEAS_NUM 0x000000FFU +#define APB_SARADC_MAX_MEAS_NUM_M (APB_SARADC_MAX_MEAS_NUM_V << APB_SARADC_MAX_MEAS_NUM_S) +#define APB_SARADC_MAX_MEAS_NUM_V 0x000000FFU +#define APB_SARADC_MAX_MEAS_NUM_S 1 +/** APB_SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0; * 1: data to DIG ADC1 CTRL is inverted, otherwise not */ -#define APB_SARADC_SARADC_SAR1_INV (BIT(9)) -#define APB_SARADC_SARADC_SAR1_INV_M (APB_SARADC_SARADC_SAR1_INV_V << APB_SARADC_SARADC_SAR1_INV_S) -#define APB_SARADC_SARADC_SAR1_INV_V 0x00000001U -#define APB_SARADC_SARADC_SAR1_INV_S 9 -/** APB_SARADC_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (APB_SARADC_SAR1_INV_V << APB_SARADC_SAR1_INV_S) +#define APB_SARADC_SAR1_INV_V 0x00000001U +#define APB_SARADC_SAR1_INV_S 9 +/** APB_SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0; * 1: data to DIG ADC2 CTRL is inverted, otherwise not */ -#define APB_SARADC_SARADC_SAR2_INV (BIT(10)) -#define APB_SARADC_SARADC_SAR2_INV_M (APB_SARADC_SARADC_SAR2_INV_V << APB_SARADC_SARADC_SAR2_INV_S) -#define APB_SARADC_SARADC_SAR2_INV_V 0x00000001U -#define APB_SARADC_SARADC_SAR2_INV_S 10 -/** APB_SARADC_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (APB_SARADC_SAR2_INV_V << APB_SARADC_SAR2_INV_S) +#define APB_SARADC_SAR2_INV_V 0x00000001U +#define APB_SARADC_SAR2_INV_S 10 +/** APB_SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10; * to set saradc timer target */ -#define APB_SARADC_SARADC_TIMER_TARGET 0x00000FFFU -#define APB_SARADC_SARADC_TIMER_TARGET_M (APB_SARADC_SARADC_TIMER_TARGET_V << APB_SARADC_SARADC_TIMER_TARGET_S) -#define APB_SARADC_SARADC_TIMER_TARGET_V 0x00000FFFU -#define APB_SARADC_SARADC_TIMER_TARGET_S 12 -/** APB_SARADC_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; +#define APB_SARADC_TIMER_TARGET 0x00000FFFU +#define APB_SARADC_TIMER_TARGET_M (APB_SARADC_TIMER_TARGET_V << APB_SARADC_TIMER_TARGET_S) +#define APB_SARADC_TIMER_TARGET_V 0x00000FFFU +#define APB_SARADC_TIMER_TARGET_S 12 +/** APB_SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0; * to enable saradc timer trigger */ -#define APB_SARADC_SARADC_TIMER_EN (BIT(24)) -#define APB_SARADC_SARADC_TIMER_EN_M (APB_SARADC_SARADC_TIMER_EN_V << APB_SARADC_SARADC_TIMER_EN_S) -#define APB_SARADC_SARADC_TIMER_EN_V 0x00000001U -#define APB_SARADC_SARADC_TIMER_EN_S 24 +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (APB_SARADC_TIMER_EN_V << APB_SARADC_TIMER_EN_S) +#define APB_SARADC_TIMER_EN_V 0x00000001U +#define APB_SARADC_TIMER_EN_S 24 /** APB_SARADC_FILTER_CTRL1_REG register * register description */ -#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_BASE + 0x8) +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8) /** APB_SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0; * Need add description */ @@ -141,121 +141,121 @@ extern "C" { /** APB_SARADC_FSM_WAIT_REG register * register description */ -#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_BASE + 0xc) -/** APB_SARADC_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xc) +/** APB_SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8; * Need add description */ -#define APB_SARADC_SARADC_XPD_WAIT 0x000000FFU -#define APB_SARADC_SARADC_XPD_WAIT_M (APB_SARADC_SARADC_XPD_WAIT_V << APB_SARADC_SARADC_XPD_WAIT_S) -#define APB_SARADC_SARADC_XPD_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_XPD_WAIT_S 0 -/** APB_SARADC_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; +#define APB_SARADC_XPD_WAIT 0x000000FFU +#define APB_SARADC_XPD_WAIT_M (APB_SARADC_XPD_WAIT_V << APB_SARADC_XPD_WAIT_S) +#define APB_SARADC_XPD_WAIT_V 0x000000FFU +#define APB_SARADC_XPD_WAIT_S 0 +/** APB_SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8; * Need add description */ -#define APB_SARADC_SARADC_RSTB_WAIT 0x000000FFU -#define APB_SARADC_SARADC_RSTB_WAIT_M (APB_SARADC_SARADC_RSTB_WAIT_V << APB_SARADC_SARADC_RSTB_WAIT_S) -#define APB_SARADC_SARADC_RSTB_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_RSTB_WAIT_S 8 -/** APB_SARADC_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; +#define APB_SARADC_RSTB_WAIT 0x000000FFU +#define APB_SARADC_RSTB_WAIT_M (APB_SARADC_RSTB_WAIT_V << APB_SARADC_RSTB_WAIT_S) +#define APB_SARADC_RSTB_WAIT_V 0x000000FFU +#define APB_SARADC_RSTB_WAIT_S 8 +/** APB_SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255; * Need add description */ -#define APB_SARADC_SARADC_STANDBY_WAIT 0x000000FFU -#define APB_SARADC_SARADC_STANDBY_WAIT_M (APB_SARADC_SARADC_STANDBY_WAIT_V << APB_SARADC_SARADC_STANDBY_WAIT_S) -#define APB_SARADC_SARADC_STANDBY_WAIT_V 0x000000FFU -#define APB_SARADC_SARADC_STANDBY_WAIT_S 16 +#define APB_SARADC_STANDBY_WAIT 0x000000FFU +#define APB_SARADC_STANDBY_WAIT_M (APB_SARADC_STANDBY_WAIT_V << APB_SARADC_STANDBY_WAIT_S) +#define APB_SARADC_STANDBY_WAIT_V 0x000000FFU +#define APB_SARADC_STANDBY_WAIT_S 16 /** APB_SARADC_SAR1_STATUS_REG register * register description */ -#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_BASE + 0x10) -/** APB_SARADC_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 0; +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10) +/** APB_SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_SAR1_STATUS 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR1_STATUS_M (APB_SARADC_SARADC_SAR1_STATUS_V << APB_SARADC_SARADC_SAR1_STATUS_S) -#define APB_SARADC_SARADC_SAR1_STATUS_V 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR1_STATUS_S 0 +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFFU +#define APB_SARADC_SAR1_STATUS_M (APB_SARADC_SAR1_STATUS_V << APB_SARADC_SAR1_STATUS_S) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SAR1_STATUS_S 0 /** APB_SARADC_SAR2_STATUS_REG register * register description */ -#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_BASE + 0x14) -/** APB_SARADC_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 0; +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14) +/** APB_SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_SAR2_STATUS 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR2_STATUS_M (APB_SARADC_SARADC_SAR2_STATUS_V << APB_SARADC_SARADC_SAR2_STATUS_S) -#define APB_SARADC_SARADC_SAR2_STATUS_V 0xFFFFFFFFU -#define APB_SARADC_SARADC_SAR2_STATUS_S 0 +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFFU +#define APB_SARADC_SAR2_STATUS_M (APB_SARADC_SAR2_STATUS_V << APB_SARADC_SAR2_STATUS_S) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFFU +#define APB_SARADC_SAR2_STATUS_S 0 /** APB_SARADC_SAR_PATT_TAB1_REG register * register description */ -#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_BASE + 0x18) -/** APB_SARADC_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; +#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18) +/** APB_SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215; * item 0 ~ 3 for pattern table 1 (each item one byte) */ -#define APB_SARADC_SARADC_SAR_PATT_TAB1 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SARADC_SAR_PATT_TAB1_S) -#define APB_SARADC_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB1_S 0 +#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFFU +#define APB_SARADC_SAR_PATT_TAB1_M (APB_SARADC_SAR_PATT_TAB1_V << APB_SARADC_SAR_PATT_TAB1_S) +#define APB_SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU +#define APB_SARADC_SAR_PATT_TAB1_S 0 /** APB_SARADC_SAR_PATT_TAB2_REG register * register description */ -#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_BASE + 0x1c) -/** APB_SARADC_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; +#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1c) +/** APB_SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215; * Item 4 ~ 7 for pattern table 1 (each item one byte) */ -#define APB_SARADC_SARADC_SAR_PATT_TAB2 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SARADC_SAR_PATT_TAB2_S) -#define APB_SARADC_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU -#define APB_SARADC_SARADC_SAR_PATT_TAB2_S 0 +#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFFU +#define APB_SARADC_SAR_PATT_TAB2_M (APB_SARADC_SAR_PATT_TAB2_V << APB_SARADC_SAR_PATT_TAB2_S) +#define APB_SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU +#define APB_SARADC_SAR_PATT_TAB2_S 0 /** APB_SARADC_ONETIME_SAMPLE_REG register * register description */ -#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_BASE + 0x20) -/** APB_SARADC_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; +#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x20) +/** APB_SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_ONETIME_ATTEN 0x00000003U -#define APB_SARADC_SARADC_ONETIME_ATTEN_M (APB_SARADC_SARADC_ONETIME_ATTEN_V << APB_SARADC_SARADC_ONETIME_ATTEN_S) -#define APB_SARADC_SARADC_ONETIME_ATTEN_V 0x00000003U -#define APB_SARADC_SARADC_ONETIME_ATTEN_S 23 -/** APB_SARADC_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; +#define APB_SARADC_ONETIME_ATTEN 0x00000003U +#define APB_SARADC_ONETIME_ATTEN_M (APB_SARADC_ONETIME_ATTEN_V << APB_SARADC_ONETIME_ATTEN_S) +#define APB_SARADC_ONETIME_ATTEN_V 0x00000003U +#define APB_SARADC_ONETIME_ATTEN_S 23 +/** APB_SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13; * Need add description */ -#define APB_SARADC_SARADC_ONETIME_CHANNEL 0x0000000FU -#define APB_SARADC_SARADC_ONETIME_CHANNEL_M (APB_SARADC_SARADC_ONETIME_CHANNEL_V << APB_SARADC_SARADC_ONETIME_CHANNEL_S) -#define APB_SARADC_SARADC_ONETIME_CHANNEL_V 0x0000000FU -#define APB_SARADC_SARADC_ONETIME_CHANNEL_S 25 -/** APB_SARADC_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; +#define APB_SARADC_ONETIME_CHANNEL 0x0000000FU +#define APB_SARADC_ONETIME_CHANNEL_M (APB_SARADC_ONETIME_CHANNEL_V << APB_SARADC_ONETIME_CHANNEL_S) +#define APB_SARADC_ONETIME_CHANNEL_V 0x0000000FU +#define APB_SARADC_ONETIME_CHANNEL_S 25 +/** APB_SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0; * Need add description */ -#define APB_SARADC_SARADC_ONETIME_START (BIT(29)) -#define APB_SARADC_SARADC_ONETIME_START_M (APB_SARADC_SARADC_ONETIME_START_V << APB_SARADC_SARADC_ONETIME_START_S) -#define APB_SARADC_SARADC_ONETIME_START_V 0x00000001U -#define APB_SARADC_SARADC_ONETIME_START_S 29 -/** APB_SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; +#define APB_SARADC_ONETIME_START (BIT(29)) +#define APB_SARADC_ONETIME_START_M (APB_SARADC_ONETIME_START_V << APB_SARADC_ONETIME_START_S) +#define APB_SARADC_ONETIME_START_V 0x00000001U +#define APB_SARADC_ONETIME_START_S 29 +/** APB_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0; * Need add description */ -#define APB_SARADC_SARADC2_ONETIME_SAMPLE (BIT(30)) -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_M (APB_SARADC_SARADC2_ONETIME_SAMPLE_V << APB_SARADC_SARADC2_ONETIME_SAMPLE_S) -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U -#define APB_SARADC_SARADC2_ONETIME_SAMPLE_S 30 -/** APB_SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; +#define APB_SARADC2_ONETIME_SAMPLE (BIT(30)) +#define APB_SARADC2_ONETIME_SAMPLE_M (APB_SARADC2_ONETIME_SAMPLE_V << APB_SARADC2_ONETIME_SAMPLE_S) +#define APB_SARADC2_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC2_ONETIME_SAMPLE_S 30 +/** APB_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0; * Need add description */ -#define APB_SARADC_SARADC1_ONETIME_SAMPLE (BIT(31)) -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_M (APB_SARADC_SARADC1_ONETIME_SAMPLE_V << APB_SARADC_SARADC1_ONETIME_SAMPLE_S) -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U -#define APB_SARADC_SARADC1_ONETIME_SAMPLE_S 31 +#define APB_SARADC1_ONETIME_SAMPLE (BIT(31)) +#define APB_SARADC1_ONETIME_SAMPLE_M (APB_SARADC1_ONETIME_SAMPLE_V << APB_SARADC1_ONETIME_SAMPLE_S) +#define APB_SARADC1_ONETIME_SAMPLE_V 0x00000001U +#define APB_SARADC1_ONETIME_SAMPLE_S 31 /** APB_SARADC_APB_ADC_ARB_CTRL_REG register * register description */ -#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_BASE + 0x24) +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x24) /** APB_SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0; * adc2 arbiter force to enableapb controller */ @@ -316,7 +316,7 @@ extern "C" { /** APB_SARADC_FILTER_CTRL0_REG register * register description */ -#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_BASE + 0x28) +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x28) /** APB_SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13; * Need add description */ @@ -342,7 +342,7 @@ extern "C" { /** APB_SARADC1_DATA_STATUS_REG register * register description */ -#define APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_BASE + 0x2c) +#define APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x2c) /** APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0; * Need add description */ @@ -354,7 +354,7 @@ extern "C" { /** APB_SARADC2_DATA_STATUS_REG register * register description */ -#define APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_BASE + 0x30) +#define APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x30) /** APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0; * Need add description */ @@ -366,7 +366,7 @@ extern "C" { /** APB_SARADC_THRES0_CTRL_REG register * register description */ -#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_BASE + 0x34) +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x34) /** APB_SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13; * Need add description */ @@ -392,7 +392,7 @@ extern "C" { /** APB_SARADC_THRES1_CTRL_REG register * register description */ -#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_BASE + 0x38) +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38) /** APB_SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13; * Need add description */ @@ -418,7 +418,7 @@ extern "C" { /** APB_SARADC_THRES_CTRL_REG register * register description */ -#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_BASE + 0x3c) +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x3c) /** APB_SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0; * Need add description */ @@ -458,7 +458,7 @@ extern "C" { /** APB_SARADC_INT_ENA_REG register * register description */ -#define APB_SARADC_INT_ENA_REG (DR_REG_APB_BASE + 0x40) +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x40) /** APB_SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0; * Need add description */ @@ -505,7 +505,7 @@ extern "C" { /** APB_SARADC_INT_RAW_REG register * register description */ -#define APB_SARADC_INT_RAW_REG (DR_REG_APB_BASE + 0x44) +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x44) /** APB_SARADC_THRES1_LOW_INT_RAW : RO; bitpos: [26]; default: 0; * Need add description */ @@ -552,7 +552,7 @@ extern "C" { /** APB_SARADC_INT_ST_REG register * register description */ -#define APB_SARADC_INT_ST_REG (DR_REG_APB_BASE + 0x48) +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x48) /** APB_SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0; * Need add description */ @@ -599,7 +599,7 @@ extern "C" { /** APB_SARADC_INT_CLR_REG register * register description */ -#define APB_SARADC_INT_CLR_REG (DR_REG_APB_BASE + 0x4c) +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x4c) /** APB_SARADC_THRES1_LOW_INT_CLR : WO; bitpos: [26]; default: 0; * Need add description */ @@ -646,7 +646,7 @@ extern "C" { /** APB_SARADC_DMA_CONF_REG register * register description */ -#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_BASE + 0x50) +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x50) /** APB_SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255; * the dma_in_suc_eof gen when sample cnt = spi_eof_num */ @@ -672,7 +672,7 @@ extern "C" { /** APB_SARADC_APB_ADC_CLKM_CONF_REG register * register description */ -#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_BASE + 0x54) +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x54) /** APB_SARADC_REG_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; * Integral I2S clock divider value */ @@ -712,7 +712,7 @@ extern "C" { /** APB_SARADC_APB_TSENS_CTRL_REG register * register description */ -#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_BASE + 0x58) +#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58) /** APB_SARADC_REG_TSENS_OUT : RO; bitpos: [7:0]; default: 0; * Need add description */ @@ -745,7 +745,7 @@ extern "C" { /** APB_SARADC_APB_TSENS_CTRL2_REG register * register description */ -#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_BASE + 0x5c) +#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x5c) /** APB_SARADC_REG_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2; * Need add description */ @@ -778,7 +778,7 @@ extern "C" { /** APB_SARADC_CALI_REG register * register description */ -#define APB_SARADC_CALI_REG (DR_REG_APB_BASE + 0x60) +#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x60) /** APB_SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768; * Need add description */ @@ -790,7 +790,7 @@ extern "C" { /** APB_SARADC_APB_CTRL_DATE_REG register * register description */ -#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_BASE + 0x3fc) +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc) /** APB_SARADC_DATE : R/W; bitpos: [31:0]; default: 34632208; * Need add description */