kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/rtc_slowclk_extra_options' into 'master'
Add more RTC_SLOW_CLK options See merge request idf/esp-idf!2984pull/2261/merge
commit
88d40e01b4
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@ -687,18 +687,39 @@ choice ESP32_RTC_CLOCK_SOURCE
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default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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default ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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help
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help
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Choose which clock is used as RTC clock source.
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Choose which clock is used as RTC clock source.
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- "Internal 150kHz oscillator" option provides lowest deep sleep current
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consumption, and does not require extra external components. However
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frequency stability with respect to temperature is poor, so time may
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drift in deep/light sleep modes.
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- "External 32kHz crystal" provides better frequency stability, at the
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expense of slightly higher (1uA) deep sleep current consumption.
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- "External 32kHz oscillator" allows using 32kHz clock generated by an
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external circuit. In this case, external clock signal must be connected
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to 32K_XP pin. Amplitude should be <1.2V in case of sine wave signal,
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and <1V in case of square wave signal. Common mode voltage should be
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0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
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Additionally, 1nF capacitor must be connected between 32K_XN pin and
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ground. 32K_XN pin can not be used as a GPIO in this case.
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- "Internal 8.5MHz oscillator divided by 256" option results in higher
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deep sleep current (by 5uA) but has better frequency stability than
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the internal 150kHz oscillator. It does not require external components.
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config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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config ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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bool "Internal 150kHz RC oscillator"
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bool "Internal 150kHz RC oscillator"
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config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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bool "External 32kHz crystal"
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bool "External 32kHz crystal"
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config ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC
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bool "External 32kHz oscillator at 32K_XP pin"
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config ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256
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bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)"
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endchoice
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endchoice
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config ESP32_RTC_CLK_CAL_CYCLES
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config ESP32_RTC_CLK_CAL_CYCLES
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int "Number of cycles for RTC_SLOW_CLK calibration"
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int "Number of cycles for RTC_SLOW_CLK calibration"
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default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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default 3000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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default 1024 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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default 1024 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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range 0 27000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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range 0 27000 if ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL || ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC || ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256
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range 0 32766 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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range 0 32766 if ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC
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help
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help
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When the startup code initializes RTC_SLOW_CLK, it can perform
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When the startup code initializes RTC_SLOW_CLK, it can perform
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@ -40,7 +40,23 @@
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#define MHZ (1000000)
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#define MHZ (1000000)
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
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/* Indicates that this 32k oscillator gets input from external oscillator, rather
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* than a crystal.
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*/
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#define EXT_OSC_FLAG BIT(3)
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/* This is almost the same as rtc_slow_freq_t, except that we define
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* an extra enum member for the external 32k oscillator.
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* For convenience, lower 2 bits should correspond to rtc_slow_freq_t values.
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*/
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typedef enum {
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SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, //!< Internal 150 kHz RC oscillator
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SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, //!< External 32 kHz XTAL
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SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, //!< Internal 8 MHz RC oscillator, divided by 256
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SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG //!< External 32k oscillator connected to 32K_XP pin
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} slow_clk_sel_t;
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
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// g_ticks_us defined in ROMs for PRO and APP CPU
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// g_ticks_us defined in ROMs for PRO and APP CPU
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extern uint32_t g_ticks_per_us_pro;
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extern uint32_t g_ticks_per_us_pro;
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@ -71,8 +87,12 @@ void esp_clk_init(void)
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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#if defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL)
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select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
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#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC)
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select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
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#elif defined(CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256)
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select_rtc_slow_clk(SLOW_CLK_8MD256);
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#else
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#else
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select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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#endif
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#endif
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@ -117,16 +137,12 @@ void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
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g_ticks_per_us_app = ticks_per_us;
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g_ticks_per_us_app = ticks_per_us;
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}
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}
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
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static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
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{
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{
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rtc_slow_freq_t rtc_slow_freq = slow_clk & RTC_CNTL_ANA_CLK_RTC_SEL_V;
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uint32_t cal_val = 0;
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uint32_t cal_val = 0;
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uint32_t wait = 0;
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uint32_t freq_hz = ((slow_clk == RTC_SLOW_FREQ_32K_XTAL) ? 32768 : 150000);
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uint32_t warning_timeout = 3 /* sec */ * freq_hz /* Hz */ / (SLOW_CLK_CAL_CYCLES + 1);
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warning_timeout = ((warning_timeout == 0) ? 3 /* sec */ : warning_timeout);
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bool changing_clock_to_150k = false;
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do {
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do {
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if (slow_clk == RTC_SLOW_FREQ_32K_XTAL) {
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if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
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/* 32k XTAL oscillator needs to be enabled and running before it can
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/* 32k XTAL oscillator needs to be enabled and running before it can
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* be used. Hardware doesn't have a direct way of checking if the
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* be used. Hardware doesn't have a direct way of checking if the
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* oscillator is running. Here we use rtc_clk_cal function to count
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* oscillator is running. Here we use rtc_clk_cal function to count
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@ -135,25 +151,23 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
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* will time out, returning 0.
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* will time out, returning 0.
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*/
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*/
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up");
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rtc_clk_32k_enable(true);
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if (slow_clk == SLOW_CLK_32K_XTAL) {
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rtc_clk_32k_enable(true);
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} else if (slow_clk == SLOW_CLK_32K_EXT_OSC) {
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rtc_clk_32k_enable_external();
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}
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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// When SLOW_CLK_CAL_CYCLES is set to 0, clock calibration will not be performed at startup.
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
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cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, SLOW_CLK_CAL_CYCLES);
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if (cal_val == 0 || cal_val < 15000000L) {
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if (cal_val == 0 || cal_val < 15000000L) {
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ESP_EARLY_LOGE(TAG, "RTC: Not found External 32 kHz XTAL. Switching to Internal 150 kHz RC chain");
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ESP_EARLY_LOGW(TAG, "32 kHz XTAL not found, switching to internal 150 kHz oscillator");
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slow_clk = RTC_SLOW_FREQ_RTC;
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rtc_slow_freq = RTC_SLOW_FREQ_RTC;
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changing_clock_to_150k = true;
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}
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}
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}
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}
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} else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) {
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rtc_clk_8m_enable(true, true);
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}
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}
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rtc_clk_slow_freq_set(slow_clk);
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rtc_clk_slow_freq_set(rtc_slow_freq);
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if (changing_clock_to_150k == true && wait > 1){
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// This helps when there are errors when switching the clock from External 32 kHz XTAL to Internal 150 kHz RC chain.
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rtc_clk_32k_enable(false);
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uint32_t min_bootstrap = 5; // Min bootstrapping for continue switching the clock.
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rtc_clk_32k_bootstrap(min_bootstrap);
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rtc_clk_32k_enable(true);
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}
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if (SLOW_CLK_CAL_CYCLES > 0) {
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if (SLOW_CLK_CAL_CYCLES > 0) {
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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/* TODO: 32k XTAL oscillator has some frequency drift at startup.
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@ -164,9 +178,6 @@ static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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}
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}
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if (++wait % warning_timeout == 0) {
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ESP_EARLY_LOGW(TAG, "still waiting for source selection RTC");
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}
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} while (cal_val == 0);
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} while (cal_val == 0);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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esp_clk_slowclk_cal_set(cal_val);
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@ -193,6 +193,11 @@ void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
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*/
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*/
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void rtc_clk_32k_enable(bool en);
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void rtc_clk_32k_enable(bool en);
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/**
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* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
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*/
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void rtc_clk_32k_enable_external();
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/**
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/**
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* @brief Get the state of 32k XTAL oscillator
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* @brief Get the state of 32k XTAL oscillator
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* @return true if 32k XTAL oscillator has been enabled
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* @return true if 32k XTAL oscillator has been enabled
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@ -62,6 +62,10 @@
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#define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
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#define XTAL_32K_BOOTSTRAP_DBIAS_VAL 0
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#define XTAL_32K_BOOTSTRAP_TIME_US 7
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#define XTAL_32K_BOOTSTRAP_TIME_US 7
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#define XTAL_32K_EXT_DAC_VAL 2
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#define XTAL_32K_EXT_DRES_VAL 3
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#define XTAL_32K_EXT_DBIAS_VAL 1
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/* Delays for various clock sources to be enabled/switched.
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/* Delays for various clock sources to be enabled/switched.
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* All values are in microseconds.
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* All values are in microseconds.
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* TODO: some of these are excessive, and should be reduced.
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* TODO: some of these are excessive, and should be reduced.
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@ -98,7 +102,7 @@ static bool rtc_clk_cpu_freq_from_mhz_internal(int mhz, rtc_cpu_freq_t* out_val)
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// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
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// Current PLL frequency, in MHZ (320 or 480). Zero if PLL is not enabled.
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static int s_cur_pll_freq;
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static int s_cur_pll_freq;
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static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
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static void rtc_clk_32k_enable_common(int dac, int dres, int dbias)
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{
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{
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG,
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@ -113,12 +117,17 @@ static void rtc_clk_32k_enable_internal(int dac, int dres, int dbias)
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void rtc_clk_32k_enable(bool enable)
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void rtc_clk_32k_enable(bool enable)
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{
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{
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if (enable) {
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if (enable) {
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rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
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rtc_clk_32k_enable_common(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DBIAS_VAL);
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} else {
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} else {
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K);
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}
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}
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}
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}
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void rtc_clk_32k_enable_external()
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{
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rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
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}
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/* Helping external 32kHz crystal to start up.
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/* Helping external 32kHz crystal to start up.
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* External crystal connected to outputs GPIO32 GPIO33.
|
* External crystal connected to outputs GPIO32 GPIO33.
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* Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
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* Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
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@ -150,7 +159,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
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SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32N_RDE);
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ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
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ets_delay_us(XTAL_32K_BOOTSTRAP_TIME_US);
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rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL,
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rtc_clk_32k_enable_common(XTAL_32K_BOOTSTRAP_DAC_VAL,
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XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
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XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
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}
|
}
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@ -197,6 +197,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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|
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REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
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REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
|
||||||
|
|
||||||
|
if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == RTC_SLOW_FREQ_8MD256) {
|
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|
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
|
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|
} else {
|
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|
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
|
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|
}
|
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|
|
||||||
/* enable VDDSDIO control by state machine */
|
/* enable VDDSDIO control by state machine */
|
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REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
|
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
|
||||||
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
|
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
|
||||||
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