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rtc_clk: Fix rtc8m calibration failure after cpu/core reset 

Explicitly guarantee 8md256 clk is enabled before calibration
pull/10244/head
Song Ruo Jing 2022-10-12 12:33:47 +08:00
rodzic 9269a536ac
commit 883e54aa71
4 zmienionych plików z 16 dodań i 0 usunięć
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4
components/esp_hw_support/port/esp32/rtc_time.c
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@ -41,7 +41,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* Prepare calibration */
@ -92,6 +95,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
if (timeout_us == 0) {
/* timed out waiting for calibration */

4
components/esp_hw_support/port/esp32c3/rtc_time.c
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@ -54,7 +54,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* There may be another calibration process already running during we call this function,
@ -112,6 +115,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;

4
components/esp_hw_support/port/esp32s2/rtc_time.c
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@ -156,7 +156,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
@ -173,6 +176,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;

4
components/esp_hw_support/port/esp32s3/rtc_time.c
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@ -52,7 +52,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
}
bool clk8m_enabled = rtc_clk_8m_enabled();
bool clk8md256_enabled = rtc_clk_8md256_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
}
/* There may be another calibration process already running during we call this function,
@ -110,6 +113,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
rtc_clk_8m_enable(clk8m_enabled, clk8md256_enabled);
}
return cal_val;