diff --git a/components/bootloader/src/main/flash_qio_mode.c b/components/bootloader/src/main/flash_qio_mode.c
index 4b2ec30883..55c618654b 100644
--- a/components/bootloader/src/main/flash_qio_mode.c
+++ b/components/bootloader/src/main/flash_qio_mode.c
@@ -180,7 +180,8 @@ static void enable_qio_mode(read_status_fn_t read_status_fn,
 #else
     mode = ESP_ROM_SPIFLASH_QIO_MODE;
 #endif
-    esp_rom_spiflash_master_config_readmode(mode);
+    esp_rom_spiflash_config_readmode(mode);
+
 }
 
 static unsigned read_status_8b_rdsr()
diff --git a/components/esp32/include/rom/spi_flash.h b/components/esp32/include/rom/spi_flash.h
index bb2da748ba..97efccc368 100644
--- a/components/esp32/include/rom/spi_flash.h
+++ b/components/esp32/include/rom/spi_flash.h
@@ -279,25 +279,13 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8
   *
   * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
   *
-  * @param  uint8_t legacy: In legacy mode, more SPI command is used in line.
+  * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
   *
   * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
   *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
   *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
   */
-esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode, bool legacy);
-
-/**
-  * @brief Config SPI Flash read mode when Flash is running in some mode.
-  *        Please do not call this function in SDK.
-  *
-  * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
-  *
-  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
-  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
-  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
-  */
-esp_rom_spiflash_result_t esp_rom_spiflash_master_config_readmode(esp_rom_spiflash_read_mode_t mode);
+esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
 
 /**
   * @brief Config SPI Flash clock divisor.
diff --git a/components/esp32/ld/esp32.rom.spiflash.ld b/components/esp32/ld/esp32.rom.spiflash.ld
index 64af6a4b9e..709b358114 100644
--- a/components/esp32/ld/esp32.rom.spiflash.ld
+++ b/components/esp32/ld/esp32.rom.spiflash.ld
@@ -10,7 +10,7 @@ PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
 PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
 PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
 PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
-PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062944 );
+PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 ); /* SPIMasterReadModeCnfig */
 PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
 PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
 PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );
diff --git a/components/spi_flash/spi_flash_rom_patch.c b/components/spi_flash/spi_flash_rom_patch.c
index 0664c74829..ec59a1ff19 100644
--- a/components/spi_flash/spi_flash_rom_patch.c
+++ b/components/spi_flash/spi_flash_rom_patch.c
@@ -87,9 +87,6 @@ extern uint8_t g_rom_spiflash_dummy_len_plus[];
 
 
 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
-static esp_rom_spiflash_result_t esp_rom_spiflash_enable_qmode(esp_rom_spiflash_chip_t *spi);
-static esp_rom_spiflash_result_t esp_rom_spiflash_disable_qmode(esp_rom_spiflash_chip_t *spi);
-
 
 //only support spi1
 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi)
@@ -309,65 +306,6 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_
     return ESP_ROM_SPIFLASH_RESULT_OK;
 }
 
-static esp_rom_spiflash_result_t esp_rom_spiflash_enable_qmode(esp_rom_spiflash_chip_t *spi)
-{
-    uint32_t flash_status;
-    uint32_t status;
-    //read QE bit, not write if QE
-    if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(spi, &status)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-    if (status & ESP_ROM_SPIFLASH_QE) {
-        return ESP_ROM_SPIFLASH_RESULT_OK;
-    }
-
-    //enable 2 byte status writing
-    SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
-
-    if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-
-    esp_rom_spiflash_read_status(spi, &flash_status);
-
-    if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(spi, flash_status | ESP_ROM_SPIFLASH_QE)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-
-    return ESP_ROM_SPIFLASH_RESULT_OK;
-}
-
-static esp_rom_spiflash_result_t esp_rom_spiflash_disable_qmode(esp_rom_spiflash_chip_t *spi)
-{
-    uint32_t flash_status;
-    uint32_t status;
-
-    //read QE bit, not write if not QE
-    if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(spi, &status)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-    //ets_printf("status %08x, line:%u\n", status, __LINE__);
-
-    if (!(status & ESP_ROM_SPIFLASH_QE)) {
-        return ESP_ROM_SPIFLASH_RESULT_OK;
-    }
-
-    //enable 2 byte status writing
-    SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
-
-    if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-
-    esp_rom_spiflash_read_status(spi, &flash_status);
-    //keep low 8 bit
-    if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(spi, flash_status & 0xff)) {
-        return ESP_ROM_SPIFLASH_RESULT_ERR;
-    }
-
-    return ESP_ROM_SPIFLASH_RESULT_OK;
-}
-
 static void spi_cache_mode_switch(uint32_t  modebit)
 {
     if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
@@ -431,7 +369,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock()
 }
 
 
-esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode, bool legacy)
+esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)
 {
     uint32_t  modebit;
 
@@ -453,15 +391,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
     default : modebit = 0;
     }
 
-    if ((ESP_ROM_SPIFLASH_QIO_MODE == mode) || (ESP_ROM_SPIFLASH_QOUT_MODE == mode)) {
-        esp_rom_spiflash_enable_qmode(&g_rom_spiflash_chip);
-    } else {
-        //do not need disable QMode in faster boot
-        if (legacy) {
-            esp_rom_spiflash_disable_qmode(&g_rom_spiflash_chip);
-        }
-    }
-
     SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit);
     SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit);
     spi_cache_mode_switch(modebit);
@@ -668,7 +597,10 @@ esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint3
     uint32_t sector_num_per_block;
 
     //set read mode to Fastmode ,not QDIO mode for erase
-    esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE, true);
+    //
+    // TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this
+    // function is not used in IDF.
+    esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE);
 
     //check if area is oversize of flash
     if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) {