kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feat/c6lite_c61_introduce_step2_soc' into 'master'
feat(esp32c61): add soc peripheral header files (stage 2/8, part 1/2) See merge request espressif/esp-idf!29353pull/13338/head
Wan Lei
commit
84f27d65f6
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/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SARADC_CTRL_REG register
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* digital saradc configure register
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*/
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#define SARADC_CTRL_REG (DR_REG_SARADC_BASE + 0x0)
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/** SARADC_START_FORCE : R/W; bitpos: [0]; default: 0;
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* select software enable saradc sample
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*/
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#define SARADC_START_FORCE (BIT(0))
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#define SARADC_START_FORCE_M (SARADC_START_FORCE_V << SARADC_START_FORCE_S)
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#define SARADC_START_FORCE_V 0x00000001U
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#define SARADC_START_FORCE_S 0
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/** SARADC_START : R/W; bitpos: [1]; default: 0;
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* software enable saradc sample
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*/
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#define SARADC_START (BIT(1))
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#define SARADC_START_M (SARADC_START_V << SARADC_START_S)
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#define SARADC_START_V 0x00000001U
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#define SARADC_START_S 1
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/** SARADC_SAR_CLK_GATED : R/W; bitpos: [6]; default: 1;
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* SAR clock gated
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*/
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#define SARADC_SAR_CLK_GATED (BIT(6))
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#define SARADC_SAR_CLK_GATED_M (SARADC_SAR_CLK_GATED_V << SARADC_SAR_CLK_GATED_S)
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#define SARADC_SAR_CLK_GATED_V 0x00000001U
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#define SARADC_SAR_CLK_GATED_S 6
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/** SARADC_SAR_CLK_DIV : R/W; bitpos: [14:7]; default: 4;
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* SAR clock divider
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*/
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#define SARADC_SAR_CLK_DIV 0x000000FFU
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#define SARADC_SAR_CLK_DIV_M (SARADC_SAR_CLK_DIV_V << SARADC_SAR_CLK_DIV_S)
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#define SARADC_SAR_CLK_DIV_V 0x000000FFU
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#define SARADC_SAR_CLK_DIV_S 7
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/** SARADC_SAR_PATT_LEN : R/W; bitpos: [17:15]; default: 7;
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* 0 ~ 15 means length 1 ~ 16
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*/
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#define SARADC_SAR_PATT_LEN 0x00000007U
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#define SARADC_SAR_PATT_LEN_M (SARADC_SAR_PATT_LEN_V << SARADC_SAR_PATT_LEN_S)
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#define SARADC_SAR_PATT_LEN_V 0x00000007U
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#define SARADC_SAR_PATT_LEN_S 15
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/** SARADC_SAR_PATT_P_CLEAR : R/W; bitpos: [23]; default: 0;
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* clear the pointer of pattern table for DIG ADC1 CTRL
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*/
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#define SARADC_SAR_PATT_P_CLEAR (BIT(23))
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#define SARADC_SAR_PATT_P_CLEAR_M (SARADC_SAR_PATT_P_CLEAR_V << SARADC_SAR_PATT_P_CLEAR_S)
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#define SARADC_SAR_PATT_P_CLEAR_V 0x00000001U
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#define SARADC_SAR_PATT_P_CLEAR_S 23
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/** SARADC_XPD_SAR_FORCE : R/W; bitpos: [28:27]; default: 0;
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* force option to xpd sar blocks
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*/
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#define SARADC_XPD_SAR_FORCE 0x00000003U
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#define SARADC_XPD_SAR_FORCE_M (SARADC_XPD_SAR_FORCE_V << SARADC_XPD_SAR_FORCE_S)
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#define SARADC_XPD_SAR_FORCE_V 0x00000003U
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#define SARADC_XPD_SAR_FORCE_S 27
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/** SARADC_SARADC2_PWDET_DRV : R/W; bitpos: [29]; default: 0;
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* enable saradc2 power detect driven func.
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*/
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#define SARADC_SARADC2_PWDET_DRV (BIT(29))
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#define SARADC_SARADC2_PWDET_DRV_M (SARADC_SARADC2_PWDET_DRV_V << SARADC_SARADC2_PWDET_DRV_S)
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#define SARADC_SARADC2_PWDET_DRV_V 0x00000001U
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#define SARADC_SARADC2_PWDET_DRV_S 29
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/** SARADC_WAIT_ARB_CYCLE : R/W; bitpos: [31:30]; default: 1;
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* wait arbit signal stable after sar_done
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*/
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#define SARADC_WAIT_ARB_CYCLE 0x00000003U
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#define SARADC_WAIT_ARB_CYCLE_M (SARADC_WAIT_ARB_CYCLE_V << SARADC_WAIT_ARB_CYCLE_S)
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#define SARADC_WAIT_ARB_CYCLE_V 0x00000003U
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#define SARADC_WAIT_ARB_CYCLE_S 30
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/** SARADC_CTRL2_REG register
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* digital saradc configure register
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*/
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#define SARADC_CTRL2_REG (DR_REG_SARADC_BASE + 0x4)
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/** SARADC_MEAS_NUM_LIMIT : R/W; bitpos: [0]; default: 0;
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* enable max meas num
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*/
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#define SARADC_MEAS_NUM_LIMIT (BIT(0))
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#define SARADC_MEAS_NUM_LIMIT_M (SARADC_MEAS_NUM_LIMIT_V << SARADC_MEAS_NUM_LIMIT_S)
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#define SARADC_MEAS_NUM_LIMIT_V 0x00000001U
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#define SARADC_MEAS_NUM_LIMIT_S 0
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/** SARADC_MAX_MEAS_NUM : R/W; bitpos: [8:1]; default: 255;
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* max conversion number
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*/
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#define SARADC_MAX_MEAS_NUM 0x000000FFU
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#define SARADC_MAX_MEAS_NUM_M (SARADC_MAX_MEAS_NUM_V << SARADC_MAX_MEAS_NUM_S)
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#define SARADC_MAX_MEAS_NUM_V 0x000000FFU
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#define SARADC_MAX_MEAS_NUM_S 1
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/** SARADC_SAR1_INV : R/W; bitpos: [9]; default: 0;
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* 1: data to DIG ADC1 CTRL is inverted, otherwise not
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*/
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#define SARADC_SAR1_INV (BIT(9))
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#define SARADC_SAR1_INV_M (SARADC_SAR1_INV_V << SARADC_SAR1_INV_S)
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#define SARADC_SAR1_INV_V 0x00000001U
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#define SARADC_SAR1_INV_S 9
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/** SARADC_SAR2_INV : R/W; bitpos: [10]; default: 0;
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* 1: data to DIG ADC2 CTRL is inverted, otherwise not
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*/
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#define SARADC_SAR2_INV (BIT(10))
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#define SARADC_SAR2_INV_M (SARADC_SAR2_INV_V << SARADC_SAR2_INV_S)
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#define SARADC_SAR2_INV_V 0x00000001U
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#define SARADC_SAR2_INV_S 10
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/** SARADC_TIMER_TARGET : R/W; bitpos: [23:12]; default: 10;
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* to set saradc timer target
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*/
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#define SARADC_TIMER_TARGET 0x00000FFFU
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#define SARADC_TIMER_TARGET_M (SARADC_TIMER_TARGET_V << SARADC_TIMER_TARGET_S)
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#define SARADC_TIMER_TARGET_V 0x00000FFFU
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#define SARADC_TIMER_TARGET_S 12
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/** SARADC_TIMER_EN : R/W; bitpos: [24]; default: 0;
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* to enable saradc timer trigger
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*/
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#define SARADC_TIMER_EN (BIT(24))
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#define SARADC_TIMER_EN_M (SARADC_TIMER_EN_V << SARADC_TIMER_EN_S)
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#define SARADC_TIMER_EN_V 0x00000001U
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#define SARADC_TIMER_EN_S 24
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/** SARADC_FILTER_CTRL1_REG register
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* digital saradc configure register
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*/
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#define SARADC_FILTER_CTRL1_REG (DR_REG_SARADC_BASE + 0x8)
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/** SARADC_FILTER_FACTOR1 : R/W; bitpos: [28:26]; default: 0;
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* Factor of saradc filter1
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*/
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#define SARADC_FILTER_FACTOR1 0x00000007U
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#define SARADC_FILTER_FACTOR1_M (SARADC_FILTER_FACTOR1_V << SARADC_FILTER_FACTOR1_S)
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#define SARADC_FILTER_FACTOR1_V 0x00000007U
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#define SARADC_FILTER_FACTOR1_S 26
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/** SARADC_FILTER_FACTOR0 : R/W; bitpos: [31:29]; default: 0;
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* Factor of saradc filter0
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*/
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#define SARADC_FILTER_FACTOR0 0x00000007U
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#define SARADC_FILTER_FACTOR0_M (SARADC_FILTER_FACTOR0_V << SARADC_FILTER_FACTOR0_S)
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#define SARADC_FILTER_FACTOR0_V 0x00000007U
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#define SARADC_FILTER_FACTOR0_S 29
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/** SARADC_FSM_WAIT_REG register
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* digital saradc configure register
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*/
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#define SARADC_FSM_WAIT_REG (DR_REG_SARADC_BASE + 0xc)
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/** SARADC_XPD_WAIT : R/W; bitpos: [7:0]; default: 8;
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* saradc_xpd_wait
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*/
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#define SARADC_XPD_WAIT 0x000000FFU
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#define SARADC_XPD_WAIT_M (SARADC_XPD_WAIT_V << SARADC_XPD_WAIT_S)
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#define SARADC_XPD_WAIT_V 0x000000FFU
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#define SARADC_XPD_WAIT_S 0
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/** SARADC_RSTB_WAIT : R/W; bitpos: [15:8]; default: 8;
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* saradc_rstb_wait
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*/
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#define SARADC_RSTB_WAIT 0x000000FFU
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#define SARADC_RSTB_WAIT_M (SARADC_RSTB_WAIT_V << SARADC_RSTB_WAIT_S)
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#define SARADC_RSTB_WAIT_V 0x000000FFU
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#define SARADC_RSTB_WAIT_S 8
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/** SARADC_STANDBY_WAIT : R/W; bitpos: [23:16]; default: 255;
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* saradc_standby_wait
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*/
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#define SARADC_STANDBY_WAIT 0x000000FFU
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#define SARADC_STANDBY_WAIT_M (SARADC_STANDBY_WAIT_V << SARADC_STANDBY_WAIT_S)
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#define SARADC_STANDBY_WAIT_V 0x000000FFU
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#define SARADC_STANDBY_WAIT_S 16
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/** SARADC_SAR1_STATUS_REG register
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* digital saradc configure register
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*/
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#define SARADC_SAR1_STATUS_REG (DR_REG_SARADC_BASE + 0x10)
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/** SARADC_SAR1_STATUS : RO; bitpos: [31:0]; default: 536870912;
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* saradc1 status about data and channel
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*/
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#define SARADC_SAR1_STATUS 0xFFFFFFFFU
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#define SARADC_SAR1_STATUS_M (SARADC_SAR1_STATUS_V << SARADC_SAR1_STATUS_S)
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#define SARADC_SAR1_STATUS_V 0xFFFFFFFFU
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#define SARADC_SAR1_STATUS_S 0
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/** SARADC_SAR2_STATUS_REG register
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* digital saradc configure register
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*/
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#define SARADC_SAR2_STATUS_REG (DR_REG_SARADC_BASE + 0x14)
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/** SARADC_SAR2_STATUS : RO; bitpos: [31:0]; default: 536870912;
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* saradc2 status about data and channel
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*/
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#define SARADC_SAR2_STATUS 0xFFFFFFFFU
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#define SARADC_SAR2_STATUS_M (SARADC_SAR2_STATUS_V << SARADC_SAR2_STATUS_S)
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#define SARADC_SAR2_STATUS_V 0xFFFFFFFFU
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#define SARADC_SAR2_STATUS_S 0
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/** SARADC_SAR_PATT_TAB1_REG register
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* digital saradc configure register
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*/
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#define SARADC_SAR_PATT_TAB1_REG (DR_REG_SARADC_BASE + 0x18)
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/** SARADC_SAR_PATT_TAB1 : R/W; bitpos: [23:0]; default: 16777215;
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* item 0 ~ 3 for pattern table 1 (each item one byte)
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*/
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#define SARADC_SAR_PATT_TAB1 0x00FFFFFFU
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#define SARADC_SAR_PATT_TAB1_M (SARADC_SAR_PATT_TAB1_V << SARADC_SAR_PATT_TAB1_S)
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#define SARADC_SAR_PATT_TAB1_V 0x00FFFFFFU
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#define SARADC_SAR_PATT_TAB1_S 0
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/** SARADC_SAR_PATT_TAB2_REG register
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* digital saradc configure register
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*/
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#define SARADC_SAR_PATT_TAB2_REG (DR_REG_SARADC_BASE + 0x1c)
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/** SARADC_SAR_PATT_TAB2 : R/W; bitpos: [23:0]; default: 16777215;
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* Item 4 ~ 7 for pattern table 1 (each item one byte)
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*/
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#define SARADC_SAR_PATT_TAB2 0x00FFFFFFU
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#define SARADC_SAR_PATT_TAB2_M (SARADC_SAR_PATT_TAB2_V << SARADC_SAR_PATT_TAB2_S)
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#define SARADC_SAR_PATT_TAB2_V 0x00FFFFFFU
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#define SARADC_SAR_PATT_TAB2_S 0
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/** SARADC_ONETIME_SAMPLE_REG register
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* digital saradc configure register
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*/
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#define SARADC_ONETIME_SAMPLE_REG (DR_REG_SARADC_BASE + 0x20)
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/** SARADC_ONETIME_ATTEN : R/W; bitpos: [24:23]; default: 0;
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* configure onetime atten
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*/
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#define SARADC_ONETIME_ATTEN 0x00000003U
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#define SARADC_ONETIME_ATTEN_M (SARADC_ONETIME_ATTEN_V << SARADC_ONETIME_ATTEN_S)
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#define SARADC_ONETIME_ATTEN_V 0x00000003U
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#define SARADC_ONETIME_ATTEN_S 23
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/** SARADC_ONETIME_CHANNEL : R/W; bitpos: [28:25]; default: 13;
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* configure onetime channel
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*/
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#define SARADC_ONETIME_CHANNEL 0x0000000FU
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#define SARADC_ONETIME_CHANNEL_M (SARADC_ONETIME_CHANNEL_V << SARADC_ONETIME_CHANNEL_S)
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#define SARADC_ONETIME_CHANNEL_V 0x0000000FU
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#define SARADC_ONETIME_CHANNEL_S 25
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/** SARADC_ONETIME_START : R/W; bitpos: [29]; default: 0;
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* trigger adc onetime sample
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*/
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#define SARADC_ONETIME_START (BIT(29))
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#define SARADC_ONETIME_START_M (SARADC_ONETIME_START_V << SARADC_ONETIME_START_S)
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#define SARADC_ONETIME_START_V 0x00000001U
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#define SARADC_ONETIME_START_S 29
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/** SARADC_SARADC2_ONETIME_SAMPLE : R/W; bitpos: [30]; default: 0;
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* enable adc2 onetime sample
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*/
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#define SARADC_SARADC2_ONETIME_SAMPLE (BIT(30))
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#define SARADC_SARADC2_ONETIME_SAMPLE_M (SARADC_SARADC2_ONETIME_SAMPLE_V << SARADC_SARADC2_ONETIME_SAMPLE_S)
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#define SARADC_SARADC2_ONETIME_SAMPLE_V 0x00000001U
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#define SARADC_SARADC2_ONETIME_SAMPLE_S 30
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/** SARADC_SARADC1_ONETIME_SAMPLE : R/W; bitpos: [31]; default: 0;
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* enable adc1 onetime sample
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*/
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#define SARADC_SARADC1_ONETIME_SAMPLE (BIT(31))
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#define SARADC_SARADC1_ONETIME_SAMPLE_M (SARADC_SARADC1_ONETIME_SAMPLE_V << SARADC_SARADC1_ONETIME_SAMPLE_S)
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#define SARADC_SARADC1_ONETIME_SAMPLE_V 0x00000001U
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#define SARADC_SARADC1_ONETIME_SAMPLE_S 31
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/** SARADC_ARB_CTRL_REG register
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* digital saradc configure register
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*/
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#define SARADC_ARB_CTRL_REG (DR_REG_SARADC_BASE + 0x24)
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/** SARADC_ADC_ARB_APB_FORCE : R/W; bitpos: [2]; default: 0;
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* adc2 arbiter force to enableapb controller
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*/
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#define SARADC_ADC_ARB_APB_FORCE (BIT(2))
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#define SARADC_ADC_ARB_APB_FORCE_M (SARADC_ADC_ARB_APB_FORCE_V << SARADC_ADC_ARB_APB_FORCE_S)
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#define SARADC_ADC_ARB_APB_FORCE_V 0x00000001U
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#define SARADC_ADC_ARB_APB_FORCE_S 2
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/** SARADC_ADC_ARB_RTC_FORCE : R/W; bitpos: [3]; default: 0;
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* adc2 arbiter force to enable rtc controller
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*/
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#define SARADC_ADC_ARB_RTC_FORCE (BIT(3))
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#define SARADC_ADC_ARB_RTC_FORCE_M (SARADC_ADC_ARB_RTC_FORCE_V << SARADC_ADC_ARB_RTC_FORCE_S)
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#define SARADC_ADC_ARB_RTC_FORCE_V 0x00000001U
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#define SARADC_ADC_ARB_RTC_FORCE_S 3
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/** SARADC_ADC_ARB_WIFI_FORCE : R/W; bitpos: [4]; default: 0;
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* adc2 arbiter force to enable wifi controller
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*/
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#define SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
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#define SARADC_ADC_ARB_WIFI_FORCE_M (SARADC_ADC_ARB_WIFI_FORCE_V << SARADC_ADC_ARB_WIFI_FORCE_S)
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#define SARADC_ADC_ARB_WIFI_FORCE_V 0x00000001U
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#define SARADC_ADC_ARB_WIFI_FORCE_S 4
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/** SARADC_ADC_ARB_GRANT_FORCE : R/W; bitpos: [5]; default: 0;
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* adc2 arbiter force grant
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*/
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#define SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
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#define SARADC_ADC_ARB_GRANT_FORCE_M (SARADC_ADC_ARB_GRANT_FORCE_V << SARADC_ADC_ARB_GRANT_FORCE_S)
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#define SARADC_ADC_ARB_GRANT_FORCE_V 0x00000001U
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#define SARADC_ADC_ARB_GRANT_FORCE_S 5
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/** SARADC_ADC_ARB_APB_PRIORITY : R/W; bitpos: [7:6]; default: 0;
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* Set adc2 arbiterapb priority
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*/
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#define SARADC_ADC_ARB_APB_PRIORITY 0x00000003U
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#define SARADC_ADC_ARB_APB_PRIORITY_M (SARADC_ADC_ARB_APB_PRIORITY_V << SARADC_ADC_ARB_APB_PRIORITY_S)
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#define SARADC_ADC_ARB_APB_PRIORITY_V 0x00000003U
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#define SARADC_ADC_ARB_APB_PRIORITY_S 6
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/** SARADC_ADC_ARB_RTC_PRIORITY : R/W; bitpos: [9:8]; default: 1;
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* Set adc2 arbiter rtc priority
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*/
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#define SARADC_ADC_ARB_RTC_PRIORITY 0x00000003U
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#define SARADC_ADC_ARB_RTC_PRIORITY_M (SARADC_ADC_ARB_RTC_PRIORITY_V << SARADC_ADC_ARB_RTC_PRIORITY_S)
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#define SARADC_ADC_ARB_RTC_PRIORITY_V 0x00000003U
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#define SARADC_ADC_ARB_RTC_PRIORITY_S 8
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/** SARADC_ADC_ARB_WIFI_PRIORITY : R/W; bitpos: [11:10]; default: 2;
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* Set adc2 arbiter wifi priority
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*/
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#define SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003U
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#define SARADC_ADC_ARB_WIFI_PRIORITY_M (SARADC_ADC_ARB_WIFI_PRIORITY_V << SARADC_ADC_ARB_WIFI_PRIORITY_S)
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#define SARADC_ADC_ARB_WIFI_PRIORITY_V 0x00000003U
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#define SARADC_ADC_ARB_WIFI_PRIORITY_S 10
|
||||
/** SARADC_ADC_ARB_FIX_PRIORITY : R/W; bitpos: [12]; default: 0;
|
||||
* adc2 arbiter uses fixed priority
|
||||
*/
|
||||
#define SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
|
||||
#define SARADC_ADC_ARB_FIX_PRIORITY_M (SARADC_ADC_ARB_FIX_PRIORITY_V << SARADC_ADC_ARB_FIX_PRIORITY_S)
|
||||
#define SARADC_ADC_ARB_FIX_PRIORITY_V 0x00000001U
|
||||
#define SARADC_ADC_ARB_FIX_PRIORITY_S 12
|
||||
|
||||
/** SARADC_FILTER_CTRL0_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_FILTER_CTRL0_REG (DR_REG_SARADC_BASE + 0x28)
|
||||
/** SARADC_FILTER_CHANNEL1 : R/W; bitpos: [21:18]; default: 13;
|
||||
* configure filter1 to adc channel
|
||||
*/
|
||||
#define SARADC_FILTER_CHANNEL1 0x0000000FU
|
||||
#define SARADC_FILTER_CHANNEL1_M (SARADC_FILTER_CHANNEL1_V << SARADC_FILTER_CHANNEL1_S)
|
||||
#define SARADC_FILTER_CHANNEL1_V 0x0000000FU
|
||||
#define SARADC_FILTER_CHANNEL1_S 18
|
||||
/** SARADC_FILTER_CHANNEL0 : R/W; bitpos: [25:22]; default: 13;
|
||||
* configure filter0 to adc channel
|
||||
*/
|
||||
#define SARADC_FILTER_CHANNEL0 0x0000000FU
|
||||
#define SARADC_FILTER_CHANNEL0_M (SARADC_FILTER_CHANNEL0_V << SARADC_FILTER_CHANNEL0_S)
|
||||
#define SARADC_FILTER_CHANNEL0_V 0x0000000FU
|
||||
#define SARADC_FILTER_CHANNEL0_S 22
|
||||
/** SARADC_FILTER_RESET : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc1_filter
|
||||
*/
|
||||
#define SARADC_FILTER_RESET (BIT(31))
|
||||
#define SARADC_FILTER_RESET_M (SARADC_FILTER_RESET_V << SARADC_FILTER_RESET_S)
|
||||
#define SARADC_FILTER_RESET_V 0x00000001U
|
||||
#define SARADC_FILTER_RESET_S 31
|
||||
|
||||
/** SARADC_SAR1DATA_STATUS_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_SAR1DATA_STATUS_REG (DR_REG_SARADC_BASE + 0x2c)
|
||||
/** SARADC_APB_SARADC1_DATA : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc1 data
|
||||
*/
|
||||
#define SARADC_APB_SARADC1_DATA 0x0001FFFFU
|
||||
#define SARADC_APB_SARADC1_DATA_M (SARADC_APB_SARADC1_DATA_V << SARADC_APB_SARADC1_DATA_S)
|
||||
#define SARADC_APB_SARADC1_DATA_V 0x0001FFFFU
|
||||
#define SARADC_APB_SARADC1_DATA_S 0
|
||||
|
||||
/** SARADC_SAR2DATA_STATUS_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_SAR2DATA_STATUS_REG (DR_REG_SARADC_BASE + 0x30)
|
||||
/** SARADC_APB_SARADC2_DATA : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc2 data
|
||||
*/
|
||||
#define SARADC_APB_SARADC2_DATA 0x0001FFFFU
|
||||
#define SARADC_APB_SARADC2_DATA_M (SARADC_APB_SARADC2_DATA_V << SARADC_APB_SARADC2_DATA_S)
|
||||
#define SARADC_APB_SARADC2_DATA_V 0x0001FFFFU
|
||||
#define SARADC_APB_SARADC2_DATA_S 0
|
||||
|
||||
/** SARADC_THRES0_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_THRES0_CTRL_REG (DR_REG_SARADC_BASE + 0x34)
|
||||
/** SARADC_THRES0_CHANNEL : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres0 to adc channel
|
||||
*/
|
||||
#define SARADC_THRES0_CHANNEL 0x0000000FU
|
||||
#define SARADC_THRES0_CHANNEL_M (SARADC_THRES0_CHANNEL_V << SARADC_THRES0_CHANNEL_S)
|
||||
#define SARADC_THRES0_CHANNEL_V 0x0000000FU
|
||||
#define SARADC_THRES0_CHANNEL_S 0
|
||||
/** SARADC_THRES0_HIGH : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
#define SARADC_THRES0_HIGH 0x00001FFFU
|
||||
#define SARADC_THRES0_HIGH_M (SARADC_THRES0_HIGH_V << SARADC_THRES0_HIGH_S)
|
||||
#define SARADC_THRES0_HIGH_V 0x00001FFFU
|
||||
#define SARADC_THRES0_HIGH_S 5
|
||||
/** SARADC_THRES0_LOW : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
#define SARADC_THRES0_LOW 0x00001FFFU
|
||||
#define SARADC_THRES0_LOW_M (SARADC_THRES0_LOW_V << SARADC_THRES0_LOW_S)
|
||||
#define SARADC_THRES0_LOW_V 0x00001FFFU
|
||||
#define SARADC_THRES0_LOW_S 18
|
||||
|
||||
/** SARADC_THRES1_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_THRES1_CTRL_REG (DR_REG_SARADC_BASE + 0x38)
|
||||
/** SARADC_THRES1_CHANNEL : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres1 to adc channel
|
||||
*/
|
||||
#define SARADC_THRES1_CHANNEL 0x0000000FU
|
||||
#define SARADC_THRES1_CHANNEL_M (SARADC_THRES1_CHANNEL_V << SARADC_THRES1_CHANNEL_S)
|
||||
#define SARADC_THRES1_CHANNEL_V 0x0000000FU
|
||||
#define SARADC_THRES1_CHANNEL_S 0
|
||||
/** SARADC_THRES1_HIGH : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
#define SARADC_THRES1_HIGH 0x00001FFFU
|
||||
#define SARADC_THRES1_HIGH_M (SARADC_THRES1_HIGH_V << SARADC_THRES1_HIGH_S)
|
||||
#define SARADC_THRES1_HIGH_V 0x00001FFFU
|
||||
#define SARADC_THRES1_HIGH_S 5
|
||||
/** SARADC_THRES1_LOW : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
#define SARADC_THRES1_LOW 0x00001FFFU
|
||||
#define SARADC_THRES1_LOW_M (SARADC_THRES1_LOW_V << SARADC_THRES1_LOW_S)
|
||||
#define SARADC_THRES1_LOW_V 0x00001FFFU
|
||||
#define SARADC_THRES1_LOW_S 18
|
||||
|
||||
/** SARADC_THRES_CTRL_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_THRES_CTRL_REG (DR_REG_SARADC_BASE + 0x3c)
|
||||
/** SARADC_THRES_ALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* enable thres to all channel
|
||||
*/
|
||||
#define SARADC_THRES_ALL_EN (BIT(27))
|
||||
#define SARADC_THRES_ALL_EN_M (SARADC_THRES_ALL_EN_V << SARADC_THRES_ALL_EN_S)
|
||||
#define SARADC_THRES_ALL_EN_V 0x00000001U
|
||||
#define SARADC_THRES_ALL_EN_S 27
|
||||
/** SARADC_THRES1_EN : R/W; bitpos: [30]; default: 0;
|
||||
* enable thres1
|
||||
*/
|
||||
#define SARADC_THRES1_EN (BIT(30))
|
||||
#define SARADC_THRES1_EN_M (SARADC_THRES1_EN_V << SARADC_THRES1_EN_S)
|
||||
#define SARADC_THRES1_EN_V 0x00000001U
|
||||
#define SARADC_THRES1_EN_S 30
|
||||
/** SARADC_THRES0_EN : R/W; bitpos: [31]; default: 0;
|
||||
* enable thres0
|
||||
*/
|
||||
#define SARADC_THRES0_EN (BIT(31))
|
||||
#define SARADC_THRES0_EN_M (SARADC_THRES0_EN_V << SARADC_THRES0_EN_S)
|
||||
#define SARADC_THRES0_EN_V 0x00000001U
|
||||
#define SARADC_THRES0_EN_S 31
|
||||
|
||||
/** SARADC_INT_ENA_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define SARADC_INT_ENA_REG (DR_REG_SARADC_BASE + 0x40)
|
||||
/** SARADC_TSENS_INT_ENA : R/W; bitpos: [25]; default: 0;
|
||||
* tsens low interrupt enable
|
||||
*/
|
||||
#define SARADC_TSENS_INT_ENA (BIT(25))
|
||||
#define SARADC_TSENS_INT_ENA_M (SARADC_TSENS_INT_ENA_V << SARADC_TSENS_INT_ENA_S)
|
||||
#define SARADC_TSENS_INT_ENA_V 0x00000001U
|
||||
#define SARADC_TSENS_INT_ENA_S 25
|
||||
/** SARADC_THRES1_LOW_INT_ENA : R/W; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt enable
|
||||
*/
|
||||
#define SARADC_THRES1_LOW_INT_ENA (BIT(26))
|
||||
#define SARADC_THRES1_LOW_INT_ENA_M (SARADC_THRES1_LOW_INT_ENA_V << SARADC_THRES1_LOW_INT_ENA_S)
|
||||
#define SARADC_THRES1_LOW_INT_ENA_V 0x00000001U
|
||||
#define SARADC_THRES1_LOW_INT_ENA_S 26
|
||||
/** SARADC_THRES0_LOW_INT_ENA : R/W; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt enable
|
||||
*/
|
||||
#define SARADC_THRES0_LOW_INT_ENA (BIT(27))
|
||||
#define SARADC_THRES0_LOW_INT_ENA_M (SARADC_THRES0_LOW_INT_ENA_V << SARADC_THRES0_LOW_INT_ENA_S)
|
||||
#define SARADC_THRES0_LOW_INT_ENA_V 0x00000001U
|
||||
#define SARADC_THRES0_LOW_INT_ENA_S 27
|
||||
/** SARADC_THRES1_HIGH_INT_ENA : R/W; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt enable
|
||||
*/
|
||||
#define SARADC_THRES1_HIGH_INT_ENA (BIT(28))
|
||||
#define SARADC_THRES1_HIGH_INT_ENA_M (SARADC_THRES1_HIGH_INT_ENA_V << SARADC_THRES1_HIGH_INT_ENA_S)
|
||||
#define SARADC_THRES1_HIGH_INT_ENA_V 0x00000001U
|
||||
#define SARADC_THRES1_HIGH_INT_ENA_S 28
|
||||
/** SARADC_THRES0_HIGH_INT_ENA : R/W; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt enable
|
||||
*/
|
||||
#define SARADC_THRES0_HIGH_INT_ENA (BIT(29))
|
||||
#define SARADC_THRES0_HIGH_INT_ENA_M (SARADC_THRES0_HIGH_INT_ENA_V << SARADC_THRES0_HIGH_INT_ENA_S)
|
||||
#define SARADC_THRES0_HIGH_INT_ENA_V 0x00000001U
|
||||
#define SARADC_THRES0_HIGH_INT_ENA_S 29
|
||||
/** SARADC_APB_SARADC2_DONE_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt enable
|
||||
*/
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ENA (BIT(30))
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ENA_M (SARADC_APB_SARADC2_DONE_INT_ENA_V << SARADC_APB_SARADC2_DONE_INT_ENA_S)
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ENA_V 0x00000001U
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ENA_S 30
|
||||
/** SARADC_APB_SARADC1_DONE_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt enable
|
||||
*/
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ENA (BIT(31))
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ENA_M (SARADC_APB_SARADC1_DONE_INT_ENA_V << SARADC_APB_SARADC1_DONE_INT_ENA_S)
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ENA_V 0x00000001U
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ENA_S 31
|
||||
|
||||
/** SARADC_INT_RAW_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define SARADC_INT_RAW_REG (DR_REG_SARADC_BASE + 0x44)
|
||||
/** SARADC_TSENS_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt raw
|
||||
*/
|
||||
#define SARADC_TSENS_INT_RAW (BIT(25))
|
||||
#define SARADC_TSENS_INT_RAW_M (SARADC_TSENS_INT_RAW_V << SARADC_TSENS_INT_RAW_S)
|
||||
#define SARADC_TSENS_INT_RAW_V 0x00000001U
|
||||
#define SARADC_TSENS_INT_RAW_S 25
|
||||
/** SARADC_THRES1_LOW_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt raw
|
||||
*/
|
||||
#define SARADC_THRES1_LOW_INT_RAW (BIT(26))
|
||||
#define SARADC_THRES1_LOW_INT_RAW_M (SARADC_THRES1_LOW_INT_RAW_V << SARADC_THRES1_LOW_INT_RAW_S)
|
||||
#define SARADC_THRES1_LOW_INT_RAW_V 0x00000001U
|
||||
#define SARADC_THRES1_LOW_INT_RAW_S 26
|
||||
/** SARADC_THRES0_LOW_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt raw
|
||||
*/
|
||||
#define SARADC_THRES0_LOW_INT_RAW (BIT(27))
|
||||
#define SARADC_THRES0_LOW_INT_RAW_M (SARADC_THRES0_LOW_INT_RAW_V << SARADC_THRES0_LOW_INT_RAW_S)
|
||||
#define SARADC_THRES0_LOW_INT_RAW_V 0x00000001U
|
||||
#define SARADC_THRES0_LOW_INT_RAW_S 27
|
||||
/** SARADC_THRES1_HIGH_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt raw
|
||||
*/
|
||||
#define SARADC_THRES1_HIGH_INT_RAW (BIT(28))
|
||||
#define SARADC_THRES1_HIGH_INT_RAW_M (SARADC_THRES1_HIGH_INT_RAW_V << SARADC_THRES1_HIGH_INT_RAW_S)
|
||||
#define SARADC_THRES1_HIGH_INT_RAW_V 0x00000001U
|
||||
#define SARADC_THRES1_HIGH_INT_RAW_S 28
|
||||
/** SARADC_THRES0_HIGH_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt raw
|
||||
*/
|
||||
#define SARADC_THRES0_HIGH_INT_RAW (BIT(29))
|
||||
#define SARADC_THRES0_HIGH_INT_RAW_M (SARADC_THRES0_HIGH_INT_RAW_V << SARADC_THRES0_HIGH_INT_RAW_S)
|
||||
#define SARADC_THRES0_HIGH_INT_RAW_V 0x00000001U
|
||||
#define SARADC_THRES0_HIGH_INT_RAW_S 29
|
||||
/** SARADC_APB_SARADC2_DONE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt raw
|
||||
*/
|
||||
#define SARADC_APB_SARADC2_DONE_INT_RAW (BIT(30))
|
||||
#define SARADC_APB_SARADC2_DONE_INT_RAW_M (SARADC_APB_SARADC2_DONE_INT_RAW_V << SARADC_APB_SARADC2_DONE_INT_RAW_S)
|
||||
#define SARADC_APB_SARADC2_DONE_INT_RAW_V 0x00000001U
|
||||
#define SARADC_APB_SARADC2_DONE_INT_RAW_S 30
|
||||
/** SARADC_APB_SARADC1_DONE_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt raw
|
||||
*/
|
||||
#define SARADC_APB_SARADC1_DONE_INT_RAW (BIT(31))
|
||||
#define SARADC_APB_SARADC1_DONE_INT_RAW_M (SARADC_APB_SARADC1_DONE_INT_RAW_V << SARADC_APB_SARADC1_DONE_INT_RAW_S)
|
||||
#define SARADC_APB_SARADC1_DONE_INT_RAW_V 0x00000001U
|
||||
#define SARADC_APB_SARADC1_DONE_INT_RAW_S 31
|
||||
|
||||
/** SARADC_INT_ST_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define SARADC_INT_ST_REG (DR_REG_SARADC_BASE + 0x48)
|
||||
/** SARADC_TSENS_INT_ST : RO; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt state
|
||||
*/
|
||||
#define SARADC_TSENS_INT_ST (BIT(25))
|
||||
#define SARADC_TSENS_INT_ST_M (SARADC_TSENS_INT_ST_V << SARADC_TSENS_INT_ST_S)
|
||||
#define SARADC_TSENS_INT_ST_V 0x00000001U
|
||||
#define SARADC_TSENS_INT_ST_S 25
|
||||
/** SARADC_THRES1_LOW_INT_ST : RO; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt state
|
||||
*/
|
||||
#define SARADC_THRES1_LOW_INT_ST (BIT(26))
|
||||
#define SARADC_THRES1_LOW_INT_ST_M (SARADC_THRES1_LOW_INT_ST_V << SARADC_THRES1_LOW_INT_ST_S)
|
||||
#define SARADC_THRES1_LOW_INT_ST_V 0x00000001U
|
||||
#define SARADC_THRES1_LOW_INT_ST_S 26
|
||||
/** SARADC_THRES0_LOW_INT_ST : RO; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt state
|
||||
*/
|
||||
#define SARADC_THRES0_LOW_INT_ST (BIT(27))
|
||||
#define SARADC_THRES0_LOW_INT_ST_M (SARADC_THRES0_LOW_INT_ST_V << SARADC_THRES0_LOW_INT_ST_S)
|
||||
#define SARADC_THRES0_LOW_INT_ST_V 0x00000001U
|
||||
#define SARADC_THRES0_LOW_INT_ST_S 27
|
||||
/** SARADC_THRES1_HIGH_INT_ST : RO; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt state
|
||||
*/
|
||||
#define SARADC_THRES1_HIGH_INT_ST (BIT(28))
|
||||
#define SARADC_THRES1_HIGH_INT_ST_M (SARADC_THRES1_HIGH_INT_ST_V << SARADC_THRES1_HIGH_INT_ST_S)
|
||||
#define SARADC_THRES1_HIGH_INT_ST_V 0x00000001U
|
||||
#define SARADC_THRES1_HIGH_INT_ST_S 28
|
||||
/** SARADC_THRES0_HIGH_INT_ST : RO; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt state
|
||||
*/
|
||||
#define SARADC_THRES0_HIGH_INT_ST (BIT(29))
|
||||
#define SARADC_THRES0_HIGH_INT_ST_M (SARADC_THRES0_HIGH_INT_ST_V << SARADC_THRES0_HIGH_INT_ST_S)
|
||||
#define SARADC_THRES0_HIGH_INT_ST_V 0x00000001U
|
||||
#define SARADC_THRES0_HIGH_INT_ST_S 29
|
||||
/** SARADC_APB_SARADC2_DONE_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt state
|
||||
*/
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ST (BIT(30))
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ST_M (SARADC_APB_SARADC2_DONE_INT_ST_V << SARADC_APB_SARADC2_DONE_INT_ST_S)
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ST_V 0x00000001U
|
||||
#define SARADC_APB_SARADC2_DONE_INT_ST_S 30
|
||||
/** SARADC_APB_SARADC1_DONE_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt state
|
||||
*/
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ST (BIT(31))
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ST_M (SARADC_APB_SARADC1_DONE_INT_ST_V << SARADC_APB_SARADC1_DONE_INT_ST_S)
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ST_V 0x00000001U
|
||||
#define SARADC_APB_SARADC1_DONE_INT_ST_S 31
|
||||
|
||||
/** SARADC_INT_CLR_REG register
|
||||
* digital saradc int register
|
||||
*/
|
||||
#define SARADC_INT_CLR_REG (DR_REG_SARADC_BASE + 0x4c)
|
||||
/** SARADC_TSENS_INT_CLR : WT; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt clear
|
||||
*/
|
||||
#define SARADC_TSENS_INT_CLR (BIT(25))
|
||||
#define SARADC_TSENS_INT_CLR_M (SARADC_TSENS_INT_CLR_V << SARADC_TSENS_INT_CLR_S)
|
||||
#define SARADC_TSENS_INT_CLR_V 0x00000001U
|
||||
#define SARADC_TSENS_INT_CLR_S 25
|
||||
/** SARADC_THRES1_LOW_INT_CLR : WT; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt clear
|
||||
*/
|
||||
#define SARADC_THRES1_LOW_INT_CLR (BIT(26))
|
||||
#define SARADC_THRES1_LOW_INT_CLR_M (SARADC_THRES1_LOW_INT_CLR_V << SARADC_THRES1_LOW_INT_CLR_S)
|
||||
#define SARADC_THRES1_LOW_INT_CLR_V 0x00000001U
|
||||
#define SARADC_THRES1_LOW_INT_CLR_S 26
|
||||
/** SARADC_THRES0_LOW_INT_CLR : WT; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt clear
|
||||
*/
|
||||
#define SARADC_THRES0_LOW_INT_CLR (BIT(27))
|
||||
#define SARADC_THRES0_LOW_INT_CLR_M (SARADC_THRES0_LOW_INT_CLR_V << SARADC_THRES0_LOW_INT_CLR_S)
|
||||
#define SARADC_THRES0_LOW_INT_CLR_V 0x00000001U
|
||||
#define SARADC_THRES0_LOW_INT_CLR_S 27
|
||||
/** SARADC_THRES1_HIGH_INT_CLR : WT; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt clear
|
||||
*/
|
||||
#define SARADC_THRES1_HIGH_INT_CLR (BIT(28))
|
||||
#define SARADC_THRES1_HIGH_INT_CLR_M (SARADC_THRES1_HIGH_INT_CLR_V << SARADC_THRES1_HIGH_INT_CLR_S)
|
||||
#define SARADC_THRES1_HIGH_INT_CLR_V 0x00000001U
|
||||
#define SARADC_THRES1_HIGH_INT_CLR_S 28
|
||||
/** SARADC_THRES0_HIGH_INT_CLR : WT; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt clear
|
||||
*/
|
||||
#define SARADC_THRES0_HIGH_INT_CLR (BIT(29))
|
||||
#define SARADC_THRES0_HIGH_INT_CLR_M (SARADC_THRES0_HIGH_INT_CLR_V << SARADC_THRES0_HIGH_INT_CLR_S)
|
||||
#define SARADC_THRES0_HIGH_INT_CLR_V 0x00000001U
|
||||
#define SARADC_THRES0_HIGH_INT_CLR_S 29
|
||||
/** SARADC_APB_SARADC2_DONE_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt clear
|
||||
*/
|
||||
#define SARADC_APB_SARADC2_DONE_INT_CLR (BIT(30))
|
||||
#define SARADC_APB_SARADC2_DONE_INT_CLR_M (SARADC_APB_SARADC2_DONE_INT_CLR_V << SARADC_APB_SARADC2_DONE_INT_CLR_S)
|
||||
#define SARADC_APB_SARADC2_DONE_INT_CLR_V 0x00000001U
|
||||
#define SARADC_APB_SARADC2_DONE_INT_CLR_S 30
|
||||
/** SARADC_APB_SARADC1_DONE_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt clear
|
||||
*/
|
||||
#define SARADC_APB_SARADC1_DONE_INT_CLR (BIT(31))
|
||||
#define SARADC_APB_SARADC1_DONE_INT_CLR_M (SARADC_APB_SARADC1_DONE_INT_CLR_V << SARADC_APB_SARADC1_DONE_INT_CLR_S)
|
||||
#define SARADC_APB_SARADC1_DONE_INT_CLR_V 0x00000001U
|
||||
#define SARADC_APB_SARADC1_DONE_INT_CLR_S 31
|
||||
|
||||
/** SARADC_DMA_CONF_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_DMA_CONF_REG (DR_REG_SARADC_BASE + 0x50)
|
||||
/** SARADC_APB_ADC_EOF_NUM : R/W; bitpos: [15:0]; default: 255;
|
||||
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
|
||||
*/
|
||||
#define SARADC_APB_ADC_EOF_NUM 0x0000FFFFU
|
||||
#define SARADC_APB_ADC_EOF_NUM_M (SARADC_APB_ADC_EOF_NUM_V << SARADC_APB_ADC_EOF_NUM_S)
|
||||
#define SARADC_APB_ADC_EOF_NUM_V 0x0000FFFFU
|
||||
#define SARADC_APB_ADC_EOF_NUM_S 0
|
||||
/** SARADC_APB_ADC_RESET_FSM : R/W; bitpos: [30]; default: 0;
|
||||
* reset_apb_adc_state
|
||||
*/
|
||||
#define SARADC_APB_ADC_RESET_FSM (BIT(30))
|
||||
#define SARADC_APB_ADC_RESET_FSM_M (SARADC_APB_ADC_RESET_FSM_V << SARADC_APB_ADC_RESET_FSM_S)
|
||||
#define SARADC_APB_ADC_RESET_FSM_V 0x00000001U
|
||||
#define SARADC_APB_ADC_RESET_FSM_S 30
|
||||
/** SARADC_APB_ADC_TRANS : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc use spi_dma
|
||||
*/
|
||||
#define SARADC_APB_ADC_TRANS (BIT(31))
|
||||
#define SARADC_APB_ADC_TRANS_M (SARADC_APB_ADC_TRANS_V << SARADC_APB_ADC_TRANS_S)
|
||||
#define SARADC_APB_ADC_TRANS_V 0x00000001U
|
||||
#define SARADC_APB_ADC_TRANS_S 31
|
||||
|
||||
/** SARADC_CLKM_CONF_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_CLKM_CONF_REG (DR_REG_SARADC_BASE + 0x54)
|
||||
/** SARADC_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4;
|
||||
* Integral I2S clock divider value
|
||||
*/
|
||||
#define SARADC_CLKM_DIV_NUM 0x000000FFU
|
||||
#define SARADC_CLKM_DIV_NUM_M (SARADC_CLKM_DIV_NUM_V << SARADC_CLKM_DIV_NUM_S)
|
||||
#define SARADC_CLKM_DIV_NUM_V 0x000000FFU
|
||||
#define SARADC_CLKM_DIV_NUM_S 0
|
||||
/** SARADC_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0;
|
||||
* Fractional clock divider numerator value
|
||||
*/
|
||||
#define SARADC_CLKM_DIV_B 0x0000003FU
|
||||
#define SARADC_CLKM_DIV_B_M (SARADC_CLKM_DIV_B_V << SARADC_CLKM_DIV_B_S)
|
||||
#define SARADC_CLKM_DIV_B_V 0x0000003FU
|
||||
#define SARADC_CLKM_DIV_B_S 8
|
||||
/** SARADC_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0;
|
||||
* Fractional clock divider denominator value
|
||||
*/
|
||||
#define SARADC_CLKM_DIV_A 0x0000003FU
|
||||
#define SARADC_CLKM_DIV_A_M (SARADC_CLKM_DIV_A_V << SARADC_CLKM_DIV_A_S)
|
||||
#define SARADC_CLKM_DIV_A_V 0x0000003FU
|
||||
#define SARADC_CLKM_DIV_A_S 14
|
||||
/** SARADC_CLK_EN : R/W; bitpos: [20]; default: 0;
|
||||
* reg clk en
|
||||
*/
|
||||
#define SARADC_CLK_EN (BIT(20))
|
||||
#define SARADC_CLK_EN_M (SARADC_CLK_EN_V << SARADC_CLK_EN_S)
|
||||
#define SARADC_CLK_EN_V 0x00000001U
|
||||
#define SARADC_CLK_EN_S 20
|
||||
/** SARADC_CLK_SEL : R/W; bitpos: [22:21]; default: 0;
|
||||
* Set this bit to enable clk_apll
|
||||
*/
|
||||
#define SARADC_CLK_SEL 0x00000003U
|
||||
#define SARADC_CLK_SEL_M (SARADC_CLK_SEL_V << SARADC_CLK_SEL_S)
|
||||
#define SARADC_CLK_SEL_V 0x00000003U
|
||||
#define SARADC_CLK_SEL_S 21
|
||||
|
||||
/** SARADC_APB_TSENS_CTRL_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define SARADC_APB_TSENS_CTRL_REG (DR_REG_SARADC_BASE + 0x58)
|
||||
/** SARADC_TSENS_OUT : RO; bitpos: [7:0]; default: 128;
|
||||
* temperature sensor data out
|
||||
*/
|
||||
#define SARADC_TSENS_OUT 0x000000FFU
|
||||
#define SARADC_TSENS_OUT_M (SARADC_TSENS_OUT_V << SARADC_TSENS_OUT_S)
|
||||
#define SARADC_TSENS_OUT_V 0x000000FFU
|
||||
#define SARADC_TSENS_OUT_S 0
|
||||
/** SARADC_TSENS_IN_INV : R/W; bitpos: [13]; default: 0;
|
||||
* invert temperature sensor data
|
||||
*/
|
||||
#define SARADC_TSENS_IN_INV (BIT(13))
|
||||
#define SARADC_TSENS_IN_INV_M (SARADC_TSENS_IN_INV_V << SARADC_TSENS_IN_INV_S)
|
||||
#define SARADC_TSENS_IN_INV_V 0x00000001U
|
||||
#define SARADC_TSENS_IN_INV_S 13
|
||||
/** SARADC_TSENS_CLK_DIV : R/W; bitpos: [21:14]; default: 6;
|
||||
* temperature sensor clock divider
|
||||
*/
|
||||
#define SARADC_TSENS_CLK_DIV 0x000000FFU
|
||||
#define SARADC_TSENS_CLK_DIV_M (SARADC_TSENS_CLK_DIV_V << SARADC_TSENS_CLK_DIV_S)
|
||||
#define SARADC_TSENS_CLK_DIV_V 0x000000FFU
|
||||
#define SARADC_TSENS_CLK_DIV_S 14
|
||||
/** SARADC_TSENS_PU : R/W; bitpos: [22]; default: 0;
|
||||
* temperature sensor power up
|
||||
*/
|
||||
#define SARADC_TSENS_PU (BIT(22))
|
||||
#define SARADC_TSENS_PU_M (SARADC_TSENS_PU_V << SARADC_TSENS_PU_S)
|
||||
#define SARADC_TSENS_PU_V 0x00000001U
|
||||
#define SARADC_TSENS_PU_S 22
|
||||
|
||||
/** SARADC_TSENS_CTRL2_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define SARADC_TSENS_CTRL2_REG (DR_REG_SARADC_BASE + 0x5c)
|
||||
/** SARADC_TSENS_XPD_WAIT : R/W; bitpos: [11:0]; default: 2;
|
||||
* the time that power up tsens need wait
|
||||
*/
|
||||
#define SARADC_TSENS_XPD_WAIT 0x00000FFFU
|
||||
#define SARADC_TSENS_XPD_WAIT_M (SARADC_TSENS_XPD_WAIT_V << SARADC_TSENS_XPD_WAIT_S)
|
||||
#define SARADC_TSENS_XPD_WAIT_V 0x00000FFFU
|
||||
#define SARADC_TSENS_XPD_WAIT_S 0
|
||||
/** SARADC_TSENS_XPD_FORCE : R/W; bitpos: [13:12]; default: 0;
|
||||
* force power up tsens
|
||||
*/
|
||||
#define SARADC_TSENS_XPD_FORCE 0x00000003U
|
||||
#define SARADC_TSENS_XPD_FORCE_M (SARADC_TSENS_XPD_FORCE_V << SARADC_TSENS_XPD_FORCE_S)
|
||||
#define SARADC_TSENS_XPD_FORCE_V 0x00000003U
|
||||
#define SARADC_TSENS_XPD_FORCE_S 12
|
||||
/** SARADC_TSENS_CLK_INV : R/W; bitpos: [14]; default: 1;
|
||||
* inv tsens clk
|
||||
*/
|
||||
#define SARADC_TSENS_CLK_INV (BIT(14))
|
||||
#define SARADC_TSENS_CLK_INV_M (SARADC_TSENS_CLK_INV_V << SARADC_TSENS_CLK_INV_S)
|
||||
#define SARADC_TSENS_CLK_INV_V 0x00000001U
|
||||
#define SARADC_TSENS_CLK_INV_S 14
|
||||
/** SARADC_TSENS_CLK_SEL : R/W; bitpos: [15]; default: 0;
|
||||
* tsens clk select
|
||||
*/
|
||||
#define SARADC_TSENS_CLK_SEL (BIT(15))
|
||||
#define SARADC_TSENS_CLK_SEL_M (SARADC_TSENS_CLK_SEL_V << SARADC_TSENS_CLK_SEL_S)
|
||||
#define SARADC_TSENS_CLK_SEL_V 0x00000001U
|
||||
#define SARADC_TSENS_CLK_SEL_S 15
|
||||
|
||||
/** SARADC_CALI_REG register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
#define SARADC_CALI_REG (DR_REG_SARADC_BASE + 0x60)
|
||||
/** SARADC_CALI_CFG : R/W; bitpos: [16:0]; default: 32768;
|
||||
* saradc cali factor
|
||||
*/
|
||||
#define SARADC_CALI_CFG 0x0001FFFFU
|
||||
#define SARADC_CALI_CFG_M (SARADC_CALI_CFG_V << SARADC_CALI_CFG_S)
|
||||
#define SARADC_CALI_CFG_V 0x0001FFFFU
|
||||
#define SARADC_CALI_CFG_S 0
|
||||
|
||||
/** APB_TSENS_WAKE_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_TSENS_WAKE_REG (DR_REG_SARADC_BASE + 0x64)
|
||||
/** SARADC_WAKEUP_TH_LOW : R/W; bitpos: [7:0]; default: 0;
|
||||
* reg_wakeup_th_low
|
||||
*/
|
||||
#define SARADC_WAKEUP_TH_LOW 0x000000FFU
|
||||
#define SARADC_WAKEUP_TH_LOW_M (SARADC_WAKEUP_TH_LOW_V << SARADC_WAKEUP_TH_LOW_S)
|
||||
#define SARADC_WAKEUP_TH_LOW_V 0x000000FFU
|
||||
#define SARADC_WAKEUP_TH_LOW_S 0
|
||||
/** SARADC_WAKEUP_TH_HIGH : R/W; bitpos: [15:8]; default: 255;
|
||||
* reg_wakeup_th_high
|
||||
*/
|
||||
#define SARADC_WAKEUP_TH_HIGH 0x000000FFU
|
||||
#define SARADC_WAKEUP_TH_HIGH_M (SARADC_WAKEUP_TH_HIGH_V << SARADC_WAKEUP_TH_HIGH_S)
|
||||
#define SARADC_WAKEUP_TH_HIGH_V 0x000000FFU
|
||||
#define SARADC_WAKEUP_TH_HIGH_S 8
|
||||
/** SARADC_WAKEUP_OVER_UPPER_TH : RO; bitpos: [16]; default: 0;
|
||||
* reg_wakeup_over_upper_th
|
||||
*/
|
||||
#define SARADC_WAKEUP_OVER_UPPER_TH (BIT(16))
|
||||
#define SARADC_WAKEUP_OVER_UPPER_TH_M (SARADC_WAKEUP_OVER_UPPER_TH_V << SARADC_WAKEUP_OVER_UPPER_TH_S)
|
||||
#define SARADC_WAKEUP_OVER_UPPER_TH_V 0x00000001U
|
||||
#define SARADC_WAKEUP_OVER_UPPER_TH_S 16
|
||||
/** SARADC_WAKEUP_MODE : R/W; bitpos: [17]; default: 0;
|
||||
* reg_wakeup_mode
|
||||
*/
|
||||
#define SARADC_WAKEUP_MODE (BIT(17))
|
||||
#define SARADC_WAKEUP_MODE_M (SARADC_WAKEUP_MODE_V << SARADC_WAKEUP_MODE_S)
|
||||
#define SARADC_WAKEUP_MODE_V 0x00000001U
|
||||
#define SARADC_WAKEUP_MODE_S 17
|
||||
/** SARADC_WAKEUP_EN : R/W; bitpos: [18]; default: 0;
|
||||
* reg_wakeup_en
|
||||
*/
|
||||
#define SARADC_WAKEUP_EN (BIT(18))
|
||||
#define SARADC_WAKEUP_EN_M (SARADC_WAKEUP_EN_V << SARADC_WAKEUP_EN_S)
|
||||
#define SARADC_WAKEUP_EN_V 0x00000001U
|
||||
#define SARADC_WAKEUP_EN_S 18
|
||||
|
||||
/** APB_TSENS_SAMPLE_REG register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
#define APB_TSENS_SAMPLE_REG (DR_REG_SARADC_BASE + 0x68)
|
||||
/** SARADC_TSENS_SAMPLE_RATE : R/W; bitpos: [15:0]; default: 20;
|
||||
* HW sample rate
|
||||
*/
|
||||
#define SARADC_TSENS_SAMPLE_RATE 0x0000FFFFU
|
||||
#define SARADC_TSENS_SAMPLE_RATE_M (SARADC_TSENS_SAMPLE_RATE_V << SARADC_TSENS_SAMPLE_RATE_S)
|
||||
#define SARADC_TSENS_SAMPLE_RATE_V 0x0000FFFFU
|
||||
#define SARADC_TSENS_SAMPLE_RATE_S 0
|
||||
/** SARADC_TSENS_SAMPLE_EN : R/W; bitpos: [16]; default: 0;
|
||||
* HW sample en
|
||||
*/
|
||||
#define SARADC_TSENS_SAMPLE_EN (BIT(16))
|
||||
#define SARADC_TSENS_SAMPLE_EN_M (SARADC_TSENS_SAMPLE_EN_V << SARADC_TSENS_SAMPLE_EN_S)
|
||||
#define SARADC_TSENS_SAMPLE_EN_V 0x00000001U
|
||||
#define SARADC_TSENS_SAMPLE_EN_S 16
|
||||
|
||||
/** SARADC_CTRL_DATE_REG register
|
||||
* version
|
||||
*/
|
||||
#define SARADC_CTRL_DATE_REG (DR_REG_SARADC_BASE + 0x3fc)
|
||||
/** SARADC_DATE : R/W; bitpos: [31:0]; default: 35676736;
|
||||
* version
|
||||
*/
|
||||
#define SARADC_DATE 0xFFFFFFFFU
|
||||
#define SARADC_DATE_M (SARADC_DATE_V << SARADC_DATE_S)
|
||||
#define SARADC_DATE_V 0xFFFFFFFFU
|
||||
#define SARADC_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,757 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configure Register */
|
||||
/** Type of saradc_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_start_force : R/W; bitpos: [0]; default: 0;
|
||||
* select software enable saradc sample
|
||||
*/
|
||||
uint32_t saradc_start_force:1;
|
||||
/** saradc_start : R/W; bitpos: [1]; default: 0;
|
||||
* software enable saradc sample
|
||||
*/
|
||||
uint32_t saradc_start:1;
|
||||
uint32_t reserved_2:4;
|
||||
/** saradc_sar_clk_gated : R/W; bitpos: [6]; default: 1;
|
||||
* SAR clock gated
|
||||
*/
|
||||
uint32_t saradc_sar_clk_gated:1;
|
||||
/** saradc_sar_clk_div : R/W; bitpos: [14:7]; default: 4;
|
||||
* SAR clock divider
|
||||
*/
|
||||
uint32_t saradc_sar_clk_div:8;
|
||||
/** saradc_sar_patt_len : R/W; bitpos: [17:15]; default: 7;
|
||||
* 0 ~ 15 means length 1 ~ 16
|
||||
*/
|
||||
uint32_t saradc_sar_patt_len:3;
|
||||
uint32_t reserved_18:5;
|
||||
/** saradc_sar_patt_p_clear : R/W; bitpos: [23]; default: 0;
|
||||
* clear the pointer of pattern table for DIG ADC1 CTRL
|
||||
*/
|
||||
uint32_t saradc_sar_patt_p_clear:1;
|
||||
uint32_t reserved_24:3;
|
||||
/** saradc_xpd_sar_force : R/W; bitpos: [28:27]; default: 0;
|
||||
* force option to xpd sar blocks
|
||||
*/
|
||||
uint32_t saradc_xpd_sar_force:2;
|
||||
/** saradc_saradc2_pwdet_drv : R/W; bitpos: [29]; default: 0;
|
||||
* enable saradc2 power detect driven func.
|
||||
*/
|
||||
uint32_t saradc_saradc2_pwdet_drv:1;
|
||||
/** saradc_wait_arb_cycle : R/W; bitpos: [31:30]; default: 1;
|
||||
* wait arbit signal stable after sar_done
|
||||
*/
|
||||
uint32_t saradc_wait_arb_cycle:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_ctrl2 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_meas_num_limit : R/W; bitpos: [0]; default: 0;
|
||||
* enable max meas num
|
||||
*/
|
||||
uint32_t saradc_meas_num_limit:1;
|
||||
/** saradc_max_meas_num : R/W; bitpos: [8:1]; default: 255;
|
||||
* max conversion number
|
||||
*/
|
||||
uint32_t saradc_max_meas_num:8;
|
||||
/** saradc_sar1_inv : R/W; bitpos: [9]; default: 0;
|
||||
* 1: data to DIG ADC1 CTRL is inverted, otherwise not
|
||||
*/
|
||||
uint32_t saradc_sar1_inv:1;
|
||||
/** saradc_sar2_inv : R/W; bitpos: [10]; default: 0;
|
||||
* 1: data to DIG ADC2 CTRL is inverted, otherwise not
|
||||
*/
|
||||
uint32_t saradc_sar2_inv:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** saradc_timer_target : R/W; bitpos: [23:12]; default: 10;
|
||||
* to set saradc timer target
|
||||
*/
|
||||
uint32_t saradc_timer_target:12;
|
||||
/** saradc_timer_en : R/W; bitpos: [24]; default: 0;
|
||||
* to enable saradc timer trigger
|
||||
*/
|
||||
uint32_t saradc_timer_en:1;
|
||||
uint32_t reserved_25:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_ctrl2_reg_t;
|
||||
|
||||
/** Type of saradc_filter_ctrl1 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:26;
|
||||
/** saradc_adc_filter_factor1 : R/W; bitpos: [28:26]; default: 0;
|
||||
* Factor of saradc filter1
|
||||
*/
|
||||
uint32_t saradc_adc_filter_factor1:3;
|
||||
/** saradc_adc_filter_factor0 : R/W; bitpos: [31:29]; default: 0;
|
||||
* Factor of saradc filter0
|
||||
*/
|
||||
uint32_t saradc_adc_filter_factor0:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_filter_ctrl1_reg_t;
|
||||
|
||||
/** Type of saradc_fsm_wait register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_xpd_wait : R/W; bitpos: [7:0]; default: 8;
|
||||
* saradc_xpd_wait
|
||||
*/
|
||||
uint32_t saradc_xpd_wait:8;
|
||||
/** saradc_rstb_wait : R/W; bitpos: [15:8]; default: 8;
|
||||
* saradc_rstb_wait
|
||||
*/
|
||||
uint32_t saradc_rstb_wait:8;
|
||||
/** saradc_standby_wait : R/W; bitpos: [23:16]; default: 255;
|
||||
* saradc_standby_wait
|
||||
*/
|
||||
uint32_t saradc_standby_wait:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_fsm_wait_reg_t;
|
||||
|
||||
/** Type of saradc_sar1_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_sar1_status : RO; bitpos: [31:0]; default: 536870912;
|
||||
* saradc1 status about data and channel
|
||||
*/
|
||||
uint32_t saradc_sar1_status:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar1_status_reg_t;
|
||||
|
||||
/** Type of saradc_sar2_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_sar2_status : RO; bitpos: [31:0]; default: 536870912;
|
||||
* saradc2 status about data and channel
|
||||
*/
|
||||
uint32_t saradc_sar2_status:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar2_status_reg_t;
|
||||
|
||||
/** Type of saradc_sar_patt_tab1 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_sar_patt_tab1 : R/W; bitpos: [23:0]; default: 16777215;
|
||||
* item 0 ~ 3 for pattern table 1 (each item one byte)
|
||||
*/
|
||||
uint32_t saradc_sar_patt_tab1:24;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar_patt_tab1_reg_t;
|
||||
|
||||
/** Type of saradc_sar_patt_tab2 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_sar_patt_tab2 : R/W; bitpos: [23:0]; default: 16777215;
|
||||
* Item 4 ~ 7 for pattern table 1 (each item one byte)
|
||||
*/
|
||||
uint32_t saradc_sar_patt_tab2:24;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar_patt_tab2_reg_t;
|
||||
|
||||
/** Type of saradc_onetime_sample register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:23;
|
||||
/** saradc_onetime_atten : R/W; bitpos: [24:23]; default: 0;
|
||||
* configure onetime atten
|
||||
*/
|
||||
uint32_t saradc_onetime_atten:2;
|
||||
/** saradc_onetime_channel : R/W; bitpos: [28:25]; default: 13;
|
||||
* configure onetime channel
|
||||
*/
|
||||
uint32_t saradc_onetime_channel:4;
|
||||
/** saradc_onetime_start : R/W; bitpos: [29]; default: 0;
|
||||
* trigger adc onetime sample
|
||||
*/
|
||||
uint32_t saradc_onetime_start:1;
|
||||
/** saradc_saradc2_onetime_sample : R/W; bitpos: [30]; default: 0;
|
||||
* enable adc2 onetime sample
|
||||
*/
|
||||
uint32_t saradc_saradc2_onetime_sample:1;
|
||||
/** saradc_saradc1_onetime_sample : R/W; bitpos: [31]; default: 0;
|
||||
* enable adc1 onetime sample
|
||||
*/
|
||||
uint32_t saradc_saradc1_onetime_sample:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_onetime_sample_reg_t;
|
||||
|
||||
/** Type of saradc_arb_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:2;
|
||||
/** saradc_adc_arb_apb_force : R/W; bitpos: [2]; default: 0;
|
||||
* adc2 arbiter force to enableapb controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_apb_force:1;
|
||||
/** saradc_adc_arb_rtc_force : R/W; bitpos: [3]; default: 0;
|
||||
* adc2 arbiter force to enable rtc controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_rtc_force:1;
|
||||
/** saradc_adc_arb_wifi_force : R/W; bitpos: [4]; default: 0;
|
||||
* adc2 arbiter force to enable wifi controller
|
||||
*/
|
||||
uint32_t saradc_adc_arb_wifi_force:1;
|
||||
/** saradc_adc_arb_grant_force : R/W; bitpos: [5]; default: 0;
|
||||
* adc2 arbiter force grant
|
||||
*/
|
||||
uint32_t saradc_adc_arb_grant_force:1;
|
||||
/** saradc_adc_arb_apb_priority : R/W; bitpos: [7:6]; default: 0;
|
||||
* Set adc2 arbiterapb priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_apb_priority:2;
|
||||
/** saradc_adc_arb_rtc_priority : R/W; bitpos: [9:8]; default: 1;
|
||||
* Set adc2 arbiter rtc priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_rtc_priority:2;
|
||||
/** saradc_adc_arb_wifi_priority : R/W; bitpos: [11:10]; default: 2;
|
||||
* Set adc2 arbiter wifi priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_wifi_priority:2;
|
||||
/** saradc_adc_arb_fix_priority : R/W; bitpos: [12]; default: 0;
|
||||
* adc2 arbiter uses fixed priority
|
||||
*/
|
||||
uint32_t saradc_adc_arb_fix_priority:1;
|
||||
uint32_t reserved_13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_arb_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_filter_ctrl0 register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:18;
|
||||
/** saradc_adc_filter_channel1 : R/W; bitpos: [21:18]; default: 13;
|
||||
* configure filter1 to adc channel
|
||||
*/
|
||||
uint32_t saradc_adc_filter_channel1:4;
|
||||
/** saradc_adc_filter_channel0 : R/W; bitpos: [25:22]; default: 13;
|
||||
* configure filter0 to adc channel
|
||||
*/
|
||||
uint32_t saradc_adc_filter_channel0:4;
|
||||
uint32_t reserved_26:5;
|
||||
/** saradc_adc_filter_reset : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc1_filter
|
||||
*/
|
||||
uint32_t saradc_adc_filter_reset:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_filter_ctrl0_reg_t;
|
||||
|
||||
/** Type of saradc_sar1data_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_adc1_data : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc1 data
|
||||
*/
|
||||
uint32_t saradc_adc1_data:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar1data_status_reg_t;
|
||||
|
||||
/** Type of saradc_sar2data_status register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_adc2_data : RO; bitpos: [16:0]; default: 0;
|
||||
* saradc2 data
|
||||
*/
|
||||
uint32_t saradc_adc2_data:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_sar2data_status_reg_t;
|
||||
|
||||
/** Type of saradc_thres0_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_adc_thres0_channel : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres0 to adc channel
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_channel:4;
|
||||
uint32_t reserved_4:1;
|
||||
/** saradc_adc_thres0_high : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_high:13;
|
||||
/** saradc_adc_thres0_low : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres0 monitor thres
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_low:13;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_thres0_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_thres1_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_adc_thres1_channel : R/W; bitpos: [3:0]; default: 13;
|
||||
* configure thres1 to adc channel
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_channel:4;
|
||||
uint32_t reserved_4:1;
|
||||
/** saradc_adc_thres1_high : R/W; bitpos: [17:5]; default: 8191;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_high:13;
|
||||
/** saradc_adc_thres1_low : R/W; bitpos: [30:18]; default: 0;
|
||||
* saradc thres1 monitor thres
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_low:13;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_thres1_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_thres_ctrl register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:27;
|
||||
/** saradc_adc_thres_all_en : R/W; bitpos: [27]; default: 0;
|
||||
* enable thres to all channel
|
||||
*/
|
||||
uint32_t saradc_adc_thres_all_en:1;
|
||||
uint32_t reserved_28:2;
|
||||
/** saradc_adc_thres1_en : R/W; bitpos: [30]; default: 0;
|
||||
* enable thres1
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_en:1;
|
||||
/** saradc_adc_thres0_en : R/W; bitpos: [31]; default: 0;
|
||||
* enable thres0
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_thres_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_int_ena register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_adc_tsens_int_ena : R/W; bitpos: [25]; default: 0;
|
||||
* tsens low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc_tsens_int_ena:1;
|
||||
/** saradc_adc_thres1_low_int_ena : R/W; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_low_int_ena:1;
|
||||
/** saradc_adc_thres0_low_int_ena : R/W; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_low_int_ena:1;
|
||||
/** saradc_adc_thres1_high_int_ena : R/W; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_high_int_ena:1;
|
||||
/** saradc_adc_thres0_high_int_ena : R/W; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_high_int_ena:1;
|
||||
/** saradc_adc2_done_int_ena : R/W; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc2_done_int_ena:1;
|
||||
/** saradc_adc1_done_int_ena : R/W; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt enable
|
||||
*/
|
||||
uint32_t saradc_adc1_done_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_int_ena_reg_t;
|
||||
|
||||
/** Type of saradc_int_raw register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_adc_tsens_int_raw : R/WTC/SS; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc_tsens_int_raw:1;
|
||||
/** saradc_adc_thres1_low_int_raw : R/WTC/SS; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_low_int_raw:1;
|
||||
/** saradc_adc_thres0_low_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_low_int_raw:1;
|
||||
/** saradc_adc_thres1_high_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_high_int_raw:1;
|
||||
/** saradc_adc_thres0_high_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_high_int_raw:1;
|
||||
/** saradc_adc2_done_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc2_done_int_raw:1;
|
||||
/** saradc_adc1_done_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt raw
|
||||
*/
|
||||
uint32_t saradc_adc1_done_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_int_raw_reg_t;
|
||||
|
||||
/** Type of saradc_int_st register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_adc_tsens_int_st : RO; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc_tsens_int_st:1;
|
||||
/** saradc_adc_thres1_low_int_st : RO; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_low_int_st:1;
|
||||
/** saradc_adc_thres0_low_int_st : RO; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_low_int_st:1;
|
||||
/** saradc_adc_thres1_high_int_st : RO; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_high_int_st:1;
|
||||
/** saradc_adc_thres0_high_int_st : RO; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_high_int_st:1;
|
||||
/** saradc_adc2_done_int_st : RO; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc2_done_int_st:1;
|
||||
/** saradc_adc1_done_int_st : RO; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt state
|
||||
*/
|
||||
uint32_t saradc_adc1_done_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_int_st_reg_t;
|
||||
|
||||
/** Type of saradc_int_clr register
|
||||
* digital saradc int register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:25;
|
||||
/** saradc_adc_tsens_int_clr : WT; bitpos: [25]; default: 0;
|
||||
* saradc tsens interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc_tsens_int_clr:1;
|
||||
/** saradc_adc_thres1_low_int_clr : WT; bitpos: [26]; default: 0;
|
||||
* saradc thres1 low interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_low_int_clr:1;
|
||||
/** saradc_adc_thres0_low_int_clr : WT; bitpos: [27]; default: 0;
|
||||
* saradc thres0 low interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_low_int_clr:1;
|
||||
/** saradc_adc_thres1_high_int_clr : WT; bitpos: [28]; default: 0;
|
||||
* saradc thres1 high interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc_thres1_high_int_clr:1;
|
||||
/** saradc_adc_thres0_high_int_clr : WT; bitpos: [29]; default: 0;
|
||||
* saradc thres0 high interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc_thres0_high_int_clr:1;
|
||||
/** saradc_adc2_done_int_clr : WT; bitpos: [30]; default: 0;
|
||||
* saradc2 done interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc2_done_int_clr:1;
|
||||
/** saradc_adc1_done_int_clr : WT; bitpos: [31]; default: 0;
|
||||
* saradc1 done interrupt clear
|
||||
*/
|
||||
uint32_t saradc_adc1_done_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_int_clr_reg_t;
|
||||
|
||||
/** Type of saradc_dma_conf register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_apb_adc_eof_num : R/W; bitpos: [15:0]; default: 255;
|
||||
* the dma_in_suc_eof gen when sample cnt = spi_eof_num
|
||||
*/
|
||||
uint32_t saradc_apb_adc_eof_num:16;
|
||||
uint32_t reserved_16:14;
|
||||
/** saradc_apb_adc_reset_fsm : R/W; bitpos: [30]; default: 0;
|
||||
* reset_apb_adc_state
|
||||
*/
|
||||
uint32_t saradc_apb_adc_reset_fsm:1;
|
||||
/** saradc_apb_adc_trans : R/W; bitpos: [31]; default: 0;
|
||||
* enable apb_adc use spi_dma
|
||||
*/
|
||||
uint32_t saradc_apb_adc_trans:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_dma_conf_reg_t;
|
||||
|
||||
/** Type of saradc_clkm_conf register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_clkm_div_num : R/W; bitpos: [7:0]; default: 4;
|
||||
* Integral I2S clock divider value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_num:8;
|
||||
/** saradc_clkm_div_b : R/W; bitpos: [13:8]; default: 0;
|
||||
* Fractional clock divider numerator value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_b:6;
|
||||
/** saradc_clkm_div_a : R/W; bitpos: [19:14]; default: 0;
|
||||
* Fractional clock divider denominator value
|
||||
*/
|
||||
uint32_t saradc_clkm_div_a:6;
|
||||
/** saradc_clk_en : R/W; bitpos: [20]; default: 0;
|
||||
* reg clk en
|
||||
*/
|
||||
uint32_t saradc_clk_en:1;
|
||||
/** saradc_clk_sel : R/W; bitpos: [22:21]; default: 0;
|
||||
* Set this bit to enable clk_apll
|
||||
*/
|
||||
uint32_t saradc_clk_sel:2;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_clkm_conf_reg_t;
|
||||
|
||||
/** Type of saradc_apb_tsens_ctrl register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_tsens_out : RO; bitpos: [7:0]; default: 128;
|
||||
* temperature sensor data out
|
||||
*/
|
||||
uint32_t saradc_tsens_out:8;
|
||||
uint32_t reserved_8:5;
|
||||
/** saradc_tsens_in_inv : R/W; bitpos: [13]; default: 0;
|
||||
* invert temperature sensor data
|
||||
*/
|
||||
uint32_t saradc_tsens_in_inv:1;
|
||||
/** saradc_tsens_clk_div : R/W; bitpos: [21:14]; default: 6;
|
||||
* temperature sensor clock divider
|
||||
*/
|
||||
uint32_t saradc_tsens_clk_div:8;
|
||||
/** saradc_tsens_pu : R/W; bitpos: [22]; default: 0;
|
||||
* temperature sensor power up
|
||||
*/
|
||||
uint32_t saradc_tsens_pu:1;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_apb_tsens_ctrl_reg_t;
|
||||
|
||||
/** Type of saradc_tsens_ctrl2 register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_tsens_xpd_wait : R/W; bitpos: [11:0]; default: 2;
|
||||
* the time that power up tsens need wait
|
||||
*/
|
||||
uint32_t saradc_tsens_xpd_wait:12;
|
||||
/** saradc_tsens_xpd_force : R/W; bitpos: [13:12]; default: 0;
|
||||
* force power up tsens
|
||||
*/
|
||||
uint32_t saradc_tsens_xpd_force:2;
|
||||
/** saradc_tsens_clk_inv : R/W; bitpos: [14]; default: 1;
|
||||
* inv tsens clk
|
||||
*/
|
||||
uint32_t saradc_tsens_clk_inv:1;
|
||||
/** saradc_tsens_clk_sel : R/W; bitpos: [15]; default: 0;
|
||||
* tsens clk select
|
||||
*/
|
||||
uint32_t saradc_tsens_clk_sel:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_tsens_ctrl2_reg_t;
|
||||
|
||||
/** Type of saradc_cali register
|
||||
* digital saradc configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_adc_cali_cfg : R/W; bitpos: [16:0]; default: 32768;
|
||||
* saradc cali factor
|
||||
*/
|
||||
uint32_t saradc_adc_cali_cfg:17;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_cali_reg_t;
|
||||
|
||||
/** Type of tsens_wake register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_wakeup_th_low : R/W; bitpos: [7:0]; default: 0;
|
||||
* reg_wakeup_th_low
|
||||
*/
|
||||
uint32_t saradc_wakeup_th_low:8;
|
||||
/** saradc_wakeup_th_high : R/W; bitpos: [15:8]; default: 255;
|
||||
* reg_wakeup_th_high
|
||||
*/
|
||||
uint32_t saradc_wakeup_th_high:8;
|
||||
/** saradc_wakeup_over_upper_th : RO; bitpos: [16]; default: 0;
|
||||
* reg_wakeup_over_upper_th
|
||||
*/
|
||||
uint32_t saradc_wakeup_over_upper_th:1;
|
||||
/** saradc_wakeup_mode : R/W; bitpos: [17]; default: 0;
|
||||
* reg_wakeup_mode
|
||||
*/
|
||||
uint32_t saradc_wakeup_mode:1;
|
||||
/** saradc_wakeup_en : R/W; bitpos: [18]; default: 0;
|
||||
* reg_wakeup_en
|
||||
*/
|
||||
uint32_t saradc_wakeup_en:1;
|
||||
uint32_t reserved_19:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_wake_reg_t;
|
||||
|
||||
/** Type of tsens_sample register
|
||||
* digital tsens configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_tsens_sample_rate : R/W; bitpos: [15:0]; default: 20;
|
||||
* HW sample rate
|
||||
*/
|
||||
uint32_t saradc_tsens_sample_rate:16;
|
||||
/** saradc_tsens_sample_en : R/W; bitpos: [16]; default: 0;
|
||||
* HW sample en
|
||||
*/
|
||||
uint32_t saradc_tsens_sample_en:1;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_sample_reg_t;
|
||||
|
||||
/** Type of saradc_ctrl_date register
|
||||
* version
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** saradc_date : R/W; bitpos: [31:0]; default: 35676736;
|
||||
* version
|
||||
*/
|
||||
uint32_t saradc_date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} adc_ctrl_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile adc_ctrl_reg_t saradc_ctrl;
|
||||
volatile adc_ctrl2_reg_t saradc_ctrl2;
|
||||
volatile adc_filter_ctrl1_reg_t saradc_filter_ctrl1;
|
||||
volatile adc_fsm_wait_reg_t saradc_fsm_wait;
|
||||
volatile adc_sar1_status_reg_t saradc_sar1_status;
|
||||
volatile adc_sar2_status_reg_t saradc_sar2_status;
|
||||
volatile adc_sar_patt_tab1_reg_t saradc_sar_patt_tab1;
|
||||
volatile adc_sar_patt_tab2_reg_t saradc_sar_patt_tab2;
|
||||
volatile adc_onetime_sample_reg_t saradc_onetime_sample;
|
||||
volatile adc_arb_ctrl_reg_t saradc_arb_ctrl;
|
||||
volatile adc_filter_ctrl0_reg_t saradc_filter_ctrl0;
|
||||
volatile adc_sar1data_status_reg_t saradc_sar1data_status;
|
||||
volatile adc_sar2data_status_reg_t saradc_sar2data_status;
|
||||
volatile adc_thres0_ctrl_reg_t saradc_thres0_ctrl;
|
||||
volatile adc_thres1_ctrl_reg_t saradc_thres1_ctrl;
|
||||
volatile adc_thres_ctrl_reg_t saradc_thres_ctrl;
|
||||
volatile adc_int_ena_reg_t saradc_int_ena;
|
||||
volatile adc_int_raw_reg_t saradc_int_raw;
|
||||
volatile adc_int_st_reg_t saradc_int_st;
|
||||
volatile adc_int_clr_reg_t saradc_int_clr;
|
||||
volatile adc_dma_conf_reg_t saradc_dma_conf;
|
||||
volatile adc_clkm_conf_reg_t saradc_clkm_conf;
|
||||
volatile adc_apb_tsens_ctrl_reg_t saradc_apb_tsens_ctrl;
|
||||
volatile adc_tsens_ctrl2_reg_t saradc_tsens_ctrl2;
|
||||
volatile adc_cali_reg_t saradc_cali;
|
||||
volatile apb_tsens_wake_reg_t tsens_wake;
|
||||
volatile apb_tsens_sample_reg_t tsens_sample;
|
||||
uint32_t reserved_06c[228];
|
||||
volatile adc_ctrl_date_reg_t saradc_ctrl_date;
|
||||
} adc_dev_t;
|
||||
|
||||
extern adc_dev_t ADC;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,964 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** GPIO_EXT_CLOCK_GATE_REG register
|
||||
* Clock Gating Configure Register
|
||||
*/
|
||||
#define GPIO_EXT_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x0)
|
||||
/** GPIO_EXT_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Clock enable bit of configuration registers for sigma delta modulation.
|
||||
*/
|
||||
#define GPIO_EXT_CLK_EN (BIT(0))
|
||||
#define GPIO_EXT_CLK_EN_M (GPIO_EXT_CLK_EN_V << GPIO_EXT_CLK_EN_S)
|
||||
#define GPIO_EXT_CLK_EN_V 0x00000001U
|
||||
#define GPIO_EXT_CLK_EN_S 0
|
||||
|
||||
/** GPIO_EXT_PAD_COMP_CONFIG_0_REG register
|
||||
* Configuration register for zero-crossing detection
|
||||
*/
|
||||
#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58)
|
||||
/** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the function of analog PAD voltage comparator.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_XPD_COMP_0 (BIT(0))
|
||||
#define GPIO_EXT_XPD_COMP_0_M (GPIO_EXT_XPD_COMP_0_V << GPIO_EXT_XPD_COMP_0_S)
|
||||
#define GPIO_EXT_XPD_COMP_0_V 0x00000001U
|
||||
#define GPIO_EXT_XPD_COMP_0_S 0
|
||||
/** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0;
|
||||
* Configures the reference voltage for analog PAD voltage comparater.. \\
|
||||
* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
|
||||
* used as a regular GPIO\\
|
||||
* 1: Reference voltage is the voltage on the GPIO8 PAD\\
|
||||
*/
|
||||
#define GPIO_EXT_MODE_COMP_0 (BIT(1))
|
||||
#define GPIO_EXT_MODE_COMP_0_M (GPIO_EXT_MODE_COMP_0_V << GPIO_EXT_MODE_COMP_0_S)
|
||||
#define GPIO_EXT_MODE_COMP_0_V 0x00000001U
|
||||
#define GPIO_EXT_MODE_COMP_0_S 1
|
||||
/** GPIO_EXT_DREF_COMP_0 : R/W; bitpos: [4:2]; default: 0;
|
||||
* Configures the internal reference voltage for analog PAD voltage coparator. \\
|
||||
* 0: Internal reference voltage is 0 * VDDPST1\\
|
||||
* 1: Internal reference voltage is 0.1 * VDDPST1\\
|
||||
* ......\\
|
||||
* 6: Internal reference voltage is 0.6 * VDDPST1\\
|
||||
* 7: Internal reference voltage is 0.7 * VDDPST1\\
|
||||
*/
|
||||
#define GPIO_EXT_DREF_COMP_0 0x00000007U
|
||||
#define GPIO_EXT_DREF_COMP_0_M (GPIO_EXT_DREF_COMP_0_V << GPIO_EXT_DREF_COMP_0_S)
|
||||
#define GPIO_EXT_DREF_COMP_0_V 0x00000007U
|
||||
#define GPIO_EXT_DREF_COMP_0_S 2
|
||||
|
||||
/** GPIO_EXT_PAD_COMP_FILTER_0_REG register
|
||||
* Configuration register for interrupt source mask period of zero-crossing detection
|
||||
*/
|
||||
#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c)
|
||||
/** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the period of masking new interrupt source foe analog PAD voltage
|
||||
* comparator.\\
|
||||
* Measurement unit: IO MUX operating clock cycle\\
|
||||
*/
|
||||
#define GPIO_EXT_ZERO_DET_FILTER_CNT_0 0xFFFFFFFFU
|
||||
#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_M (GPIO_EXT_ZERO_DET_FILTER_CNT_0_V << GPIO_EXT_ZERO_DET_FILTER_CNT_0_S)
|
||||
#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_V 0xFFFFFFFFU
|
||||
#define GPIO_EXT_ZERO_DET_FILTER_CNT_0_S 0
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118)
|
||||
/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c)
|
||||
/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120)
|
||||
/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124)
|
||||
/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128)
|
||||
/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c)
|
||||
/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130)
|
||||
/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134)
|
||||
/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S)
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000001FU
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0
|
||||
/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7))
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S)
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7
|
||||
|
||||
/** GPIO_EXT_ETM_TASK_P0_CFG_REG register
|
||||
* GPIO selection register 0 for ETM
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158)
|
||||
/** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO0.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 0
|
||||
/** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO0 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(5))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO0_EN_S 5
|
||||
/** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO1.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 6
|
||||
/** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO1 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(11))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO1_EN_S 11
|
||||
/** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO2.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 12
|
||||
/** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO2 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(17))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO2_EN_S 17
|
||||
/** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO3.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 18
|
||||
/** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO3 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(23))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO3_EN_S 23
|
||||
/** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO4.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 24
|
||||
/** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO4 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(29))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO4_EN_S 29
|
||||
|
||||
/** GPIO_EXT_ETM_TASK_P1_CFG_REG register
|
||||
* GPIO selection register 1 for ETM
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c)
|
||||
/** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO5.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 0
|
||||
/** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO5 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(5))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO5_EN_S 5
|
||||
/** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO6.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 6
|
||||
/** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO6 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(11))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO6_EN_S 11
|
||||
/** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO7.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 12
|
||||
/** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO7 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(17))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO7_EN_S 17
|
||||
/** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO8.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 18
|
||||
/** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO8 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(23))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO8_EN_S 23
|
||||
/** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO9.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 24
|
||||
/** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO9 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(29))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO9_EN_S 29
|
||||
|
||||
/** GPIO_EXT_ETM_TASK_P2_CFG_REG register
|
||||
* GPIO selection register 2 for ETM
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160)
|
||||
/** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO10.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 0
|
||||
/** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO10 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(5))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO10_EN_S 5
|
||||
/** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO11.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 6
|
||||
/** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO11 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(11))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO11_EN_S 11
|
||||
/** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO12.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 12
|
||||
/** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO12 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(17))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO12_EN_S 17
|
||||
/** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO13.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 18
|
||||
/** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO13 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(23))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO13_EN_S 23
|
||||
/** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO14.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 24
|
||||
/** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO14 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(29))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO14_EN_S 29
|
||||
|
||||
/** GPIO_EXT_ETM_TASK_P3_CFG_REG register
|
||||
* GPIO selection register 3 for ETM
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164)
|
||||
/** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO15.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 0
|
||||
/** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO15 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(5))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO15_EN_S 5
|
||||
/** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO16.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 6
|
||||
/** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO16 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(11))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO16_EN_S 11
|
||||
/** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO17.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 12
|
||||
/** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO17 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(17))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO17_EN_S 17
|
||||
/** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO18.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 18
|
||||
/** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO18 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(23))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO18_EN_S 23
|
||||
/** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO19.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 24
|
||||
/** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO19 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(29))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO19_EN_S 29
|
||||
|
||||
/** GPIO_EXT_ETM_TASK_P4_CFG_REG register
|
||||
* GPIO selection register 4 for ETM
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168)
|
||||
/** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO20.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 0
|
||||
/** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO20 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(5))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO20_EN_S 5
|
||||
/** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO21.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 6
|
||||
/** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO21 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(11))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO21_EN_S 11
|
||||
/** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO22.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 12
|
||||
/** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO22 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(17))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO22_EN_S 17
|
||||
/** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO23.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 18
|
||||
/** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO23 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(23))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO23_EN_S 23
|
||||
/** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO24.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 24
|
||||
/** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO24 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(29))
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S)
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U
|
||||
#define GPIO_EXT_ETM_TASK_GPIO24_EN_S 29
|
||||
|
||||
/** GPIO_EXT_INT_RAW_REG register
|
||||
* GPIO_EXT interrupt raw register
|
||||
*/
|
||||
#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0)
|
||||
/** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt raw
|
||||
*/
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_RAW (BIT(0))
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_RAW_M (GPIO_EXT_COMP_NEG_0_INT_RAW_V << GPIO_EXT_COMP_NEG_0_INT_RAW_S)
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_RAW_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_RAW_S 0
|
||||
/** GPIO_EXT_COMP_POS_0_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt raw
|
||||
*/
|
||||
#define GPIO_EXT_COMP_POS_0_INT_RAW (BIT(1))
|
||||
#define GPIO_EXT_COMP_POS_0_INT_RAW_M (GPIO_EXT_COMP_POS_0_INT_RAW_V << GPIO_EXT_COMP_POS_0_INT_RAW_S)
|
||||
#define GPIO_EXT_COMP_POS_0_INT_RAW_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_POS_0_INT_RAW_S 1
|
||||
/** GPIO_EXT_COMP_ALL_0_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt raw
|
||||
*/
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_RAW (BIT(2))
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_RAW_M (GPIO_EXT_COMP_ALL_0_INT_RAW_V << GPIO_EXT_COMP_ALL_0_INT_RAW_S)
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_RAW_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_RAW_S 2
|
||||
|
||||
/** GPIO_EXT_INT_ST_REG register
|
||||
* GPIO_EXT interrupt masked register
|
||||
*/
|
||||
#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4)
|
||||
/** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt status
|
||||
*/
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ST (BIT(0))
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ST_M (GPIO_EXT_COMP_NEG_0_INT_ST_V << GPIO_EXT_COMP_NEG_0_INT_ST_S)
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ST_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ST_S 0
|
||||
/** GPIO_EXT_COMP_POS_0_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt status
|
||||
*/
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ST (BIT(1))
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ST_M (GPIO_EXT_COMP_POS_0_INT_ST_V << GPIO_EXT_COMP_POS_0_INT_ST_S)
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ST_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ST_S 1
|
||||
/** GPIO_EXT_COMP_ALL_0_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt status
|
||||
*/
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ST (BIT(2))
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ST_M (GPIO_EXT_COMP_ALL_0_INT_ST_V << GPIO_EXT_COMP_ALL_0_INT_ST_S)
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ST_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ST_S 2
|
||||
|
||||
/** GPIO_EXT_INT_ENA_REG register
|
||||
* GPIO_EXT interrupt enable register
|
||||
*/
|
||||
#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8)
|
||||
/** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1;
|
||||
* analog comparator pos edge interrupt enable
|
||||
*/
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ENA (BIT(0))
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ENA_M (GPIO_EXT_COMP_NEG_0_INT_ENA_V << GPIO_EXT_COMP_NEG_0_INT_ENA_S)
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ENA_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_ENA_S 0
|
||||
/** GPIO_EXT_COMP_POS_0_INT_ENA : R/W; bitpos: [1]; default: 1;
|
||||
* analog comparator neg edge interrupt enable
|
||||
*/
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ENA (BIT(1))
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ENA_M (GPIO_EXT_COMP_POS_0_INT_ENA_V << GPIO_EXT_COMP_POS_0_INT_ENA_S)
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ENA_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_POS_0_INT_ENA_S 1
|
||||
/** GPIO_EXT_COMP_ALL_0_INT_ENA : R/W; bitpos: [2]; default: 1;
|
||||
* analog comparator neg or pos edge interrupt enable
|
||||
*/
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ENA (BIT(2))
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ENA_M (GPIO_EXT_COMP_ALL_0_INT_ENA_V << GPIO_EXT_COMP_ALL_0_INT_ENA_S)
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ENA_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_ENA_S 2
|
||||
|
||||
/** GPIO_EXT_INT_CLR_REG register
|
||||
* GPIO_EXT interrupt clear register
|
||||
*/
|
||||
#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc)
|
||||
/** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt clear
|
||||
*/
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_CLR (BIT(0))
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_CLR_M (GPIO_EXT_COMP_NEG_0_INT_CLR_V << GPIO_EXT_COMP_NEG_0_INT_CLR_S)
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_CLR_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_NEG_0_INT_CLR_S 0
|
||||
/** GPIO_EXT_COMP_POS_0_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt clear
|
||||
*/
|
||||
#define GPIO_EXT_COMP_POS_0_INT_CLR (BIT(1))
|
||||
#define GPIO_EXT_COMP_POS_0_INT_CLR_M (GPIO_EXT_COMP_POS_0_INT_CLR_V << GPIO_EXT_COMP_POS_0_INT_CLR_S)
|
||||
#define GPIO_EXT_COMP_POS_0_INT_CLR_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_POS_0_INT_CLR_S 1
|
||||
/** GPIO_EXT_COMP_ALL_0_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt clear
|
||||
*/
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_CLR (BIT(2))
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_CLR_M (GPIO_EXT_COMP_ALL_0_INT_CLR_V << GPIO_EXT_COMP_ALL_0_INT_CLR_S)
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_CLR_V 0x00000001U
|
||||
#define GPIO_EXT_COMP_ALL_0_INT_CLR_S 2
|
||||
|
||||
/** GPIO_EXT_PIN_CTRL_REG register
|
||||
* Clock Output Configuration Register
|
||||
*/
|
||||
#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0)
|
||||
/** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
|
||||
* CLK_OUT_out1 can be found in peripheral output signals.
|
||||
*/
|
||||
#define GPIO_EXT_CLK_OUT1 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT1_M (GPIO_EXT_CLK_OUT1_V << GPIO_EXT_CLK_OUT1_S)
|
||||
#define GPIO_EXT_CLK_OUT1_V 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT1_S 0
|
||||
/** GPIO_EXT_CLK_OUT2 : R/W; bitpos: [9:5]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
|
||||
* CLK_OUT_out2 can be found in peripheral output signals.
|
||||
*/
|
||||
#define GPIO_EXT_CLK_OUT2 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT2_M (GPIO_EXT_CLK_OUT2_V << GPIO_EXT_CLK_OUT2_S)
|
||||
#define GPIO_EXT_CLK_OUT2_V 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT2_S 5
|
||||
/** GPIO_EXT_CLK_OUT3 : R/W; bitpos: [14:10]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
|
||||
* CLK_OUT_out3 can be found in peripheral output signals.
|
||||
*/
|
||||
#define GPIO_EXT_CLK_OUT3 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT3_M (GPIO_EXT_CLK_OUT3_V << GPIO_EXT_CLK_OUT3_S)
|
||||
#define GPIO_EXT_CLK_OUT3_V 0x0000001FU
|
||||
#define GPIO_EXT_CLK_OUT3_S 10
|
||||
|
||||
/** GPIO_EXT_VERSION_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc)
|
||||
/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37753392;
|
||||
* Version control register.
|
||||
*/
|
||||
#define GPIO_EXT_DATE 0x0FFFFFFFU
|
||||
#define GPIO_EXT_DATE_M (GPIO_EXT_DATE_V << GPIO_EXT_DATE_S)
|
||||
#define GPIO_EXT_DATE_V 0x0FFFFFFFU
|
||||
#define GPIO_EXT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,693 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Clock gate Register */
|
||||
/** Type of clock_gate register
|
||||
* Clock Gating Configure Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* Clock enable bit of configuration registers for sigma delta modulation.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Configure Registers */
|
||||
/** Type of pad_comp_config_0 register
|
||||
* Configuration register for zero-crossing detection
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** xpd_comp_0 : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the function of analog PAD voltage comparator.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t xpd_comp_0:1;
|
||||
/** mode_comp_0 : R/W; bitpos: [1]; default: 0;
|
||||
* Configures the reference voltage for analog PAD voltage comparater.. \\
|
||||
* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
|
||||
* used as a regular GPIO\\
|
||||
* 1: Reference voltage is the voltage on the GPIO8 PAD\\
|
||||
*/
|
||||
uint32_t mode_comp_0:1;
|
||||
/** dref_comp_0 : R/W; bitpos: [4:2]; default: 0;
|
||||
* Configures the internal reference voltage for analog PAD voltage coparator. \\
|
||||
* 0: Internal reference voltage is 0 * VDDPST1\\
|
||||
* 1: Internal reference voltage is 0.1 * VDDPST1\\
|
||||
* ......\\
|
||||
* 6: Internal reference voltage is 0.6 * VDDPST1\\
|
||||
* 7: Internal reference voltage is 0.7 * VDDPST1\\
|
||||
*/
|
||||
uint32_t dref_comp_0:3;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_pad_comp_config_0_reg_t;
|
||||
|
||||
/** Type of pad_comp_filter_0 register
|
||||
* Configuration register for interrupt source mask period of zero-crossing detection
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the period of masking new interrupt source foe analog PAD voltage
|
||||
* comparator.\\
|
||||
* Measurement unit: IO MUX operating clock cycle\\
|
||||
*/
|
||||
uint32_t zero_det_filter_cnt_0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_pad_comp_filter_0_reg_t;
|
||||
|
||||
/** Type of pin_ctrl register
|
||||
* Clock Output Configuration Register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_out1 : R/W; bitpos: [4:0]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
|
||||
* CLK_OUT_out1 can be found in peripheral output signals.
|
||||
*/
|
||||
uint32_t clk_out1:5;
|
||||
/** clk_out2 : R/W; bitpos: [9:5]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
|
||||
* CLK_OUT_out2 can be found in peripheral output signals.
|
||||
*/
|
||||
uint32_t clk_out2:5;
|
||||
/** clk_out3 : R/W; bitpos: [14:10]; default: 0;
|
||||
* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
|
||||
* CLK_OUT_out3 can be found in peripheral output signals.
|
||||
*/
|
||||
uint32_t clk_out3:5;
|
||||
uint32_t reserved_15:17;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_pin_ctrl_reg_t;
|
||||
|
||||
|
||||
/** Group: ETM Configuration Registers */
|
||||
/** Type of etm_event_chn_cfg register
|
||||
* ETM configuration register for channel 0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0;
|
||||
* Configures to select GPIO for ETM event channel.\\
|
||||
* 0: Select GPIO0\\
|
||||
* 1: Select GPIO1\\
|
||||
* ......\\
|
||||
* 23: Select GPIO23\\
|
||||
* 24: Select GPIO24\\
|
||||
* 25 ~ 31: Reserved\\
|
||||
*/
|
||||
uint32_t etm_chn_event_sel:5;
|
||||
uint32_t reserved_5:2;
|
||||
/** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable ETM event send.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_chn_event_en:1;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_event_chn_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_p0_cfg register
|
||||
* GPIO selection register 0 for ETM
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO0.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio0_sel:3;
|
||||
uint32_t reserved_3:2;
|
||||
/** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO0 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio0_en:1;
|
||||
/** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO1.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio1_sel:3;
|
||||
uint32_t reserved_9:2;
|
||||
/** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO1 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio1_en:1;
|
||||
/** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO2.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio2_sel:3;
|
||||
uint32_t reserved_15:2;
|
||||
/** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO2 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio2_en:1;
|
||||
/** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO3.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio3_sel:3;
|
||||
uint32_t reserved_21:2;
|
||||
/** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO3 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio3_en:1;
|
||||
/** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO4.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio4_sel:3;
|
||||
uint32_t reserved_27:2;
|
||||
/** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO4 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio4_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_p0_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_p1_cfg register
|
||||
* GPIO selection register 1 for ETM
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO5.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio5_sel:3;
|
||||
uint32_t reserved_3:2;
|
||||
/** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO5 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio5_en:1;
|
||||
/** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO6.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio6_sel:3;
|
||||
uint32_t reserved_9:2;
|
||||
/** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO6 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio6_en:1;
|
||||
/** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO7.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio7_sel:3;
|
||||
uint32_t reserved_15:2;
|
||||
/** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO7 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio7_en:1;
|
||||
/** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO8.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio8_sel:3;
|
||||
uint32_t reserved_21:2;
|
||||
/** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO8 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio8_en:1;
|
||||
/** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO9.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio9_sel:3;
|
||||
uint32_t reserved_27:2;
|
||||
/** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO9 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio9_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_p1_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_p2_cfg register
|
||||
* GPIO selection register 2 for ETM
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO10.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio10_sel:3;
|
||||
uint32_t reserved_3:2;
|
||||
/** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO10 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio10_en:1;
|
||||
/** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO11.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio11_sel:3;
|
||||
uint32_t reserved_9:2;
|
||||
/** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO11 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio11_en:1;
|
||||
/** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO12.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio12_sel:3;
|
||||
uint32_t reserved_15:2;
|
||||
/** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO12 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio12_en:1;
|
||||
/** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO13.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio13_sel:3;
|
||||
uint32_t reserved_21:2;
|
||||
/** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO13 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio13_en:1;
|
||||
/** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO14.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio14_sel:3;
|
||||
uint32_t reserved_27:2;
|
||||
/** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO14 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio14_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_p2_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_p3_cfg register
|
||||
* GPIO selection register 3 for ETM
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO15.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio15_sel:3;
|
||||
uint32_t reserved_3:2;
|
||||
/** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO15 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio15_en:1;
|
||||
/** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO16.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio16_sel:3;
|
||||
uint32_t reserved_9:2;
|
||||
/** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO16 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio16_en:1;
|
||||
/** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO17.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio17_sel:3;
|
||||
uint32_t reserved_15:2;
|
||||
/** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO17 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio17_en:1;
|
||||
/** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO18.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio18_sel:3;
|
||||
uint32_t reserved_21:2;
|
||||
/** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO18 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio18_en:1;
|
||||
/** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO19.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio19_sel:3;
|
||||
uint32_t reserved_27:2;
|
||||
/** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO19 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio19_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_p3_cfg_reg_t;
|
||||
|
||||
/** Type of etm_task_p4_cfg register
|
||||
* GPIO selection register 4 for ETM
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO20.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio20_sel:3;
|
||||
uint32_t reserved_3:2;
|
||||
/** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0;
|
||||
* Configures whether or not to enable GPIO20 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio20_en:1;
|
||||
/** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO21.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio21_sel:3;
|
||||
uint32_t reserved_9:2;
|
||||
/** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0;
|
||||
* Configures whether or not to enable GPIO21 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio21_en:1;
|
||||
/** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO22.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio22_sel:3;
|
||||
uint32_t reserved_15:2;
|
||||
/** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0;
|
||||
* Configures whether or not to enable GPIO22 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio22_en:1;
|
||||
/** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO23.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio23_sel:3;
|
||||
uint32_t reserved_21:2;
|
||||
/** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable GPIO23 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio23_en:1;
|
||||
/** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0;
|
||||
* Configures to select an ETM task channel for GPIO24.\\
|
||||
* 0: Select channel 0\\
|
||||
* 1: Select channel 1\\
|
||||
* ......\\
|
||||
* 7: Select channel 7\\
|
||||
*/
|
||||
uint32_t etm_task_gpio24_sel:3;
|
||||
uint32_t reserved_27:2;
|
||||
/** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable GPIO24 to response ETM task.\\
|
||||
* 0: Not enable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_task_gpio24_en:1;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_etm_task_p4_cfg_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of int_raw register
|
||||
* GPIO_EXT interrupt raw register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp_neg_0_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt raw
|
||||
*/
|
||||
uint32_t comp_neg_0_int_raw:1;
|
||||
/** comp_pos_0_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt raw
|
||||
*/
|
||||
uint32_t comp_pos_0_int_raw:1;
|
||||
/** comp_all_0_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt raw
|
||||
*/
|
||||
uint32_t comp_all_0_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* GPIO_EXT interrupt masked register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp_neg_0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt status
|
||||
*/
|
||||
uint32_t comp_neg_0_int_st:1;
|
||||
/** comp_pos_0_int_st : RO; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt status
|
||||
*/
|
||||
uint32_t comp_pos_0_int_st:1;
|
||||
/** comp_all_0_int_st : RO; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt status
|
||||
*/
|
||||
uint32_t comp_all_0_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* GPIO_EXT interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp_neg_0_int_ena : R/W; bitpos: [0]; default: 1;
|
||||
* analog comparator pos edge interrupt enable
|
||||
*/
|
||||
uint32_t comp_neg_0_int_ena:1;
|
||||
/** comp_pos_0_int_ena : R/W; bitpos: [1]; default: 1;
|
||||
* analog comparator neg edge interrupt enable
|
||||
*/
|
||||
uint32_t comp_pos_0_int_ena:1;
|
||||
/** comp_all_0_int_ena : R/W; bitpos: [2]; default: 1;
|
||||
* analog comparator neg or pos edge interrupt enable
|
||||
*/
|
||||
uint32_t comp_all_0_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* GPIO_EXT interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** comp_neg_0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* analog comparator pos edge interrupt clear
|
||||
*/
|
||||
uint32_t comp_neg_0_int_clr:1;
|
||||
/** comp_pos_0_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* analog comparator neg edge interrupt clear
|
||||
*/
|
||||
uint32_t comp_pos_0_int_clr:1;
|
||||
/** comp_all_0_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* analog comparator neg or pos edge interrupt clear
|
||||
*/
|
||||
uint32_t comp_all_0_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of version register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 37753392;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_ext_version_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile gpio_ext_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_004[21];
|
||||
volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
|
||||
volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
|
||||
uint32_t reserved_060[46];
|
||||
volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
|
||||
uint32_t reserved_138[8];
|
||||
volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
|
||||
volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
|
||||
volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
|
||||
volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
|
||||
volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
|
||||
uint32_t reserved_16c[25];
|
||||
volatile gpio_ext_int_raw_reg_t int_raw;
|
||||
volatile gpio_ext_int_st_reg_t int_st;
|
||||
volatile gpio_ext_int_ena_reg_t int_ena;
|
||||
volatile gpio_ext_int_clr_reg_t int_clr;
|
||||
volatile gpio_ext_pin_ctrl_reg_t pin_ctrl;
|
||||
uint32_t reserved_1e4[6];
|
||||
volatile gpio_ext_version_reg_t version;
|
||||
} gpio_ext_dev_t;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define EXT_ADC_START_IDX 0
|
||||
#define LEDC_LS_SIG_OUT0_IDX 0
|
||||
#define LEDC_LS_SIG_OUT1_IDX 1
|
||||
#define LEDC_LS_SIG_OUT2_IDX 2
|
||||
#define LEDC_LS_SIG_OUT3_IDX 3
|
||||
#define LEDC_LS_SIG_OUT4_IDX 4
|
||||
#define LEDC_LS_SIG_OUT5_IDX 5
|
||||
#define U0RXD_IN_IDX 6
|
||||
#define U0TXD_OUT_IDX 6
|
||||
#define U0CTS_IN_IDX 7
|
||||
#define U0RTS_OUT_IDX 7
|
||||
#define U0DSR_IN_IDX 8
|
||||
#define U0DTR_OUT_IDX 8
|
||||
#define U1RXD_IN_IDX 9
|
||||
#define U1TXD_OUT_IDX 9
|
||||
#define U1CTS_IN_IDX 10
|
||||
#define U1RTS_OUT_IDX 10
|
||||
#define U1DSR_IN_IDX 11
|
||||
#define U1DTR_OUT_IDX 11
|
||||
#define I2S_MCLK_IN_IDX 12
|
||||
#define I2S_MCLK_OUT_IDX 12
|
||||
#define I2SO_BCK_IN_IDX 13
|
||||
#define I2SO_BCK_OUT_IDX 13
|
||||
#define I2SO_WS_IN_IDX 14
|
||||
#define I2SO_WS_OUT_IDX 14
|
||||
#define I2SI_SD_IN_IDX 15
|
||||
#define I2SO_SD_OUT_IDX 15
|
||||
#define I2SI_BCK_IN_IDX 16
|
||||
#define I2SI_BCK_OUT_IDX 16
|
||||
#define I2SI_WS_IN_IDX 17
|
||||
#define I2SI_WS_OUT_IDX 17
|
||||
#define I2SO_SD1_OUT_IDX 18
|
||||
#define CPU_TESTBUS0_IDX 19
|
||||
#define CPU_TESTBUS1_IDX 20
|
||||
#define CPU_TESTBUS2_IDX 21
|
||||
#define CPU_TESTBUS3_IDX 22
|
||||
#define CPU_TESTBUS4_IDX 23
|
||||
#define CPU_TESTBUS5_IDX 24
|
||||
#define CPU_TESTBUS6_IDX 25
|
||||
#define CPU_TESTBUS7_IDX 26
|
||||
#define CPU_GPIO_IN0_IDX 27
|
||||
#define CPU_GPIO_OUT0_IDX 27
|
||||
#define CPU_GPIO_IN1_IDX 28
|
||||
#define CPU_GPIO_OUT1_IDX 28
|
||||
#define CPU_GPIO_IN2_IDX 29
|
||||
#define CPU_GPIO_OUT2_IDX 29
|
||||
#define CPU_GPIO_IN3_IDX 30
|
||||
#define CPU_GPIO_OUT3_IDX 30
|
||||
#define CPU_GPIO_IN4_IDX 31
|
||||
#define CPU_GPIO_OUT4_IDX 31
|
||||
#define CPU_GPIO_IN5_IDX 32
|
||||
#define CPU_GPIO_OUT5_IDX 32
|
||||
#define CPU_GPIO_IN6_IDX 33
|
||||
#define CPU_GPIO_OUT6_IDX 33
|
||||
#define CPU_GPIO_IN7_IDX 34
|
||||
#define CPU_GPIO_OUT7_IDX 34
|
||||
#define USB_JTAG_TDO_IDX 35
|
||||
#define USB_JTAG_TRST_IDX 35
|
||||
#define USB_JTAG_SRST_IDX 36
|
||||
#define USB_JTAG_TCK_IDX 37
|
||||
#define USB_JTAG_TMS_IDX 38
|
||||
#define USB_JTAG_TDI_IDX 39
|
||||
#define CPU_USB_JTAG_TDO_IDX 40
|
||||
#define USB_EXTPHY_VP_IDX 41
|
||||
#define USB_EXTPHY_OEN_IDX 41
|
||||
#define USB_EXTPHY_VM_IDX 42
|
||||
#define USB_EXTPHY_SPEED_IDX 42
|
||||
#define USB_EXTPHY_RCV_IDX 43
|
||||
#define USB_EXTPHY_VPO_IDX 43
|
||||
#define USB_EXTPHY_VMO_IDX 44
|
||||
#define USB_EXTPHY_SUSPND_IDX 45
|
||||
#define I2CEXT0_SCL_IN_IDX 46
|
||||
#define I2CEXT0_SCL_OUT_IDX 46
|
||||
#define I2CEXT0_SDA_IN_IDX 47
|
||||
#define I2CEXT0_SDA_OUT_IDX 47
|
||||
#define ANT_SEL0_IDX 48
|
||||
#define ANT_SEL1_IDX 49
|
||||
#define ANT_SEL2_IDX 50
|
||||
#define ANT_SEL3_IDX 51
|
||||
#define ANT_SEL4_IDX 52
|
||||
#define ANT_SEL5_IDX 53
|
||||
#define ANT_SEL6_IDX 54
|
||||
#define ANT_SEL7_IDX 55
|
||||
#define ANT_SEL8_IDX 56
|
||||
#define ANT_SEL9_IDX 57
|
||||
#define ANT_SEL10_IDX 58
|
||||
#define ANT_SEL11_IDX 59
|
||||
#define ANT_SEL12_IDX 60
|
||||
#define ANT_SEL13_IDX 61
|
||||
#define ANT_SEL14_IDX 62
|
||||
#define ANT_SEL15_IDX 63
|
||||
#define FSPICLK_IN_IDX 64
|
||||
#define FSPICLK_OUT_IDX 64
|
||||
#define FSPIQ_IN_IDX 65
|
||||
#define FSPIQ_OUT_IDX 65
|
||||
#define FSPID_IN_IDX 66
|
||||
#define FSPID_OUT_IDX 66
|
||||
#define FSPIHD_IN_IDX 67
|
||||
#define FSPIHD_OUT_IDX 67
|
||||
#define FSPIWP_IN_IDX 68
|
||||
#define FSPIWP_OUT_IDX 68
|
||||
#define FSPICS0_IN_IDX 69
|
||||
#define FSPICS0_OUT_IDX 69
|
||||
#define U2RXD_IN_IDX 72
|
||||
#define U2TXD_OUT_IDX 72
|
||||
#define U2CTS_IN_IDX 73
|
||||
#define U2RTS_OUT_IDX 73
|
||||
#define U2DSR_IN_IDX 74
|
||||
#define U2DTR_OUT_IDX 74
|
||||
#define EXTERN_PRIORITY_I_IDX 82
|
||||
#define EXTERN_PRIORITY_O_IDX 82
|
||||
#define EXTERN_ACTIVE_I_IDX 83
|
||||
#define EXTERN_ACTIVE_O_IDX 83
|
||||
#define SIG_IN_FUNC97_IDX 97
|
||||
#define SIG_IN_FUNC97_IDX 97
|
||||
#define SIG_IN_FUNC98_IDX 98
|
||||
#define SIG_IN_FUNC98_IDX 98
|
||||
#define SIG_IN_FUNC99_IDX 99
|
||||
#define SIG_IN_FUNC99_IDX 99
|
||||
#define SIG_IN_FUNC100_IDX 100
|
||||
#define SIG_IN_FUNC100_IDX 100
|
||||
#define FSPICS1_OUT_IDX 102
|
||||
#define FSPICS2_OUT_IDX 103
|
||||
#define FSPICS3_OUT_IDX 104
|
||||
#define FSPICS4_OUT_IDX 105
|
||||
#define FSPICS5_OUT_IDX 106
|
||||
#define GPIO_EVENT_MATRIX_IN0_IDX 118
|
||||
#define GPIO_TASK_MATRIX_OUT0_IDX 118
|
||||
#define GPIO_EVENT_MATRIX_IN1_IDX 119
|
||||
#define GPIO_TASK_MATRIX_OUT1_IDX 119
|
||||
#define GPIO_EVENT_MATRIX_IN2_IDX 120
|
||||
#define GPIO_TASK_MATRIX_OUT2_IDX 120
|
||||
#define GPIO_EVENT_MATRIX_IN3_IDX 121
|
||||
#define GPIO_TASK_MATRIX_OUT3_IDX 121
|
||||
#define CLK_OUT_OUT1_IDX 126
|
||||
#define CLK_OUT_OUT2_IDX 127
|
||||
#define CLK_OUT_OUT3_IDX 128
|
||||
#define MODEM_DIAG0_IDX 129
|
||||
#define MODEM_DIAG1_IDX 130
|
||||
#define MODEM_DIAG2_IDX 131
|
||||
#define MODEM_DIAG3_IDX 132
|
||||
#define MODEM_DIAG4_IDX 133
|
||||
#define MODEM_DIAG5_IDX 134
|
||||
#define MODEM_DIAG6_IDX 135
|
||||
#define MODEM_DIAG7_IDX 136
|
||||
#define MODEM_DIAG8_IDX 137
|
||||
#define MODEM_DIAG9_IDX 138
|
||||
#define MODEM_DIAG10_IDX 139
|
||||
#define MODEM_DIAG11_IDX 140
|
||||
#define MODEM_DIAG12_IDX 141
|
||||
#define MODEM_DIAG13_IDX 142
|
||||
#define MODEM_DIAG14_IDX 143
|
||||
#define MODEM_DIAG15_IDX 144
|
||||
#define MODEM_DIAG16_IDX 145
|
||||
#define MODEM_DIAG17_IDX 146
|
||||
#define MODEM_DIAG18_IDX 147
|
||||
#define MODEM_DIAG19_IDX 148
|
||||
#define MODEM_DIAG20_IDX 149
|
||||
#define MODEM_DIAG21_IDX 150
|
||||
#define MODEM_DIAG22_IDX 151
|
||||
#define MODEM_DIAG23_IDX 152
|
||||
#define MODEM_DIAG24_IDX 153
|
||||
#define MODEM_DIAG25_IDX 154
|
||||
#define MODEM_DIAG26_IDX 155
|
||||
#define MODEM_DIAG27_IDX 156
|
||||
#define MODEM_DIAG28_IDX 157
|
||||
#define MODEM_DIAG29_IDX 158
|
||||
#define MODEM_DIAG30_IDX 159
|
||||
#define MODEM_DIAG31_IDX 160
|
||||
// version date 2310090
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,441 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
|
||||
* External device encryption/decryption configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0)
|
||||
/** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0))
|
||||
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
|
||||
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0
|
||||
/** HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1))
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1
|
||||
/** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS auto decryption in download boot
|
||||
* mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2))
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001U
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2
|
||||
/** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS manual encryption in download boot
|
||||
* mode. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3))
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3
|
||||
|
||||
/** HP_SYSTEM_SRAM_USAGE_CONF_REG register
|
||||
* HP memory usage configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4)
|
||||
/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_CACHE_USAGE (BIT(0))
|
||||
#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S)
|
||||
#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U
|
||||
#define HP_SYSTEM_CACHE_USAGE_S 0
|
||||
/** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [12:8]; default: 0;
|
||||
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
|
||||
*/
|
||||
#define HP_SYSTEM_SRAM_USAGE 0x0000001FU
|
||||
#define HP_SYSTEM_SRAM_USAGE_M (HP_SYSTEM_SRAM_USAGE_V << HP_SYSTEM_SRAM_USAGE_S)
|
||||
#define HP_SYSTEM_SRAM_USAGE_V 0x0000001FU
|
||||
#define HP_SYSTEM_SRAM_USAGE_S 8
|
||||
/** HP_SYSTEM_MAC_DUMP_ALLOC : R/W; bitpos: [16]; default: 0;
|
||||
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
|
||||
*/
|
||||
#define HP_SYSTEM_MAC_DUMP_ALLOC (BIT(16))
|
||||
#define HP_SYSTEM_MAC_DUMP_ALLOC_M (HP_SYSTEM_MAC_DUMP_ALLOC_V << HP_SYSTEM_MAC_DUMP_ALLOC_S)
|
||||
#define HP_SYSTEM_MAC_DUMP_ALLOC_V 0x00000001U
|
||||
#define HP_SYSTEM_MAC_DUMP_ALLOC_S 16
|
||||
|
||||
/** HP_SYSTEM_SEC_DPA_CONF_REG register
|
||||
* HP anti-DPA security configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8)
|
||||
/** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0;
|
||||
* Configures whether or not to enable anti-DPA attack. Valid only when
|
||||
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
|
||||
* 0: Disable\\
|
||||
* 1-3: Enable. The larger the number, the higher the security level, which represents
|
||||
* the ability to resist DPA attacks, with increased computational overhead of the
|
||||
* hardware crypto-accelerators at the same time. \\
|
||||
*/
|
||||
#define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U
|
||||
#define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S)
|
||||
#define HP_SYSTEM_SEC_DPA_LEVEL_V 0x00000003U
|
||||
#define HP_SYSTEM_SEC_DPA_LEVEL_S 0
|
||||
/** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0;
|
||||
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
|
||||
* eFuse) to control DPA level. \\
|
||||
* 0: Select EFUSE_SEC_DPA_LEVEL\\
|
||||
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
|
||||
*/
|
||||
#define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2))
|
||||
#define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S)
|
||||
#define HP_SYSTEM_SEC_DPA_CFG_SEL_V 0x00000001U
|
||||
#define HP_SYSTEM_SEC_DPA_CFG_SEL_S 2
|
||||
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG register
|
||||
* CPU_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0xc)
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Configures the timeout threshold for bus access for accessing CPU peripheral
|
||||
* register in the number of clock cycles of the clock domain.
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES 0x0000FFFFU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_M (HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V << HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S)
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_V 0x0000FFFFU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_THRES_S 0
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
|
||||
* Write 1 to clear timeout interrupt.
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR (BIT(16))
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S)
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
|
||||
* Configures whether or not to enable timeout protection for accessing CPU peripheral
|
||||
* registers.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17))
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S)
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S 17
|
||||
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG register
|
||||
* CPU_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x10)
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address information of abnormal access.
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S)
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_ADDR_S 0
|
||||
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG register
|
||||
* CPU_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x14)
|
||||
/** HP_SYSTEM_CPU_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
|
||||
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
|
||||
* register will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID 0x0000007FU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_M (HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V << HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S)
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_V 0x0000007FU
|
||||
#define HP_SYSTEM_CPU_PERI_TIMEOUT_UID_S 0
|
||||
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG register
|
||||
* HP_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x18)
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Configures the timeout threshold for bus access for accessing HP peripheral
|
||||
* register, corresponding to the number of clock cycles of the clock domain.
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES 0x0000FFFFU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_M (HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V << HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S)
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
|
||||
* Configures whether or not to clear timeout interrupt.\\
|
||||
* 0: No effect\\
|
||||
* 1: Clear timeout interrupt\\
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16))
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S)
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
|
||||
* Configures whether or not to enable timeout protection for accessing HP peripheral
|
||||
* registers.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17))
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S)
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S 17
|
||||
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG register
|
||||
* HP_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x1c)
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address information of abnormal access.
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S)
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_ADDR_S 0
|
||||
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG register
|
||||
* HP_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x20)
|
||||
/** HP_SYSTEM_HP_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
|
||||
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
|
||||
* register will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID 0x0000007FU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_M (HP_SYSTEM_HP_PERI_TIMEOUT_UID_V << HP_SYSTEM_HP_PERI_TIMEOUT_UID_S)
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU
|
||||
#define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0
|
||||
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register
|
||||
* MODEM_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24)
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Set the timeout threshold for bus access, corresponding to the number of clock
|
||||
* cycles of the clock domain.
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S)
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0;
|
||||
* Set this bit as 1 to clear timeout interrupt
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16))
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S)
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1;
|
||||
* Set this bit as 1 to enable timeout protection for accessing modem registers
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17))
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S)
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17
|
||||
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register
|
||||
* MODEM_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28)
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* Record the address information of abnormal access
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S)
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0
|
||||
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register
|
||||
* MODEM_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c)
|
||||
/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0;
|
||||
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
|
||||
* will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S)
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU
|
||||
#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0
|
||||
|
||||
/** HP_SYSTEM_ROM_TABLE_LOCK_REG register
|
||||
* ROM-Table lock register
|
||||
*/
|
||||
#define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x30)
|
||||
/** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
|
||||
* 0: Unlock \\
|
||||
* 1: Lock \\
|
||||
*/
|
||||
#define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0))
|
||||
#define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S)
|
||||
#define HP_SYSTEM_ROM_TABLE_LOCK_V 0x00000001U
|
||||
#define HP_SYSTEM_ROM_TABLE_LOCK_S 0
|
||||
|
||||
/** HP_SYSTEM_ROM_TABLE_REG register
|
||||
* ROM-Table register
|
||||
*/
|
||||
#define HP_SYSTEM_ROM_TABLE_REG (DR_REG_HP_SYSTEM_BASE + 0x34)
|
||||
/** HP_SYSTEM_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
|
||||
* Software ROM-Table register, whose content can be modified only when
|
||||
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
|
||||
*/
|
||||
#define HP_SYSTEM_ROM_TABLE 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_ROM_TABLE_M (HP_SYSTEM_ROM_TABLE_V << HP_SYSTEM_ROM_TABLE_S)
|
||||
#define HP_SYSTEM_ROM_TABLE_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_ROM_TABLE_S 0
|
||||
|
||||
/** HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG register
|
||||
* Core Debug RunStall configurion register
|
||||
*/
|
||||
#define HP_SYSTEM_CORE_DEBUG_RUNSTALL_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x38)
|
||||
/** HP_SYSTEM_CORE_RUNSTALLED : RO; bitpos: [1]; default: 0;
|
||||
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
|
||||
* not stalled.
|
||||
*/
|
||||
#define HP_SYSTEM_CORE_RUNSTALLED (BIT(1))
|
||||
#define HP_SYSTEM_CORE_RUNSTALLED_M (HP_SYSTEM_CORE_RUNSTALLED_V << HP_SYSTEM_CORE_RUNSTALLED_S)
|
||||
#define HP_SYSTEM_CORE_RUNSTALLED_V 0x00000001U
|
||||
#define HP_SYSTEM_CORE_RUNSTALLED_S 1
|
||||
|
||||
/** HP_SYSTEM_SPROM_CTRL_REG register
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPROM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x3c)
|
||||
/** HP_SYSTEM_SPROM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 112;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_M (HP_SYSTEM_SPROM_MEM_AUX_CTRL_V << HP_SYSTEM_SPROM_MEM_AUX_CTRL_S)
|
||||
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPROM_MEM_AUX_CTRL_S 0
|
||||
|
||||
/** HP_SYSTEM_SPRAM_CTRL_REG register
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPRAM_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x40)
|
||||
/** HP_SYSTEM_SPRAM_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_M (HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V << HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S)
|
||||
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPRAM_MEM_AUX_CTRL_S 0
|
||||
|
||||
/** HP_SYSTEM_SPRF_CTRL_REG register
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x44)
|
||||
/** HP_SYSTEM_SPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SPRF_MEM_AUX_CTRL_S)
|
||||
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SPRF_MEM_AUX_CTRL_S 0
|
||||
|
||||
/** HP_SYSTEM_SDPRF_CTRL_REG register
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SDPRF_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x48)
|
||||
/** HP_SYSTEM_SDPRF_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_M (HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V << HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S)
|
||||
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0
|
||||
|
||||
/** HP_SYSTEM_RND_ECO_REG register
|
||||
* redcy eco register.
|
||||
*/
|
||||
#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x4c)
|
||||
/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define HP_SYSTEM_REDCY_ENA (BIT(0))
|
||||
#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S)
|
||||
#define HP_SYSTEM_REDCY_ENA_V 0x00000001U
|
||||
#define HP_SYSTEM_REDCY_ENA_S 0
|
||||
/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define HP_SYSTEM_REDCY_RESULT (BIT(1))
|
||||
#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S)
|
||||
#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U
|
||||
#define HP_SYSTEM_REDCY_RESULT_S 1
|
||||
|
||||
/** HP_SYSTEM_RND_ECO_LOW_REG register
|
||||
* redcy eco low register.
|
||||
*/
|
||||
#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x50)
|
||||
/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S)
|
||||
#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_REDCY_LOW_S 0
|
||||
|
||||
/** HP_SYSTEM_RND_ECO_HIGH_REG register
|
||||
* redcy eco high register.
|
||||
*/
|
||||
#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x54)
|
||||
/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S)
|
||||
#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU
|
||||
#define HP_SYSTEM_REDCY_HIGH_S 0
|
||||
|
||||
/** HP_SYSTEM_DEBUG_REG register
|
||||
* HP-SYSTEM debug register
|
||||
*/
|
||||
#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x58)
|
||||
/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
#define HP_SYSTEM_FPGA_DEBUG (BIT(0))
|
||||
#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S)
|
||||
#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U
|
||||
#define HP_SYSTEM_FPGA_DEBUG_S 0
|
||||
|
||||
/** HP_SYSTEM_CLOCK_GATE_REG register
|
||||
* HP-SYSTEM clock gating configure register
|
||||
*/
|
||||
#define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x5c)
|
||||
/** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit as 1 to force on clock gating.
|
||||
*/
|
||||
#define HP_SYSTEM_CLK_EN (BIT(0))
|
||||
#define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S)
|
||||
#define HP_SYSTEM_CLK_EN_V 0x00000001U
|
||||
#define HP_SYSTEM_CLK_EN_S 0
|
||||
|
||||
/** HP_SYSTEM_DATE_REG register
|
||||
* Date control and version control register
|
||||
*/
|
||||
#define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc)
|
||||
/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36769824;
|
||||
* Version control register.
|
||||
*/
|
||||
#define HP_SYSTEM_DATE 0x0FFFFFFFU
|
||||
#define HP_SYSTEM_DATE_M (HP_SYSTEM_DATE_V << HP_SYSTEM_DATE_S)
|
||||
#define HP_SYSTEM_DATE_V 0x0FFFFFFFU
|
||||
#define HP_SYSTEM_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,489 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of external_device_encrypt_decrypt_control register
|
||||
* External device encryption/decryption configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t enable_spi_manual_encrypt:1;
|
||||
/** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t enable_download_db_encrypt:1;
|
||||
/** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS auto decryption in download boot
|
||||
* mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t enable_download_g0cb_decrypt:1;
|
||||
/** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
|
||||
* Configures whether or not to enable MSPI XTS manual encryption in download boot
|
||||
* mode. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t enable_download_manual_encrypt:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_external_device_encrypt_decrypt_control_reg_t;
|
||||
|
||||
/** Type of sram_usage_conf register
|
||||
* HP memory usage configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cache_usage : HRO; bitpos: [0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t cache_usage:1;
|
||||
uint32_t reserved_1:7;
|
||||
/** sram_usage : R/W; bitpos: [12:8]; default: 0;
|
||||
* 0: cpu use hp-memory. 1:mac-dump accessing hp-memory.
|
||||
*/
|
||||
uint32_t sram_usage:5;
|
||||
uint32_t reserved_13:3;
|
||||
/** mac_dump_alloc : R/W; bitpos: [16]; default: 0;
|
||||
* Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory.
|
||||
*/
|
||||
uint32_t mac_dump_alloc:1;
|
||||
uint32_t reserved_17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_sram_usage_conf_reg_t;
|
||||
|
||||
/** Type of sec_dpa_conf register
|
||||
* HP anti-DPA security configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sec_dpa_level : R/W; bitpos: [1:0]; default: 0;
|
||||
* Configures whether or not to enable anti-DPA attack. Valid only when
|
||||
* HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\
|
||||
* 0: Disable\\
|
||||
* 1-3: Enable. The larger the number, the higher the security level, which represents
|
||||
* the ability to resist DPA attacks, with increased computational overhead of the
|
||||
* hardware crypto-accelerators at the same time. \\
|
||||
*/
|
||||
uint32_t sec_dpa_level:2;
|
||||
/** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0;
|
||||
* Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from
|
||||
* eFuse) to control DPA level. \\
|
||||
* 0: Select EFUSE_SEC_DPA_LEVEL\\
|
||||
* 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\
|
||||
*/
|
||||
uint32_t sec_dpa_cfg_sel:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_sec_dpa_conf_reg_t;
|
||||
|
||||
/** Type of rom_table_lock register
|
||||
* ROM-Table lock register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rom_table_lock : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\
|
||||
* 0: Unlock \\
|
||||
* 1: Lock \\
|
||||
*/
|
||||
uint32_t rom_table_lock:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_rom_table_lock_reg_t;
|
||||
|
||||
/** Type of rom_table register
|
||||
* ROM-Table register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rom_table : R/W; bitpos: [31:0]; default: 0;
|
||||
* Software ROM-Table register, whose content can be modified only when
|
||||
* HP_SYSTEM_ROM_TABLE_LOCK is 0.
|
||||
*/
|
||||
uint32_t rom_table:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_rom_table_reg_t;
|
||||
|
||||
/** Type of core_debug_runstall_conf register
|
||||
* Core Debug RunStall configurion register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:1;
|
||||
/** core_runstalled : RO; bitpos: [1]; default: 0;
|
||||
* Software can read this field to get the runstall status of hp-core. 1: stalled, 0:
|
||||
* not stalled.
|
||||
*/
|
||||
uint32_t core_runstalled:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_core_debug_runstall_conf_reg_t;
|
||||
|
||||
/** Type of sprom_ctrl register
|
||||
* reserved
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t sprom_mem_aux_ctrl:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_sprom_ctrl_reg_t;
|
||||
|
||||
/** Type of spram_ctrl register
|
||||
* reserved
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t spram_mem_aux_ctrl:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_spram_ctrl_reg_t;
|
||||
|
||||
/** Type of sprf_ctrl register
|
||||
* reserved
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t sprf_mem_aux_ctrl:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_sprf_ctrl_reg_t;
|
||||
|
||||
/** Type of sdprf_ctrl register
|
||||
* reserved
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t sdprf_mem_aux_ctrl:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_sdprf_ctrl_reg_t;
|
||||
|
||||
/** Type of clock_gate register
|
||||
* HP-SYSTEM clock gating configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit as 1 to force on clock gating.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Timeout Register */
|
||||
/** Type of cpu_peri_timeout_conf register
|
||||
* CPU_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Configures the timeout threshold for bus access for accessing CPU peripheral
|
||||
* register in the number of clock cycles of the clock domain.
|
||||
*/
|
||||
uint32_t cpu_peri_timeout_thres:16;
|
||||
/** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
|
||||
* Write 1 to clear timeout interrupt.
|
||||
*/
|
||||
uint32_t cpu_peri_timeout_int_clear:1;
|
||||
/** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
|
||||
* Configures whether or not to enable timeout protection for accessing CPU peripheral
|
||||
* registers.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t cpu_peri_timeout_protect_en:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_cpu_peri_timeout_conf_reg_t;
|
||||
|
||||
/** Type of cpu_peri_timeout_addr register
|
||||
* CPU_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address information of abnormal access.
|
||||
*/
|
||||
uint32_t cpu_peri_timeout_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_cpu_peri_timeout_addr_reg_t;
|
||||
|
||||
/** Type of cpu_peri_timeout_uid register
|
||||
* CPU_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
|
||||
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
|
||||
* register will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
uint32_t cpu_peri_timeout_uid:7;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_cpu_peri_timeout_uid_reg_t;
|
||||
|
||||
/** Type of hp_peri_timeout_conf register
|
||||
* HP_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Configures the timeout threshold for bus access for accessing HP peripheral
|
||||
* register, corresponding to the number of clock cycles of the clock domain.
|
||||
*/
|
||||
uint32_t hp_peri_timeout_thres:16;
|
||||
/** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
|
||||
* Configures whether or not to clear timeout interrupt.\\
|
||||
* 0: No effect\\
|
||||
* 1: Clear timeout interrupt\\
|
||||
*/
|
||||
uint32_t hp_peri_timeout_int_clear:1;
|
||||
/** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
|
||||
* Configures whether or not to enable timeout protection for accessing HP peripheral
|
||||
* registers.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t hp_peri_timeout_protect_en:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_hp_peri_timeout_conf_reg_t;
|
||||
|
||||
/** Type of hp_peri_timeout_addr register
|
||||
* HP_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address information of abnormal access.
|
||||
*/
|
||||
uint32_t hp_peri_timeout_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_hp_peri_timeout_addr_reg_t;
|
||||
|
||||
/** Type of hp_peri_timeout_uid register
|
||||
* HP_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
|
||||
* Represents the master id[4:0] and master permission[6:5] when trigger timeout. This
|
||||
* register will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
uint32_t hp_peri_timeout_uid:7;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_hp_peri_timeout_uid_reg_t;
|
||||
|
||||
/** Type of modem_peri_timeout_conf register
|
||||
* MODEM_PERI_TIMEOUT configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535;
|
||||
* Set the timeout threshold for bus access, corresponding to the number of clock
|
||||
* cycles of the clock domain.
|
||||
*/
|
||||
uint32_t modem_peri_timeout_thres:16;
|
||||
/** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0;
|
||||
* Set this bit as 1 to clear timeout interrupt
|
||||
*/
|
||||
uint32_t modem_peri_timeout_int_clear:1;
|
||||
/** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1;
|
||||
* Set this bit as 1 to enable timeout protection for accessing modem registers
|
||||
*/
|
||||
uint32_t modem_peri_timeout_protect_en:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_modem_peri_timeout_conf_reg_t;
|
||||
|
||||
/** Type of modem_peri_timeout_addr register
|
||||
* MODEM_PERI_TIMEOUT_ADDR register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Record the address information of abnormal access
|
||||
*/
|
||||
uint32_t modem_peri_timeout_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_modem_peri_timeout_addr_reg_t;
|
||||
|
||||
/** Type of modem_peri_timeout_uid register
|
||||
* MODEM_PERI_TIMEOUT_UID register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0;
|
||||
* Record master id[4:0] & master permission[6:5] when trigger timeout. This register
|
||||
* will be cleared after the interrupt is cleared.
|
||||
*/
|
||||
uint32_t modem_peri_timeout_uid:7;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_modem_peri_timeout_uid_reg_t;
|
||||
|
||||
|
||||
/** Group: Redcy ECO Registers */
|
||||
/** Type of rnd_eco register
|
||||
* redcy eco register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_ena : W/R; bitpos: [0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_ena:1;
|
||||
/** redcy_result : RO; bitpos: [1]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_result:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_rnd_eco_reg_t;
|
||||
|
||||
/** Type of rnd_eco_low register
|
||||
* redcy eco low register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_low:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_rnd_eco_low_reg_t;
|
||||
|
||||
/** Type of rnd_eco_high register
|
||||
* redcy eco high register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_high:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_rnd_eco_high_reg_t;
|
||||
|
||||
|
||||
/** Group: Debug Register */
|
||||
/** Type of debug register
|
||||
* HP-SYSTEM debug register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fpga_debug : R/W; bitpos: [0]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t fpga_debug:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_debug_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* Date control and version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36769824;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} hp_system_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
|
||||
volatile hp_system_sram_usage_conf_reg_t sram_usage_conf;
|
||||
volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf;
|
||||
volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf;
|
||||
volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr;
|
||||
volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid;
|
||||
volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf;
|
||||
volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr;
|
||||
volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid;
|
||||
volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf;
|
||||
volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr;
|
||||
volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid;
|
||||
volatile hp_system_rom_table_lock_reg_t rom_table_lock;
|
||||
volatile hp_system_rom_table_reg_t rom_table;
|
||||
volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf;
|
||||
volatile hp_system_sprom_ctrl_reg_t sprom_ctrl;
|
||||
volatile hp_system_spram_ctrl_reg_t spram_ctrl;
|
||||
volatile hp_system_sprf_ctrl_reg_t sprf_ctrl;
|
||||
volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl;
|
||||
volatile hp_system_rnd_eco_reg_t rnd_eco;
|
||||
volatile hp_system_rnd_eco_low_reg_t rnd_eco_low;
|
||||
volatile hp_system_rnd_eco_high_reg_t rnd_eco_high;
|
||||
volatile hp_system_debug_reg_t debug;
|
||||
volatile hp_system_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_060[231];
|
||||
volatile hp_system_date_reg_t date;
|
||||
} hp_system_dev_t;
|
||||
|
||||
extern hp_system_dev_t HP_SYSTEM;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(hp_system_dev_t) == 0x400, "Invalid size of hp_system_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,814 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register
|
||||
* WIFI_MAC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0)
|
||||
/** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register
|
||||
* WIFI_MAC_NMI mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4)
|
||||
/** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S)
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register
|
||||
* WIFI_PWR_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8)
|
||||
/** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register
|
||||
* WIFI_BB_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc)
|
||||
/** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register
|
||||
* BT_MAC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
|
||||
/** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register
|
||||
* BT_BB_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
|
||||
/** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_BB_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
|
||||
* BT_BB_NMI mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
|
||||
/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S)
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register
|
||||
* LP_TIMER_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c)
|
||||
/** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_COEX_INTR_MAP_REG register
|
||||
* COEX_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
|
||||
/** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_COEX_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_COEX_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register
|
||||
* BLE_TIMER_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
|
||||
/** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register
|
||||
* BLE_SEC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
|
||||
/** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register
|
||||
* I2C_MST_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c)
|
||||
/** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register
|
||||
* ZB_MAC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
|
||||
/** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_PMU_INTR_MAP_REG register
|
||||
* PMU_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
|
||||
/** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_PMU_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_PMU_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register
|
||||
* EFUSE_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
|
||||
/** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_EFUSE_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register
|
||||
* LP_RTC_TIMER_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c)
|
||||
/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register
|
||||
* LP_WDT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
|
||||
/** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register
|
||||
* LP_PERI_TIMEOUT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
|
||||
/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register
|
||||
* LP_APM_M0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
|
||||
/** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c)
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
|
||||
* CPU_INTR_FROM_CPU_1 mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
|
||||
* CPU_INTR_FROM_CPU_2 mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
|
||||
* CPU_INTR_FROM_CPU_3 mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
|
||||
/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
|
||||
* ASSIST_DEBUG_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c)
|
||||
/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register
|
||||
* TRACE_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
|
||||
/** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TRACE_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register
|
||||
* CACHE_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
|
||||
/** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CACHE_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register
|
||||
* CPU_PERI_TIMEOUT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
|
||||
/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
|
||||
* GPIO_INTERRUPT_PRO mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
|
||||
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register
|
||||
* GPIO_INTERRUPT_EXT mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
|
||||
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S)
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
|
||||
* PAU_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
|
||||
/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_PAU_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_PAU_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
|
||||
* HP_PERI_TIMEOUT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
|
||||
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
|
||||
* MODEM_PERI_TIMEOUT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c)
|
||||
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
|
||||
* HP_APM_M0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
|
||||
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
|
||||
* HP_APM_M1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
|
||||
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
|
||||
* HP_APM_M2_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
|
||||
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
|
||||
* HP_APM_M3_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
|
||||
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register
|
||||
* MSPI_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
|
||||
/** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_MSPI_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register
|
||||
* I2S1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
|
||||
/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_UART0_INTR_MAP_REG register
|
||||
* UART0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
|
||||
/** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
|
||||
* UART1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
|
||||
/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_UART2_INTR_MAP_REG register
|
||||
* UART2_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
|
||||
/** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_M (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register
|
||||
* LEDC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4)
|
||||
/** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_LEDC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_USB_INTR_MAP_REG register
|
||||
* USB_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8)
|
||||
/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
|
||||
* I2C_EXT0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
|
||||
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
|
||||
* TG0_T0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0)
|
||||
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register
|
||||
* TG0_T1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4)
|
||||
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
|
||||
* TG0_WDT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8)
|
||||
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
|
||||
* TG1_T0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc)
|
||||
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register
|
||||
* TG1_T1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
|
||||
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
|
||||
* TG1_WDT_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
|
||||
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register
|
||||
* SYSTIMER_TARGET0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register
|
||||
* SYSTIMER_TARGET1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register
|
||||
* SYSTIMER_TARGET2_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
|
||||
/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register
|
||||
* APB_ADC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
|
||||
/** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
|
||||
* DMA_IN_CH0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
|
||||
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
|
||||
* DMA_IN_CH1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
|
||||
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
|
||||
* DMA_OUT_CH0_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
|
||||
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
|
||||
* DMA_OUT_CH1_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
|
||||
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
|
||||
* GPSPI2_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8)
|
||||
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
|
||||
* SHA_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec)
|
||||
/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_SHA_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_SHA_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
|
||||
* ECC_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0)
|
||||
/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ECC_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ECC_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
|
||||
* ECDSA_INTR mapping register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4)
|
||||
/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
|
||||
* Configures the interrupt source into one CPU interrupt.
|
||||
*/
|
||||
#define INTERRUPT_CORE0_ECDSA_INTR_MAP 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S)
|
||||
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU
|
||||
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_INT_STATUS_0_REG register
|
||||
* Status register for interrupt sources 0 ~ 31
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8)
|
||||
/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the status of the interrupt sources numbered from .Each bit corresponds
|
||||
* to one interrupt source
|
||||
* 0:The corresponding interrupt source triggered an interrupt
|
||||
* 1:No interrupt triggered
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INT_STATUS_0 0xFFFFFFFFU
|
||||
#define INTERRUPT_CORE0_INT_STATUS_0_M (INTERRUPT_CORE0_INT_STATUS_0_V << INTERRUPT_CORE0_INT_STATUS_0_S)
|
||||
#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
|
||||
#define INTERRUPT_CORE0_INT_STATUS_0_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_INT_STATUS_1_REG register
|
||||
* Status register for interrupt sources 32 ~ 63
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc)
|
||||
/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the status of the interrupt sources numbered from .Each bit corresponds
|
||||
* to one interrupt source
|
||||
* 0:The corresponding interrupt source triggered an interrupt
|
||||
* 1:No interrupt triggered
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INT_STATUS_1 0xFFFFFFFFU
|
||||
#define INTERRUPT_CORE0_INT_STATUS_1_M (INTERRUPT_CORE0_INT_STATUS_1_V << INTERRUPT_CORE0_INT_STATUS_1_S)
|
||||
#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
|
||||
#define INTERRUPT_CORE0_INT_STATUS_1_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_CLOCK_GATE_REG register
|
||||
* Interrupt clock gating configure register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
|
||||
/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Interrupt clock gating configure register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_REG_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE0_REG_CLK_EN_M (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
|
||||
#define INTERRUPT_CORE0_REG_CLK_EN_V 0x00000001U
|
||||
#define INTERRUPT_CORE0_REG_CLK_EN_S 0
|
||||
|
||||
/** INTERRUPT_CORE0_INTERRUPT_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
|
||||
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36774400;
|
||||
* Version control register
|
||||
*/
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_M (INTERRUPT_CORE0_INTERRUPT_DATE_V << INTERRUPT_CORE0_INTERRUPT_DATE_S)
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0x0FFFFFFFU
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
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|
|
@ -0,0 +1,88 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//Interrupt hardware source table
|
||||
//This table is decided by hardware, don't touch this.
|
||||
typedef enum {
|
||||
ETS_WIFI_MAC_INTR_SOURCE,
|
||||
ETS_WIFI_MAC_NMI_SOURCE,
|
||||
ETS_WIFI_PWR_INTR_SOURCE,
|
||||
ETS_WIFI_BB_INTR_SOURCE,
|
||||
ETS_BT_MAC_INTR_SOURCE,
|
||||
ETS_BT_BB_INTR_SOURCE,
|
||||
ETS_BT_BB_NMI_SOURCE,
|
||||
ETS_LP_TIMER_INTR_SOURCE,
|
||||
ETS_COEX_INTR_SOURCE,
|
||||
ETS_BLE_TIMER_INTR_SOURCE,
|
||||
ETS_BLE_SEC_INTR_SOURCE,
|
||||
ETS_I2C_MST_INTR_SOURCE,
|
||||
ETS_ZB_MAC_INTR_SOURCE,
|
||||
ETS_PMU_INTR_SOURCE,
|
||||
ETS_EFUSE_INTR_SOURCE,
|
||||
ETS_LP_RTC_TIMER_INTR_SOURCE,
|
||||
ETS_LP_WDT_INTR_SOURCE,
|
||||
ETS_LP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_LP_APM_M0_INTR_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
|
||||
ETS_ASSIST_DEBUG_INTR_SOURCE,
|
||||
ETS_TRACE_INTR_SOURCE,
|
||||
ETS_CACHE_INTR_SOURCE,
|
||||
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_PRO_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_EXT_SOURCE,
|
||||
ETS_PAU_INTR_SOURCE,
|
||||
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_HP_APM_M0_INTR_SOURCE,
|
||||
ETS_HP_APM_M1_INTR_SOURCE,
|
||||
ETS_HP_APM_M2_INTR_SOURCE,
|
||||
ETS_HP_APM_M3_INTR_SOURCE,
|
||||
ETS_MSPI_INTR_SOURCE,
|
||||
ETS_I2S1_INTR_SOURCE,
|
||||
ETS_UART0_INTR_SOURCE,
|
||||
ETS_UART1_INTR_SOURCE,
|
||||
ETS_UART2_INTR_SOURCE,
|
||||
ETS_LEDC_INTR_SOURCE,
|
||||
ETS_USB_INTR_SOURCE,
|
||||
ETS_I2C_EXT0_INTR_SOURCE,
|
||||
ETS_TG0_T0_INTR_SOURCE,
|
||||
ETS_TG0_T1_INTR_SOURCE,
|
||||
ETS_TG0_WDT_INTR_SOURCE,
|
||||
ETS_TG1_T0_INTR_SOURCE,
|
||||
ETS_TG1_T1_INTR_SOURCE,
|
||||
ETS_TG1_WDT_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
|
||||
ETS_APB_ADC_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH0_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH1_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH0_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH1_INTR_SOURCE,
|
||||
ETS_GPSPI2_INTR_SOURCE,
|
||||
ETS_SHA_INTR_SOURCE,
|
||||
ETS_ECC_INTR_SOURCE,
|
||||
ETS_ECDSA_INTR_SOURCE,
|
||||
ETS_MAX_INTR_SOURCE,
|
||||
} periph_interrput_t;
|
||||
|
||||
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_0_REG register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_0_REG (DR_REG_INTPRI_BASE + 0x90)
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
|
||||
* CPU_INTR_FROM_CPU_0 mapping register.
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_0 (BIT(0))
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_0_M (INTPRI_CPU_INTR_FROM_CPU_0_V << INTPRI_CPU_INTR_FROM_CPU_0_S)
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_0_V 0x00000001U
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_0_S 0
|
||||
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_1_REG register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_1_REG (DR_REG_INTPRI_BASE + 0x94)
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
|
||||
* CPU_INTR_FROM_CPU_1 mapping register.
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_1 (BIT(0))
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_1_M (INTPRI_CPU_INTR_FROM_CPU_1_V << INTPRI_CPU_INTR_FROM_CPU_1_S)
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_1_V 0x00000001U
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_1_S 0
|
||||
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_2_REG register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_2_REG (DR_REG_INTPRI_BASE + 0x98)
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
|
||||
* CPU_INTR_FROM_CPU_2 mapping register.
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_2 (BIT(0))
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_2_M (INTPRI_CPU_INTR_FROM_CPU_2_V << INTPRI_CPU_INTR_FROM_CPU_2_S)
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_2_V 0x00000001U
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_2_S 0
|
||||
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_3_REG register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_3_REG (DR_REG_INTPRI_BASE + 0x9c)
|
||||
/** INTPRI_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
|
||||
* CPU_INTR_FROM_CPU_3 mapping register.
|
||||
*/
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_3 (BIT(0))
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_3_M (INTPRI_CPU_INTR_FROM_CPU_3_V << INTPRI_CPU_INTR_FROM_CPU_3_S)
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_3_V 0x00000001U
|
||||
#define INTPRI_CPU_INTR_FROM_CPU_3_S 0
|
||||
|
||||
/** INTPRI_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define INTPRI_DATE_REG (DR_REG_INTPRI_BASE + 0xa0)
|
||||
/** INTPRI_DATE : R/W; bitpos: [27:0]; default: 36712784;
|
||||
* Version control register.
|
||||
*/
|
||||
#define INTPRI_DATE 0x0FFFFFFFU
|
||||
#define INTPRI_DATE_M (INTPRI_DATE_V << INTPRI_DATE_S)
|
||||
#define INTPRI_DATE_V 0x0FFFFFFFU
|
||||
#define INTPRI_DATE_S 0
|
||||
|
||||
/** INTPRI_CLOCK_GATE_REG register
|
||||
* register description
|
||||
*/
|
||||
#define INTPRI_CLOCK_GATE_REG (DR_REG_INTPRI_BASE + 0xa4)
|
||||
/** INTPRI_CLK_EN : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
#define INTPRI_CLK_EN (BIT(0))
|
||||
#define INTPRI_CLK_EN_M (INTPRI_CLK_EN_V << INTPRI_CLK_EN_S)
|
||||
#define INTPRI_CLK_EN_V 0x00000001U
|
||||
#define INTPRI_CLK_EN_S 0
|
||||
|
||||
/** INTPRI_RND_ECO_REG register
|
||||
* redcy eco register.
|
||||
*/
|
||||
#define INTPRI_RND_ECO_REG (DR_REG_INTPRI_BASE + 0xac)
|
||||
/** INTPRI_REDCY_ENA : W/R; bitpos: [0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define INTPRI_REDCY_ENA (BIT(0))
|
||||
#define INTPRI_REDCY_ENA_M (INTPRI_REDCY_ENA_V << INTPRI_REDCY_ENA_S)
|
||||
#define INTPRI_REDCY_ENA_V 0x00000001U
|
||||
#define INTPRI_REDCY_ENA_S 0
|
||||
/** INTPRI_REDCY_RESULT : RO; bitpos: [1]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define INTPRI_REDCY_RESULT (BIT(1))
|
||||
#define INTPRI_REDCY_RESULT_M (INTPRI_REDCY_RESULT_V << INTPRI_REDCY_RESULT_S)
|
||||
#define INTPRI_REDCY_RESULT_V 0x00000001U
|
||||
#define INTPRI_REDCY_RESULT_S 1
|
||||
|
||||
/** INTPRI_RND_ECO_LOW_REG register
|
||||
* redcy eco low register.
|
||||
*/
|
||||
#define INTPRI_RND_ECO_LOW_REG (DR_REG_INTPRI_BASE + 0xb0)
|
||||
/** INTPRI_REDCY_LOW : W/R; bitpos: [31:0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define INTPRI_REDCY_LOW 0xFFFFFFFFU
|
||||
#define INTPRI_REDCY_LOW_M (INTPRI_REDCY_LOW_V << INTPRI_REDCY_LOW_S)
|
||||
#define INTPRI_REDCY_LOW_V 0xFFFFFFFFU
|
||||
#define INTPRI_REDCY_LOW_S 0
|
||||
|
||||
/** INTPRI_RND_ECO_HIGH_REG register
|
||||
* redcy eco high register.
|
||||
*/
|
||||
#define INTPRI_RND_ECO_HIGH_REG (DR_REG_INTPRI_BASE + 0x3fc)
|
||||
/** INTPRI_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
#define INTPRI_REDCY_HIGH 0xFFFFFFFFU
|
||||
#define INTPRI_REDCY_HIGH_M (INTPRI_REDCY_HIGH_V << INTPRI_REDCY_HIGH_S)
|
||||
#define INTPRI_REDCY_HIGH_V 0xFFFFFFFFU
|
||||
#define INTPRI_REDCY_HIGH_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of cpu_intr_from_cpu_n register
|
||||
* CPU_INTR_FROM_CPU_0 mapping register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cpu_intr_from_cpu_n : R/W; bitpos: [0]; default: 0;
|
||||
* CPU_INTR_FROM_CPU_n mapping register.
|
||||
*/
|
||||
uint32_t cpu_intr_from_cpu_n:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_cpu_intr_from_cpu_n_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Registers */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36712784;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration Registers */
|
||||
/** Type of clock_gate register
|
||||
* register description
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* Need add description
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Redcy ECO Registers */
|
||||
/** Type of rnd_eco register
|
||||
* redcy eco register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_ena : W/R; bitpos: [0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_ena:1;
|
||||
/** redcy_result : RO; bitpos: [1]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_result:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_rnd_eco_reg_t;
|
||||
|
||||
/** Type of rnd_eco_low register
|
||||
* redcy eco low register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_low : W/R; bitpos: [31:0]; default: 0;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_low:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_rnd_eco_low_reg_t;
|
||||
|
||||
/** Type of rnd_eco_high register
|
||||
* redcy eco high register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** redcy_high : W/R; bitpos: [31:0]; default: 4294967295;
|
||||
* Only reserved for ECO.
|
||||
*/
|
||||
uint32_t redcy_high:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} intpri_rnd_eco_high_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved_000[36];
|
||||
volatile intpri_cpu_intr_from_cpu_n_reg_t cpu_intr_from_cpu_n[4];
|
||||
volatile intpri_date_reg_t date;
|
||||
volatile intpri_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_0a8;
|
||||
volatile intpri_rnd_eco_reg_t rnd_eco;
|
||||
volatile intpri_rnd_eco_low_reg_t rnd_eco_low;
|
||||
uint32_t reserved_0b4[210];
|
||||
volatile intpri_rnd_eco_high_reg_t rnd_eco_high;
|
||||
} intpri_dev_t;
|
||||
|
||||
extern intpri_dev_t INTPRI_REG;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(intpri_dev_t) == 0x400, "Invalid size of intpri_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,275 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_OE_M (BIT(0))
|
||||
#define SLP_OE_V 1
|
||||
#define SLP_OE_S 0
|
||||
/* Pin used for wakeup from sleep */
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_SEL_M (BIT(1))
|
||||
#define SLP_SEL_V 1
|
||||
#define SLP_SEL_S 1
|
||||
/* Pulldown enable in sleep mode */
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PD_M (BIT(2))
|
||||
#define SLP_PD_V 1
|
||||
#define SLP_PD_S 2
|
||||
/* Pullup enable in sleep mode */
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_PU_M (BIT(3))
|
||||
#define SLP_PU_V 1
|
||||
#define SLP_PU_S 3
|
||||
/* Input enable in sleep mode */
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_IE_M (BIT(4))
|
||||
#define SLP_IE_V 1
|
||||
#define SLP_IE_S 4
|
||||
/* Drive strength in sleep mode */
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
|
||||
#define SLP_DRV_V 0x3
|
||||
#define SLP_DRV_S 5
|
||||
/* Pulldown enable */
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PD_M (BIT(7))
|
||||
#define FUN_PD_V 1
|
||||
#define FUN_PD_S 7
|
||||
/* Pullup enable */
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_PU_M (BIT(8))
|
||||
#define FUN_PU_V 1
|
||||
#define FUN_PU_S 8
|
||||
/* Input enable */
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
|
||||
#define FUN_IE_V 1
|
||||
#define FUN_IE_S 9
|
||||
/* Drive strength */
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
|
||||
#define FUN_DRV_V 0x3
|
||||
#define FUN_DRV_S 10
|
||||
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
|
||||
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
|
||||
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
|
||||
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2
|
||||
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS
|
||||
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI
|
||||
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK
|
||||
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO
|
||||
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7
|
||||
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8
|
||||
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9
|
||||
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD
|
||||
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD
|
||||
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12
|
||||
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
|
||||
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1
|
||||
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0
|
||||
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ
|
||||
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP
|
||||
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI
|
||||
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
|
||||
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
|
||||
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
|
||||
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
|
||||
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
|
||||
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
|
||||
|
||||
#define PIN_FUNC_GPIO 1
|
||||
|
||||
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
|
||||
|
||||
#define U0RXD_GPIO_NUM 10
|
||||
#define U0TXD_GPIO_NUM 11
|
||||
|
||||
#define SPI_HD_GPIO_NUM 19
|
||||
#define SPI_WP_GPIO_NUM 17
|
||||
#define SPI_CS0_GPIO_NUM 15
|
||||
#define SPI_CLK_GPIO_NUM 20
|
||||
#define SPI_D_GPIO_NUM 21
|
||||
#define SPI_Q_GPIO_NUM 16
|
||||
|
||||
#define MAX_RTC_GPIO_NUM 7
|
||||
#define MAX_PAD_GPIO_NUM 30
|
||||
#define MAX_GPIO_NUM 34
|
||||
#define HIGH_IO_HOLD_BIT_SHIFT 32
|
||||
|
||||
|
||||
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
|
||||
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
|
||||
#define PAD_POWER_SEL BIT(15)
|
||||
#define PAD_POWER_SEL_V 0x1
|
||||
#define PAD_POWER_SEL_M BIT(15)
|
||||
#define PAD_POWER_SEL_S 15
|
||||
|
||||
#define PAD_POWER_SWITCH_DELAY 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_V 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
|
||||
#define PAD_POWER_SWITCH_DELAY_S 12
|
||||
|
||||
#define CLK_OUT3 IO_MUX_CLK_OUT3
|
||||
#define CLK_OUT3_V IO_MUX_CLK_OUT3_V
|
||||
#define CLK_OUT3_S IO_MUX_CLK_OUT3_S
|
||||
#define CLK_OUT3_M IO_MUX_CLK_OUT3_M
|
||||
#define CLK_OUT2 IO_MUX_CLK_OUT2
|
||||
#define CLK_OUT2_V IO_MUX_CLK_OUT2_V
|
||||
#define CLK_OUT2_S IO_MUX_CLK_OUT2_S
|
||||
#define CLK_OUT2_M IO_MUX_CLK_OUT2_M
|
||||
#define CLK_OUT1 IO_MUX_CLK_OUT1
|
||||
#define CLK_OUT1_V IO_MUX_CLK_OUT1_V
|
||||
#define CLK_OUT1_S IO_MUX_CLK_OUT1_S
|
||||
#define CLK_OUT1_M IO_MUX_CLK_OUT1_M
|
||||
// definitions above are inherited from previous version of code, should double check
|
||||
|
||||
// definitions below are generated from pin_txt.csv
|
||||
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0)
|
||||
#define FUNC_XTAL_32K_P_GPIO0 1
|
||||
#define FUNC_XTAL_32K_P_GPIO0_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4)
|
||||
#define FUNC_XTAL_32K_N_GPIO1 1
|
||||
#define FUNC_XTAL_32K_N_GPIO1_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8)
|
||||
#define FUNC_GPIO2_FSPIQ 2
|
||||
#define FUNC_GPIO2_GPIO2 1
|
||||
#define FUNC_GPIO2_GPIO2_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC)
|
||||
#define FUNC_MTMS_FSPIHD 2
|
||||
#define FUNC_MTMS_GPIO3 1
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10)
|
||||
#define FUNC_MTDI_FSPIWP 2
|
||||
#define FUNC_MTDI_GPIO4 1
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14)
|
||||
#define FUNC_MTCK_GPIO5 1
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18)
|
||||
#define FUNC_MTDO_FSPICLK 2
|
||||
#define FUNC_MTDO_GPIO6 1
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C)
|
||||
#define FUNC_GPIO7_FSPID 2
|
||||
#define FUNC_GPIO7_GPIO7 1
|
||||
#define FUNC_GPIO7_GPIO7_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20)
|
||||
#define FUNC_GPIO8_FSPICS0 2
|
||||
#define FUNC_GPIO8_GPIO8 1
|
||||
#define FUNC_GPIO8_GPIO8_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24)
|
||||
#define FUNC_GPIO9_GPIO9 1
|
||||
#define FUNC_GPIO9_GPIO9_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28)
|
||||
#define FUNC_U0RXD_GPIO10 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C)
|
||||
#define FUNC_U0TXD_GPIO11 1
|
||||
#define FUNC_U0TXD_U0TXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30)
|
||||
#define FUNC_GPIO12_GPIO12 1
|
||||
#define FUNC_GPIO12_GPIO12_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
|
||||
#define FUNC_GPIO13_GPIO13 1
|
||||
#define FUNC_GPIO13_GPIO13_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38)
|
||||
#define FUNC_SPICS1_GPIO14 1
|
||||
#define FUNC_SPICS1_SPICS1 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C)
|
||||
#define FUNC_SPICS0_GPIO15 1
|
||||
#define FUNC_SPICS0_SPICS0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40)
|
||||
#define FUNC_SPIQ_GPIO16 1
|
||||
#define FUNC_SPIQ_SPIQ 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44)
|
||||
#define FUNC_SPIWP_GPIO17 1
|
||||
#define FUNC_SPIWP_SPIWP 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48)
|
||||
#define FUNC_VDD_SPI_GPIO18 1
|
||||
#define FUNC_VDD_SPI_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C)
|
||||
#define FUNC_SPIHD_GPIO19 1
|
||||
#define FUNC_SPIHD_SPIHD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50)
|
||||
#define FUNC_SPICLK_GPIO20 1
|
||||
#define FUNC_SPICLK_SPICLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54)
|
||||
#define FUNC_SPID_GPIO21 1
|
||||
#define FUNC_SPID_SPID 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
|
||||
#define FUNC_GPIO22_GPIO22 1
|
||||
#define FUNC_GPIO22_GPIO22_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
|
||||
#define FUNC_GPIO23_GPIO23 1
|
||||
#define FUNC_GPIO23_GPIO23_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
|
||||
#define FUNC_GPIO24_GPIO24 1
|
||||
#define FUNC_GPIO24_GPIO24_0 0
|
||||
|
||||
/** IO_MUX_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define IO_MUX_DATE_REG (DR_REG_IO_MUX_BASE + 0x1fc)
|
||||
/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 36774288;
|
||||
* Version control register
|
||||
*/
|
||||
#define IO_MUX_REG_DATE 0x0FFFFFFFU
|
||||
#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
|
||||
#define IO_MUX_REG_DATE_V 0x0FFFFFFFU
|
||||
#define IO_MUX_REG_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Registers */
|
||||
/** Type of gpion register
|
||||
* IO MUX configuration register for GPIOn
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable the output of GPIOn in sleep mode.
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_mcu_oe:1;
|
||||
/** gpion_slp_sel : R/W; bitpos: [1]; default: 0;
|
||||
* Configures whether or not to enter sleep mode for GPIOn.\\
|
||||
* 0: Not enter\\
|
||||
* 1: Enter\\
|
||||
*/
|
||||
uint32_t gpion_slp_sel:1;
|
||||
/** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
|
||||
* Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_mcu_wpd:1;
|
||||
/** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
|
||||
* Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_mcu_wpu:1;
|
||||
/** gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
|
||||
* Configures whether or not to enable the input of GPIOn during sleep mode.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_mcu_ie:1;
|
||||
/** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
|
||||
* Configures the drive strength of GPIOn during sleep mode. \\
|
||||
* 0: ~5 mA\\
|
||||
* 1: ~10 mA\\
|
||||
* 2: ~20 mA\\
|
||||
* 3: ~40 mA\\
|
||||
*/
|
||||
uint32_t gpion_mcu_drv:2;
|
||||
/** gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
|
||||
* Configures whether or not to enable pull-down resistor of GPIOn.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_fun_wpd:1;
|
||||
/** gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
|
||||
* Configures whether or not enable pull-up resistor of GPIOn.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_fun_wpu:1;
|
||||
/** gpion_fun_ie : R/W; bitpos: [9]; default: 0;
|
||||
* Configures whether or not to enable input of GPIOn.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_fun_ie:1;
|
||||
/** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
|
||||
* Configures the drive strength of GPIOn. \\
|
||||
* 0: ~5 mA\\
|
||||
* 1: ~10 mA\\
|
||||
* 2: ~20 mA\\
|
||||
* 3: ~40 mA\\
|
||||
*/
|
||||
uint32_t gpion_fun_drv:2;
|
||||
/** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
|
||||
* Configures to select IO MUX function for this signal. \\
|
||||
* 0: Select Function 0\\
|
||||
* 1: Select Function 1\\
|
||||
* ......\\
|
||||
*/
|
||||
uint32_t gpion_mcu_sel:3;
|
||||
/** gpion_filter_en : R/W; bitpos: [15]; default: 0;
|
||||
* Configures whether or not to enable filter for pin input signals.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_filter_en:1;
|
||||
/** gpion_hys_en : R/W; bitpos: [16]; default: 0;
|
||||
* Configures whether or not to enable the hysteresis function of the pin when
|
||||
* IO_MUX_GPIOn_HYS_SEL is set to 1.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t gpion_hys_en:1;
|
||||
/** gpion_hys_sel : R/W; bitpos: [17]; default: 0;
|
||||
* Configures to choose the signal for enabling the hysteresis function for GPIOn. \\
|
||||
* 0: Choose the output enable signal of eFuse\\
|
||||
* 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN\\
|
||||
*/
|
||||
uint32_t gpion_hys_sel:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} io_mux_gpion_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** reg_date : R/W; bitpos: [27:0]; default: 36774288;
|
||||
* Version control register
|
||||
*/
|
||||
uint32_t reg_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} io_mux_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile io_mux_gpion_reg_t gpion[25];
|
||||
uint32_t reserved_064[102];
|
||||
volatile io_mux_date_reg_t date;
|
||||
} io_mux_dev_t;
|
||||
|
||||
extern io_mux_dev_t IO_MUX;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,345 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** MEM_MONITOR_LOG_SETTING_REG register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING_REG (DR_REG_MEM_MONITOR_BASE + 0x0)
|
||||
/** MEM_MONITOR_LOG_MODE : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[1]: Configures word monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[2]: Configures halfword monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[3]: Configures byte monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MODE 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_MODE_M (MEM_MONITOR_LOG_MODE_V << MEM_MONITOR_LOG_MODE_S)
|
||||
#define MEM_MONITOR_LOG_MODE_V 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_MODE_S 0
|
||||
/** MEM_MONITOR_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [4]; default: 1;
|
||||
* Configures the writing mode for recorded data.1: Loop mode\\
|
||||
* 0: Non-loop mode\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE (BIT(4))
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_M (MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V << MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S)
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MEM_LOOP_ENABLE_S 4
|
||||
/** MEM_MONITOR_LOG_CORE_ENA : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
|
||||
* enable HP CPU bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CORE_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_M (MEM_MONITOR_LOG_CORE_ENA_V << MEM_MONITOR_LOG_CORE_ENA_S)
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_CORE_ENA_S 8
|
||||
/** MEM_MONITOR_LOG_DMA_0_ENA : R/W; bitpos: [23:16]; default: 0;
|
||||
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_0 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_M (MEM_MONITOR_LOG_DMA_0_ENA_V << MEM_MONITOR_LOG_DMA_0_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_0_ENA_S 16
|
||||
/** MEM_MONITOR_LOG_DMA_1_ENA : R/W; bitpos: [31:24]; default: 0;
|
||||
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_1 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA_M (MEM_MONITOR_LOG_DMA_1_ENA_V << MEM_MONITOR_LOG_DMA_1_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_1_ENA_S 24
|
||||
|
||||
/** MEM_MONITOR_LOG_SETTING1_REG register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_SETTING1_REG (DR_REG_MEM_MONITOR_BASE + 0x4)
|
||||
/** MEM_MONITOR_LOG_DMA_2_ENA : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_2 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_M (MEM_MONITOR_LOG_DMA_2_ENA_V << MEM_MONITOR_LOG_DMA_2_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_2_ENA_S 0
|
||||
/** MEM_MONITOR_LOG_DMA_3_ENA : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_3 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA_M (MEM_MONITOR_LOG_DMA_3_ENA_V << MEM_MONITOR_LOG_DMA_3_ENA_S)
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_DMA_3_ENA_S 8
|
||||
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA_REG register
|
||||
* Configures monitored data in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_REG (DR_REG_MEM_MONITOR_BASE + 0x8)
|
||||
/** MEM_MONITOR_LOG_CHECK_DATA : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the data to be monitored during bus accessing.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_M (MEM_MONITOR_LOG_CHECK_DATA_V << MEM_MONITOR_LOG_CHECK_DATA_S)
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_CHECK_DATA_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_DATA_MASK_REG register
|
||||
* Configures masked data in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_REG (DR_REG_MEM_MONITOR_BASE + 0xc)
|
||||
/** MEM_MONITOR_LOG_DATA_MASK : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
|
||||
* Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[1]: Configures whether to mask the second least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[2]: Configures whether to mask the second most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[3]: Configures whether to mask the most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_DATA_MASK 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_M (MEM_MONITOR_LOG_DATA_MASK_V << MEM_MONITOR_LOG_DATA_MASK_S)
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_V 0x0000000FU
|
||||
#define MEM_MONITOR_LOG_DATA_MASK_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MIN_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MIN_REG (DR_REG_MEM_MONITOR_BASE + 0x10)
|
||||
/** MEM_MONITOR_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the lower bound address of the monitored address space.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MIN 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MIN_M (MEM_MONITOR_LOG_MIN_V << MEM_MONITOR_LOG_MIN_S)
|
||||
#define MEM_MONITOR_LOG_MIN_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MIN_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MAX_REG register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MAX_REG (DR_REG_MEM_MONITOR_BASE + 0x14)
|
||||
/** MEM_MONITOR_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of the monitored address space.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MAX 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MAX_M (MEM_MONITOR_LOG_MAX_V << MEM_MONITOR_LOG_MAX_S)
|
||||
#define MEM_MONITOR_LOG_MAX_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MAX_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_0_REG (DR_REG_MEM_MONITOR_BASE + 0x18)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the HP CPU bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_CORE_UPDATE_S 0
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE : WT; bitpos: [31]; default: 0;
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
|
||||
* 0: Not update\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE (BIT(31))
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_ALL_UPDATE_S 31
|
||||
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_UPDATE_1_REG (DR_REG_MEM_MONITOR_BASE + 0x1c)
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_0 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_0_UPDATE_S 0
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE : WT; bitpos: [15:8]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_1 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_1_UPDATE_S 8
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE : WT; bitpos: [23:16]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_2 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_2_UPDATE_S 16
|
||||
/** MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE : WT; bitpos: [31:24]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_3 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_M (MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V << MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_V 0x000000FFU
|
||||
#define MEM_MONITOR_LOG_MON_ADDR_DMA_3_UPDATE_S 24
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_START_REG register
|
||||
* Configures the starting address of the storage memory for recorded data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_START_REG (DR_REG_MEM_MONITOR_BASE + 0x20)
|
||||
/** MEM_MONITOR_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the starting address of the storage space for recorded data.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_START 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_START_M (MEM_MONITOR_LOG_MEM_START_V << MEM_MONITOR_LOG_MEM_START_S)
|
||||
#define MEM_MONITOR_LOG_MEM_START_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_START_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_END_REG register
|
||||
* Configures the end address of the storage memory for recorded data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_END_REG (DR_REG_MEM_MONITOR_BASE + 0x24)
|
||||
/** MEM_MONITOR_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the ending address of the storage space for recorded data.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_END 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_END_M (MEM_MONITOR_LOG_MEM_END_V << MEM_MONITOR_LOG_MEM_END_S)
|
||||
#define MEM_MONITOR_LOG_MEM_END_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_END_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG register
|
||||
* Represents the address for the next write
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG (DR_REG_MEM_MONITOR_BASE + 0x28)
|
||||
/** MEM_MONITOR_LOG_MEM_CURRENT_ADDR : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address of the next write.
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_M (MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V << MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S)
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_V 0xFFFFFFFFU
|
||||
#define MEM_MONITOR_LOG_MEM_CURRENT_ADDR_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG register
|
||||
* Updates the address for the next write with the starting address for the recorded
|
||||
* data
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_REG (DR_REG_MEM_MONITOR_BASE + 0x2c)
|
||||
/** MEM_MONITOR_LOG_MEM_ADDR_UPDATE : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
|
||||
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
|
||||
* 0: Not update (default) \\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE (BIT(0))
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_M (MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V << MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S)
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MEM_ADDR_UPDATE_S 0
|
||||
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG_REG register
|
||||
* Logging overflow status register
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_REG (DR_REG_MEM_MONITOR_BASE + 0x30)
|
||||
/** MEM_MONITOR_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether data overflows the storage space.0: Not Overflow\\
|
||||
* 1: Overflow\\
|
||||
*/
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG (BIT(0))
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_LOG_MEM_FULL_FLAG_S)
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_V 0x00000001U
|
||||
#define MEM_MONITOR_LOG_MEM_FULL_FLAG_S 0
|
||||
/** MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG : WT; bitpos: [1]; default: 0;
|
||||
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
|
||||
* clear\\
|
||||
* 1: Clear\\
|
||||
*/
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG (BIT(1))
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_M (MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V << MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S)
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
|
||||
#define MEM_MONITOR_CLR_LOG_MEM_FULL_FLAG_S 1
|
||||
|
||||
/** MEM_MONITOR_CLOCK_GATE_REG register
|
||||
* Register clock control
|
||||
*/
|
||||
#define MEM_MONITOR_CLOCK_GATE_REG (DR_REG_MEM_MONITOR_BASE + 0x34)
|
||||
/** MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the register clock gating.0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define MEM_MONITOR_CLK_EN (BIT(0))
|
||||
#define MEM_MONITOR_CLK_EN_M (MEM_MONITOR_CLK_EN_V << MEM_MONITOR_CLK_EN_S)
|
||||
#define MEM_MONITOR_CLK_EN_V 0x00000001U
|
||||
#define MEM_MONITOR_CLK_EN_S 0
|
||||
|
||||
/** MEM_MONITOR_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define MEM_MONITOR_DATE_REG (DR_REG_MEM_MONITOR_BASE + 0x3fc)
|
||||
/** MEM_MONITOR_DATE : R/W; bitpos: [27:0]; default: 36733248;
|
||||
* Version control register.
|
||||
*/
|
||||
#define MEM_MONITOR_DATE 0x0FFFFFFFU
|
||||
#define MEM_MONITOR_DATE_M (MEM_MONITOR_DATE_V << MEM_MONITOR_DATE_S)
|
||||
#define MEM_MONITOR_DATE_V 0x0FFFFFFFU
|
||||
#define MEM_MONITOR_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configuration registers */
|
||||
/** Type of log_setting register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mode : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures monitoring modes.bit[0]: Configures write monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[1]: Configures word monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[2]: Configures halfword monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* bit[3]: Configures byte monitoring. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t log_mode:4;
|
||||
/** log_mem_loop_enable : R/W; bitpos: [4]; default: 1;
|
||||
* Configures the writing mode for recorded data.1: Loop mode\\
|
||||
* 0: Non-loop mode\\
|
||||
*/
|
||||
uint32_t log_mem_loop_enable:1;
|
||||
uint32_t reserved_5:3;
|
||||
/** log_core_ena : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable CPU bus access logging.bit[0]: Configures whether to
|
||||
* enable HP CPU bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
uint32_t log_core_ena:8;
|
||||
/** log_dma_0_ena : R/W; bitpos: [23:16]; default: 0;
|
||||
* Configures whether to enable DMA_0 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_0 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
uint32_t log_dma_0_ena:8;
|
||||
/** log_dma_1_ena : R/W; bitpos: [31:24]; default: 0;
|
||||
* Configures whether to enable DMA_1 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_1 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
uint32_t log_dma_1_ena:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_setting_reg_t;
|
||||
|
||||
/** Type of log_setting1 register
|
||||
* Bus access logging configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_dma_2_ena : R/W; bitpos: [7:0]; default: 0;
|
||||
* Configures whether to enable DMA_2 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_2 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
uint32_t log_dma_2_ena:8;
|
||||
/** log_dma_3_ena : R/W; bitpos: [15:8]; default: 0;
|
||||
* Configures whether to enable DMA_3 bus access logging.bit[0]: Configures whether
|
||||
* to enable DMA_3 bus access logging. \\
|
||||
* 0: Disable \\
|
||||
* 1: Enable\\
|
||||
* Bit[7:1]: Reserved
|
||||
*/
|
||||
uint32_t log_dma_3_ena:8;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_setting1_reg_t;
|
||||
|
||||
/** Type of log_check_data register
|
||||
* Configures monitored data in Bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_check_data : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the data to be monitored during bus accessing.
|
||||
*/
|
||||
uint32_t log_check_data:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_check_data_reg_t;
|
||||
|
||||
/** Type of log_data_mask register
|
||||
* Configures masked data in Bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_data_mask : R/W; bitpos: [3:0]; default: 0;
|
||||
* Configures which byte(s) in MEM_MONITOR_LOG_CHECK_DATA_REG to mask.bit[0]:
|
||||
* Configures whether to mask the least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG.\\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[1]: Configures whether to mask the second least significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[2]: Configures whether to mask the second most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
* bit[3]: Configures whether to mask the most significant byte of
|
||||
* MEM_MONITOR_LOG_CHECK_DATA_REG. \\
|
||||
* 0: Not mask \\
|
||||
* 1: Mask\\
|
||||
*/
|
||||
uint32_t log_data_mask:4;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_data_mask_reg_t;
|
||||
|
||||
/** Type of log_min register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_min : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the lower bound address of the monitored address space.
|
||||
*/
|
||||
uint32_t log_min:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_min_reg_t;
|
||||
|
||||
/** Type of log_max register
|
||||
* Configures monitored address space in Bus access logging
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_max : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the upper bound address of the monitored address space.
|
||||
*/
|
||||
uint32_t log_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_max_reg_t;
|
||||
|
||||
/** Type of log_mon_addr_update_0 register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mon_addr_core_update : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the HP CPU bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
uint32_t log_mon_addr_core_update:8;
|
||||
uint32_t reserved_8:23;
|
||||
/** log_mon_addr_all_update : WT; bitpos: [31]; default: 0;
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of all masters.1: Update\\
|
||||
* 0: Not update\\
|
||||
*/
|
||||
uint32_t log_mon_addr_all_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mon_addr_update_0_reg_t;
|
||||
|
||||
/** Type of log_mon_addr_update_1 register
|
||||
* Configures the address space of from MEM_MONITOR_LOG_MIN_REG to
|
||||
* MEM_MONITOR_LOG_MAX_REG as the monitored address space of the certain master.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mon_addr_dma_0_update : WT; bitpos: [7:0]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_0 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_0_update:8;
|
||||
/** log_mon_addr_dma_1_update : WT; bitpos: [15:8]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_1 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_1_update:8;
|
||||
/** log_mon_addr_dma_2_update : WT; bitpos: [23:16]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_2 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_2_update:8;
|
||||
/** log_mon_addr_dma_3_update : WT; bitpos: [31:24]; default: 0;
|
||||
* Configures the monitored address space of the certain master. Bit[0]: Configures
|
||||
* the address space of from MEM_MONITOR_LOG_MIN_REG to MEM_MONITOR_LOG_MAX_REG as the
|
||||
* monitored address space of the DMA_3 bus.1: Update\\
|
||||
* 0: Not update\\
|
||||
* Bit[7:1]: Reserved\\
|
||||
*/
|
||||
uint32_t log_mon_addr_dma_3_update:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mon_addr_update_1_reg_t;
|
||||
|
||||
/** Type of log_mem_start register
|
||||
* Configures the starting address of the storage memory for recorded data
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_start : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the starting address of the storage space for recorded data.
|
||||
*/
|
||||
uint32_t log_mem_start:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mem_start_reg_t;
|
||||
|
||||
/** Type of log_mem_end register
|
||||
* Configures the end address of the storage memory for recorded data
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_end : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the ending address of the storage space for recorded data.
|
||||
*/
|
||||
uint32_t log_mem_end:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mem_end_reg_t;
|
||||
|
||||
/** Type of log_mem_current_addr register
|
||||
* Represents the address for the next write
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_current_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the address of the next write.
|
||||
*/
|
||||
uint32_t log_mem_current_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mem_current_addr_reg_t;
|
||||
|
||||
/** Type of log_mem_addr_update register
|
||||
* Updates the address for the next write with the starting address for the recorded
|
||||
* data
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_addr_update : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether to update the value in MEM_MONITOR_LOG_MEM_START_REG to
|
||||
* MEM_MONITOR_LOG_MEM_CURRENT_ADDR_REG.\raggedright1: Update \\
|
||||
* 0: Not update (default) \\
|
||||
*/
|
||||
uint32_t log_mem_addr_update:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mem_addr_update_reg_t;
|
||||
|
||||
/** Type of log_mem_full_flag register
|
||||
* Logging overflow status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** log_mem_full_flag : RO; bitpos: [0]; default: 0;
|
||||
* Represents whether data overflows the storage space.0: Not Overflow\\
|
||||
* 1: Overflow\\
|
||||
*/
|
||||
uint32_t log_mem_full_flag:1;
|
||||
/** clr_log_mem_full_flag : WT; bitpos: [1]; default: 0;
|
||||
* Configures whether to clear the MEM_MONITOR_LOG_MEM_FULL_FLAG flag bit.0: Not
|
||||
* clear\\
|
||||
* 1: Clear\\
|
||||
*/
|
||||
uint32_t clr_log_mem_full_flag:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_log_mem_full_flag_reg_t;
|
||||
|
||||
|
||||
/** Group: clk register */
|
||||
/** Type of clock_gate register
|
||||
* Register clock control
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* Configures whether to enable the register clock gating.0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: version register */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [27:0]; default: 36733248;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_monitor_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile mem_monitor_log_setting_reg_t log_setting;
|
||||
volatile mem_monitor_log_setting1_reg_t log_setting1;
|
||||
volatile mem_monitor_log_check_data_reg_t log_check_data;
|
||||
volatile mem_monitor_log_data_mask_reg_t log_data_mask;
|
||||
volatile mem_monitor_log_min_reg_t log_min;
|
||||
volatile mem_monitor_log_max_reg_t log_max;
|
||||
volatile mem_monitor_log_mon_addr_update_0_reg_t log_mon_addr_update_0;
|
||||
volatile mem_monitor_log_mon_addr_update_1_reg_t log_mon_addr_update_1;
|
||||
volatile mem_monitor_log_mem_start_reg_t log_mem_start;
|
||||
volatile mem_monitor_log_mem_end_reg_t log_mem_end;
|
||||
volatile mem_monitor_log_mem_current_addr_reg_t log_mem_current_addr;
|
||||
volatile mem_monitor_log_mem_addr_update_reg_t log_mem_addr_update;
|
||||
volatile mem_monitor_log_mem_full_flag_reg_t log_mem_full_flag;
|
||||
volatile mem_monitor_clock_gate_reg_t clock_gate;
|
||||
uint32_t reserved_038[241];
|
||||
volatile mem_monitor_date_reg_t date;
|
||||
} mem_monitor_dev_t;
|
||||
|
||||
extern mem_monitor_dev_t TCM_MEM_MONITOR;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(mem_monitor_dev_t) == 0x400, "Invalid size of mem_monitor_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define PMU_ICG_APB_ENA_CAN0 18
|
||||
#define PMU_ICG_APB_ENA_CAN1 19
|
||||
#define PMU_ICG_APB_ENA_GDMA 1
|
||||
#define PMU_ICG_APB_ENA_I2C 13
|
||||
#define PMU_ICG_APB_ENA_I2S 4
|
||||
#define PMU_ICG_APB_ENA_INTMTX 3
|
||||
#define PMU_ICG_APB_ENA_IOMUX 26
|
||||
#define PMU_ICG_APB_ENA_LEDC 14
|
||||
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
|
||||
#define PMU_ICG_APB_ENA_MSPI 5
|
||||
#define PMU_ICG_APB_ENA_PARL 23
|
||||
#define PMU_ICG_APB_ENA_PCNT 20
|
||||
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
|
||||
#define PMU_ICG_APB_ENA_PWM 21
|
||||
#define PMU_ICG_APB_ENA_REGDMA 24
|
||||
#define PMU_ICG_APB_ENA_RMT 15
|
||||
#define PMU_ICG_APB_ENA_SARADC 9
|
||||
#define PMU_ICG_APB_ENA_SEC 0
|
||||
#define PMU_ICG_APB_ENA_SOC_ETM 22
|
||||
#define PMU_ICG_APB_ENA_SPI2 2
|
||||
#define PMU_ICG_APB_ENA_SYSTIMER 16
|
||||
#define PMU_ICG_APB_ENA_TG0 11
|
||||
#define PMU_ICG_APB_ENA_TG1 12
|
||||
#define PMU_ICG_APB_ENA_UART0 6
|
||||
#define PMU_ICG_APB_ENA_UART1 7
|
||||
#define PMU_ICG_APB_ENA_UHCI 8
|
||||
#define PMU_ICG_APB_ENA_USB_DEVICE 17
|
||||
#define PMU_ICG_FUNC_ENA_CAN0 31
|
||||
#define PMU_ICG_FUNC_ENA_CAN1 30
|
||||
#define PMU_ICG_FUNC_ENA_I2C 29
|
||||
#define PMU_ICG_FUNC_ENA_I2S_RX 2
|
||||
#define PMU_ICG_FUNC_ENA_I2S_TX 7
|
||||
#define PMU_ICG_FUNC_ENA_IOMUX 28
|
||||
#define PMU_ICG_FUNC_ENA_LEDC 27
|
||||
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
|
||||
#define PMU_ICG_FUNC_ENA_MSPI 26
|
||||
#define PMU_ICG_FUNC_ENA_PARL_RX 25
|
||||
#define PMU_ICG_FUNC_ENA_PARL_TX 24
|
||||
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
|
||||
#define PMU_ICG_FUNC_ENA_PWM 22
|
||||
#define PMU_ICG_FUNC_ENA_RMT 21
|
||||
#define PMU_ICG_FUNC_ENA_SARADC 20
|
||||
#define PMU_ICG_FUNC_ENA_SEC 19
|
||||
#define PMU_ICG_FUNC_ENA_SPI2 1
|
||||
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
|
||||
#define PMU_ICG_FUNC_ENA_TG0 14
|
||||
#define PMU_ICG_FUNC_ENA_TG1 13
|
||||
#define PMU_ICG_FUNC_ENA_TSENS 12
|
||||
#define PMU_ICG_FUNC_ENA_UART0 3
|
||||
#define PMU_ICG_FUNC_ENA_UART1 4
|
||||
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
|
||||
#define PMU_ICG_FUNC_ENA_GDMA 0
|
||||
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
|
||||
#define PMU_ICG_FUNC_ENA_REGDMA 8
|
||||
#define PMU_ICG_FUNC_ENA_RETENTION 9
|
||||
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
|
||||
#define PMU_ICG_FUNC_ENA_UHCI 5
|
||||
#define PMU_ICG_FUNC_ENA_HPCORE 17
|
||||
#define PMU_ICG_FUNC_ENA_HPBUS 15
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define DR_REG_UART0_BASE 0x60000000
|
||||
#define DR_REG_UART1_BASE 0x60001000
|
||||
#define DR_REG_MSPI0_BASE 0x60002000
|
||||
#define DR_REG_MSPI1_BASE 0x60003000
|
||||
#define DR_REG_I2C_BASE 0x60004000
|
||||
#define DR_REG_UART2_BASE 0x60006000
|
||||
#define DR_REG_LEDC_BASE 0x60007000
|
||||
#define DR_REG_TIMG0_BASE 0x60008000
|
||||
#define DR_REG_TIMG1_BASE 0x60009000
|
||||
#define DR_REG_SYSTIMER_BASE 0x6000A000
|
||||
#define DR_REG_I2S_BASE 0x6000C000
|
||||
#define DR_REG_SARADC_BASE 0x6000E000
|
||||
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000
|
||||
#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000
|
||||
#define DR_REG_SOC_ETM_BASE 0x60013000
|
||||
#define DR_REG_PVT_MONITOR_BASE 0x60019000
|
||||
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
|
||||
#define DR_REG_AHB_GDMA_BASE 0x60080000
|
||||
#define DR_REG_GPSPI_BASE 0x60081000
|
||||
#define DR_REG_SHA_BASE 0x60089000
|
||||
#define DR_REG_ECC_BASE 0x6008B000
|
||||
#define DR_REG_ECDSA_BASE 0x6008E000
|
||||
#define DR_REG_IO_MUX_BASE 0x60090000
|
||||
#define DR_REG_GPIO_BASE 0x60091000
|
||||
#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000
|
||||
#define DR_REG_PAU_BASE 0x60093000
|
||||
#define DR_REG_HP_SYSTEM_REG_BASE 0x60095000
|
||||
#define DR_REG_PCR_REG_BASE 0x60096000
|
||||
#define DR_REG_TEE_REG_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_REG_BASE 0x60099000
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
#define DR_REG_MODEM0_BASE 0x600A0000
|
||||
#define DR_REG_MODEM1_BASE 0x600AC000
|
||||
#define DR_REG_MODEM_PWR0_BASE 0x600AD000
|
||||
#define DR_REG_MODEM_PWR1_BASE 0x600AF000
|
||||
#define DR_REG_PMU_BASE 0x600B0000
|
||||
#define DR_REG_LP_CLKRST_BASE 0x600B0400
|
||||
#define DR_REG_LP_TIMER_BASE 0x600B0C00
|
||||
#define DR_REG_LP_AON_BASE 0x600B1000
|
||||
#define DR_REG_LP_WDT_BASE 0x600B1C00
|
||||
#define DR_REG_LPPERI_BASE 0x600B2800
|
||||
#define DR_REG_LP_ANA_REG_BASE 0x600B2C00
|
||||
#define DR_REG_LP_TEE_BASE 0x600B3400
|
||||
#define DR_REG_LP_APM_BASE 0x600B3800
|
||||
#define DR_REG_LP_IO_MUX_BASE 0x600B4000
|
||||
#define DR_REG_LP_GPIO_BASE 0x600B4400
|
||||
#define DR_REG_EFUSE_AND_OTP_DEBUG0_BASE 0x600B4800
|
||||
#define DR_REG_EFUSE_AND_OTP_DEBUG1_BASE 0x600B4C00
|
||||
#define DR_REG_TRACE_BASE 0x600C0000
|
||||
#define DR_REG_BUS_MONITOR_BASE 0x600C2000
|
||||
#define DR_REG_INTPRI_REG_BASE 0x600C5000
|
||||
#define DR_REG_CACHE_CFG_BASE 0x600C8000
|
||||
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,253 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#define GPIO_EVT_CH0_RISE_EDGE 1
|
||||
#define GPIO_EVT_CH1_RISE_EDGE 2
|
||||
#define GPIO_EVT_CH2_RISE_EDGE 3
|
||||
#define GPIO_EVT_CH3_RISE_EDGE 4
|
||||
#define GPIO_EVT_CH4_RISE_EDGE 5
|
||||
#define GPIO_EVT_CH5_RISE_EDGE 6
|
||||
#define GPIO_EVT_CH6_RISE_EDGE 7
|
||||
#define GPIO_EVT_CH7_RISE_EDGE 8
|
||||
#define GPIO_EVT_CH0_FALL_EDGE 9
|
||||
#define GPIO_EVT_CH1_FALL_EDGE 10
|
||||
#define GPIO_EVT_CH2_FALL_EDGE 11
|
||||
#define GPIO_EVT_CH3_FALL_EDGE 12
|
||||
#define GPIO_EVT_CH4_FALL_EDGE 13
|
||||
#define GPIO_EVT_CH5_FALL_EDGE 14
|
||||
#define GPIO_EVT_CH6_FALL_EDGE 15
|
||||
#define GPIO_EVT_CH7_FALL_EDGE 16
|
||||
#define GPIO_EVT_CH0_ANY_EDGE 17
|
||||
#define GPIO_EVT_CH1_ANY_EDGE 18
|
||||
#define GPIO_EVT_CH2_ANY_EDGE 19
|
||||
#define GPIO_EVT_CH3_ANY_EDGE 20
|
||||
#define GPIO_EVT_CH4_ANY_EDGE 21
|
||||
#define GPIO_EVT_CH5_ANY_EDGE 22
|
||||
#define GPIO_EVT_CH6_ANY_EDGE 23
|
||||
#define GPIO_EVT_CH7_ANY_EDGE 24
|
||||
#define GPIO_EVT_ZERO_DET_POS0 25
|
||||
#define GPIO_EVT_ZERO_DET_NEG0 26
|
||||
#define GPIO_EVT_ZERO_DET_POS1 27
|
||||
#define GPIO_EVT_ZERO_DET_NEG1 28
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH0 29
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH1 30
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH2 31
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH3 32
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH4 33
|
||||
#define LEDC_EVT_DUTY_CHNG_END_CH5 34
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH0 35
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH1 36
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH2 37
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH3 38
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH4 39
|
||||
#define LEDC_EVT_OVF_CNT_PLS_CH5 40
|
||||
#define LEDC_EVT_TIME_OVF_TIMER0 41
|
||||
#define LEDC_EVT_TIME_OVF_TIMER1 42
|
||||
#define LEDC_EVT_TIME_OVF_TIMER2 43
|
||||
#define LEDC_EVT_TIME_OVF_TIMER3 44
|
||||
#define LEDC_EVT_TIMER0_CMP 45
|
||||
#define LEDC_EVT_TIMER1_CMP 46
|
||||
#define LEDC_EVT_TIMER2_CMP 47
|
||||
#define LEDC_EVT_TIMER3_CMP 48
|
||||
#define TG0_EVT_CNT_CMP_TIMER0 49
|
||||
#define TG0_EVT_CNT_CMP_TIMER1 50
|
||||
#define TG1_EVT_CNT_CMP_TIMER0 51
|
||||
#define TG1_EVT_CNT_CMP_TIMER1 52
|
||||
#define SYSTIMER_EVT_CNT_CMP0 53
|
||||
#define SYSTIMER_EVT_CNT_CMP1 54
|
||||
#define SYSTIMER_EVT_CNT_CMP2 55
|
||||
#define ADC_EVT_CONV_CMPLT0 56
|
||||
#define ADC_EVT_EQ_ABOVE_THRESH0 57
|
||||
#define ADC_EVT_EQ_ABOVE_THRESH1 58
|
||||
#define ADC_EVT_EQ_BELOW_THRESH0 59
|
||||
#define ADC_EVT_EQ_BELOW_THRESH1 60
|
||||
#define ADC_EVT_RESULT_DONE0 61
|
||||
#define ADC_EVT_STOPPED0 62
|
||||
#define ADC_EVT_STARTED0 63
|
||||
#define REGDMA_EVT_DONE0 64
|
||||
#define REGDMA_EVT_DONE1 65
|
||||
#define REGDMA_EVT_DONE2 66
|
||||
#define REGDMA_EVT_DONE3 67
|
||||
#define REGDMA_EVT_ERR0 68
|
||||
#define REGDMA_EVT_ERR1 69
|
||||
#define REGDMA_EVT_ERR2 70
|
||||
#define REGDMA_EVT_ERR3 71
|
||||
#define TMPSNSR_EVT_OVER_LIMIT 72
|
||||
#define I2S0_EVT_RX_DONE 73
|
||||
#define I2S0_EVT_TX_DONE 74
|
||||
#define I2S0_EVT_X_WORDS_RECEIVED 75
|
||||
#define I2S0_EVT_X_WORDS_SENT 76
|
||||
#define I2S1_EVT_RX_DONE 77
|
||||
#define I2S1_EVT_TX_DONE 78
|
||||
#define I2S1_EVT_X_WORDS_RECEIVED 79
|
||||
#define I2S1_EVT_X_WORDS_SENT 80
|
||||
#define ULP_EVT_ERR_INTR 81
|
||||
#define ULP_EVT_HALT 82
|
||||
#define ULP_EVT_START_INTR 83
|
||||
#define RTC_EVT_TICK 84
|
||||
#define RTC_EVT_OVF 85
|
||||
#define RTC_EVT_CMP 86
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH0 87
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH1 88
|
||||
#define GDMA_AHB_EVT_IN_DONE_CH2 89
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH0 90
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH1 91
|
||||
#define GDMA_AHB_EVT_IN_SUC_EOF_CH2 92
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 93
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 94
|
||||
#define GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2 95
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH0 96
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH1 97
|
||||
#define GDMA_AHB_EVT_IN_FIFO_FULL_CH2 98
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH0 99
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH1 100
|
||||
#define GDMA_AHB_EVT_OUT_DONE_CH2 101
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH0 102
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH1 103
|
||||
#define GDMA_AHB_EVT_OUT_EOF_CH2 104
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 105
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 106
|
||||
#define GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2 107
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 108
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 109
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2 110
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 111
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 112
|
||||
#define GDMA_AHB_EVT_OUT_FIFO_FULL_CH2 113
|
||||
#define PMU_EVT_SLEEP_WEEKUP 114
|
||||
#define GPIO_TASK_CH0_SET 1
|
||||
#define GPIO_TASK_CH1_SET 2
|
||||
#define GPIO_TASK_CH2_SET 3
|
||||
#define GPIO_TASK_CH3_SET 4
|
||||
#define GPIO_TASK_CH4_SET 5
|
||||
#define GPIO_TASK_CH5_SET 6
|
||||
#define GPIO_TASK_CH6_SET 7
|
||||
#define GPIO_TASK_CH7_SET 8
|
||||
#define GPIO_TASK_CH0_CLEAR 9
|
||||
#define GPIO_TASK_CH1_CLEAR 10
|
||||
#define GPIO_TASK_CH2_CLEAR 11
|
||||
#define GPIO_TASK_CH3_CLEAR 12
|
||||
#define GPIO_TASK_CH4_CLEAR 13
|
||||
#define GPIO_TASK_CH5_CLEAR 14
|
||||
#define GPIO_TASK_CH6_CLEAR 15
|
||||
#define GPIO_TASK_CH7_CLEAR 16
|
||||
#define GPIO_TASK_CH0_TOGGLE 17
|
||||
#define GPIO_TASK_CH1_TOGGLE 18
|
||||
#define GPIO_TASK_CH2_TOGGLE 19
|
||||
#define GPIO_TASK_CH3_TOGGLE 20
|
||||
#define GPIO_TASK_CH4_TOGGLE 21
|
||||
#define GPIO_TASK_CH5_TOGGLE 22
|
||||
#define GPIO_TASK_CH6_TOGGLE 23
|
||||
#define GPIO_TASK_CH7_TOGGLE 24
|
||||
#define LEDC_TASK_TIMER0_RES_UPDATE 25
|
||||
#define LEDC_TASK_TIMER1_RES_UPDATE 26
|
||||
#define LEDC_TASK_TIMER2_RES_UPDATE 27
|
||||
#define LEDC_TASK_TIMER3_RES_UPDATE 28
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
|
||||
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
|
||||
#define LEDC_TASK_TIMER0_CAP 35
|
||||
#define LEDC_TASK_TIMER1_CAP 36
|
||||
#define LEDC_TASK_TIMER2_CAP 37
|
||||
#define LEDC_TASK_TIMER3_CAP 38
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH0 39
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH1 40
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH2 41
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH3 42
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH4 43
|
||||
#define LEDC_TASK_SIG_OUT_DIS_CH5 44
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH0 45
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH1 46
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH2 47
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH3 48
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH4 49
|
||||
#define LEDC_TASK_OVF_CNT_RST_CH5 50
|
||||
#define LEDC_TASK_TIMER0_RST 51
|
||||
#define LEDC_TASK_TIMER1_RST 52
|
||||
#define LEDC_TASK_TIMER2_RST 53
|
||||
#define LEDC_TASK_TIMER3_RST 54
|
||||
#define LEDC_TASK_TIMER0_RESUME 55
|
||||
#define LEDC_TASK_TIMER1_RESUME 56
|
||||
#define LEDC_TASK_TIMER2_RESUME 57
|
||||
#define LEDC_TASK_TIMER3_RESUME 58
|
||||
#define LEDC_TASK_TIMER0_PAUSE 59
|
||||
#define LEDC_TASK_TIMER1_PAUSE 60
|
||||
#define LEDC_TASK_TIMER2_PAUSE 61
|
||||
#define LEDC_TASK_TIMER3_PAUSE 62
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH0 63
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH1 64
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH2 65
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH3 66
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH4 67
|
||||
#define LEDC_TASK_GAMMA_RESTART_CH5 68
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH0 69
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH1 70
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH2 71
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH3 72
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH4 73
|
||||
#define LEDC_TASK_GAMMA_PAUSE_CH5 74
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH0 75
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH1 76
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH2 77
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH3 78
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH4 79
|
||||
#define LEDC_TASK_GAMMA_RESUME_CH5 80
|
||||
#define TG0_TASK_CNT_START_TIMER0 81
|
||||
#define TG0_TASK_ALARM_START_TIMER0 82
|
||||
#define TG0_TASK_CNT_STOP_TIMER0 83
|
||||
#define TG0_TASK_CNT_RELOAD_TIMER0 84
|
||||
#define TG0_TASK_CNT_CAP_TIMER0 85
|
||||
#define TG0_TASK_CNT_START_TIMER1 86
|
||||
#define TG0_TASK_ALARM_START_TIMER1 87
|
||||
#define TG0_TASK_CNT_STOP_TIMER1 88
|
||||
#define TG0_TASK_CNT_RELOAD_TIMER1 89
|
||||
#define TG0_TASK_CNT_CAP_TIMER1 90
|
||||
#define TG1_TASK_CNT_START_TIMER0 91
|
||||
#define TG1_TASK_ALARM_START_TIMER0 92
|
||||
#define TG1_TASK_CNT_STOP_TIMER0 93
|
||||
#define TG1_TASK_CNT_RELOAD_TIMER0 94
|
||||
#define TG1_TASK_CNT_CAP_TIMER0 95
|
||||
#define TG1_TASK_CNT_START_TIMER1 96
|
||||
#define TG1_TASK_ALARM_START_TIMER1 97
|
||||
#define TG1_TASK_CNT_STOP_TIMER1 98
|
||||
#define TG1_TASK_CNT_RELOAD_TIMER1 99
|
||||
#define TG1_TASK_CNT_CAP_TIMER1 100
|
||||
#define ADC_TASK_SAMPLE0 101
|
||||
#define ADC_TASK_SAMPLE1 102
|
||||
#define ADC_TASK_START0 103
|
||||
#define ADC_TASK_STOP0 104
|
||||
#define REGDMA_TASK_START0 105
|
||||
#define REGDMA_TASK_START1 106
|
||||
#define REGDMA_TASK_START2 107
|
||||
#define REGDMA_TASK_START3 108
|
||||
#define TMPSNSR_TASK_START_SAMPLE 109
|
||||
#define TMPSNSR_TASK_STOP_SAMPLE 110
|
||||
#define I2S0_TASK_START_RX 111
|
||||
#define I2S0_TASK_START_TX 112
|
||||
#define I2S0_TASK_STOP_RX 113
|
||||
#define I2S0_TASK_STOP_TX 114
|
||||
#define I2S1_TASK_START_RX 115
|
||||
#define I2S1_TASK_START_TX 116
|
||||
#define I2S1_TASK_STOP_RX 117
|
||||
#define I2S1_TASK_STOP_TX 118
|
||||
#define ULP_TASK_WAKEUP_CPU 119
|
||||
#define ULP_TASK_INT_CPU 120
|
||||
#define RTC_TASK_START 121
|
||||
#define RTC_TASK_STOP 122
|
||||
#define RTC_TASK_CLR 123
|
||||
#define RTC_TASK_TRIGGERFLW 124
|
||||
#define GDMA_AHB_TASK_IN_START_CH0 125
|
||||
#define GDMA_AHB_TASK_IN_START_CH1 126
|
||||
#define GDMA_AHB_TASK_IN_START_CH2 127
|
||||
#define GDMA_AHB_TASK_OUT_START_CH0 128
|
||||
#define GDMA_AHB_TASK_OUT_START_CH1 129
|
||||
#define GDMA_AHB_TASK_OUT_START_CH2 130
|
||||
#define PMU_TASK_SLEEP_REQ 131
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,680 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTIMER_CONF_REG register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
|
||||
/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
|
||||
* Configures whether or not to enable generation of ETM events.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define SYSTIMER_ETM_EN (BIT(1))
|
||||
#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
|
||||
#define SYSTIMER_ETM_EN_V 0x00000001U
|
||||
#define SYSTIMER_ETM_EN_S 1
|
||||
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
|
||||
* Configures whether or not to enable COMP2.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
|
||||
* Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
|
||||
* Configures whether or not UNIT1 is stalled when CORE1 is stalled. \\
|
||||
* 0: UNIT1 is not stalled. \\
|
||||
* 1: UNIT1 is stalled.\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
|
||||
* Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
|
||||
* Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable UNIT1. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
|
||||
* Configures whether or not to enable UNIT0. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
|
||||
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Configures register clock gating. \\
|
||||
* 0: Only enable needed clock for register read or write operations. \\
|
||||
* 1: Register clock is always enabled for read and write operations. \\
|
||||
*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
|
||||
#define SYSTIMER_CLK_EN_V 0x00000001U
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_OP_REG register
|
||||
* Read UNIT0 value to registers
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* Represents UNIT0 value is synchronized and valid.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value
|
||||
* to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\
|
||||
* 0: No effect\\
|
||||
* 1: Update timer UNIT0 \\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT1_OP_REG register
|
||||
* Read UNIT1 value to registers
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* Represents UNIT1 value is synchronized and valid.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value
|
||||
* to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. \\
|
||||
* 0: No effect \\
|
||||
* 1: Update timer UNIT1\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_HI_REG register
|
||||
* High 20 bits to be loaded to UNIT0
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_LO_REG register
|
||||
* Low 32 bits to be loaded to UNIT0
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_HI_REG register
|
||||
* High 20 bits to be loaded to UNIT1
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT1, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_LO_REG register
|
||||
* Low 32 bits to be loaded to UNIT1
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT1, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_HI_REG register
|
||||
* Alarm value to be loaded to COMP0, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
|
||||
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_LO_REG register
|
||||
* Alarm value to be loaded to COMP0, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_HI_REG register
|
||||
* Alarm value to be loaded to COMP1, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP1, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_LO_REG register
|
||||
* Alarm value to be loaded to COMP1, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP1, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_HI_REG register
|
||||
* Alarm value to be loaded to COMP2, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
|
||||
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP2, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_LO_REG register
|
||||
* Alarm value to be loaded to COMP2, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP2, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_CONF_REG register
|
||||
* Configure COMP0 alarm mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP0 alarm period.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET0_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Selects the two alarm modes for COMP0. \\
|
||||
* 0: Target mode\\
|
||||
* 1: Period mode\\
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP0.\\
|
||||
* 0: Use the count value from UNIT$0\\
|
||||
* 1: Use the count value from UNIT$1\\
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET1_CONF_REG register
|
||||
* Configure COMP1 alarm mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP1 alarm period.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET1_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP1. See details in
|
||||
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET2_CONF_REG register
|
||||
* Configure COMP2 alarm mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
|
||||
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP2 alarm period.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
|
||||
#define SYSTIMER_TARGET2_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Configures Configures the two alarm modes for COMP2. See details in
|
||||
* SYSTIMER_TARGET0_PERIOD_MODE.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP2. See details in
|
||||
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_HI_REG register
|
||||
* UNIT0 value, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents UNIT0 read value, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_LO_REG register
|
||||
* UNIT0 value, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents UNIT0 read value, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_HI_REG register
|
||||
* UNIT1 value, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents UNIT1 read value, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_LO_REG register
|
||||
* UNIT1 value, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents UNIT1 read value, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_COMP0_LOAD_REG register
|
||||
* COMP0 synchronization register
|
||||
*/
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP0.\\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP0 synchronization\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP1_LOAD_REG register
|
||||
* COMP1 synchronization register
|
||||
*/
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP1. \\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP1 synchronization\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP2_LOAD_REG register
|
||||
* COMP2 synchronization register
|
||||
*/
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP2.\\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP2 synchronization\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_REG register
|
||||
* UNIT0 synchronization register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to reload the value of UNIT0, i.e., reloads the values of
|
||||
* SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. \\
|
||||
* 0: No effect \\
|
||||
* 1: Reload the value of UNIT0\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_REG register
|
||||
* UNIT1 synchronization register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to reload the value of UNIT1, i.e., reload the values of
|
||||
* SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. \\
|
||||
* 0: No effect \\
|
||||
* 1: Reload the value of UNIT1\\
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_INT_ENA_REG register
|
||||
* Interrupt enable register of system timer
|
||||
*/
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ENA_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
|
||||
/** SYSTIMER_INT_RAW_REG register
|
||||
* Interrupt raw register of system timer
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_RAW_S 0
|
||||
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* Interrupt clear register of system timer
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
|
||||
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_CLR_S 0
|
||||
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
|
||||
/** SYSTIMER_INT_ST_REG register
|
||||
* Interrupt status register of system timer
|
||||
*/
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET0_INT_ST_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_LO_REG register
|
||||
* Actual target value of COMP0, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
|
||||
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
|
||||
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET0_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_HI_REG register
|
||||
* Actual target value of COMP0, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
|
||||
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
|
||||
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET0_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_LO_REG register
|
||||
* Actual target value of COMP1, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
|
||||
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP1, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
|
||||
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET1_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_HI_REG register
|
||||
* Actual target value of COMP1, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
|
||||
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP1, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
|
||||
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET1_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_LO_REG register
|
||||
* Actual target value of COMP2, low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
|
||||
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP2, low 32 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
|
||||
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_TARGET2_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_HI_REG register
|
||||
* Actual target value of COMP2, high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
|
||||
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP2, high 20 bits.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
|
||||
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
|
||||
#define SYSTIMER_TARGET2_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 36774432;
|
||||
* Version control register.
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFFU
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,729 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: SYSTEM TIMER CLK CONTROL REGISTER */
|
||||
/** Type of conf register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
uint32_t systimer_clk_fo:1;
|
||||
/** etm_en : R/W; bitpos: [1]; default: 0;
|
||||
* Configures whether or not to enable generation of ETM events.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t etm_en:1;
|
||||
uint32_t reserved_2:20;
|
||||
/** target2_work_en : R/W; bitpos: [22]; default: 0;
|
||||
* Configures whether or not to enable COMP2.\\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t target2_work_en:1;
|
||||
/** target1_work_en : R/W; bitpos: [23]; default: 0;
|
||||
* Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN.
|
||||
*/
|
||||
uint32_t target1_work_en:1;
|
||||
/** target0_work_en : R/W; bitpos: [24]; default: 0;
|
||||
* Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN.
|
||||
*/
|
||||
uint32_t target0_work_en:1;
|
||||
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
|
||||
* Configures whether or not UNIT1 is stalled when CORE1 is stalled. \\
|
||||
* 0: UNIT1 is not stalled. \\
|
||||
* 1: UNIT1 is stalled.\\
|
||||
*/
|
||||
uint32_t timer_unit1_core1_stall_en:1;
|
||||
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
|
||||
* Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
uint32_t timer_unit1_core0_stall_en:1;
|
||||
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
|
||||
* Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
uint32_t timer_unit0_core1_stall_en:1;
|
||||
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
|
||||
* Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in
|
||||
* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
|
||||
*/
|
||||
uint32_t timer_unit0_core0_stall_en:1;
|
||||
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
|
||||
* Configures whether or not to enable UNIT1. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t timer_unit1_work_en:1;
|
||||
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
|
||||
* Configures whether or not to enable UNIT0. \\
|
||||
* 0: Disable\\
|
||||
* 1: Enable\\
|
||||
*/
|
||||
uint32_t timer_unit0_work_en:1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Configures register clock gating. \\
|
||||
* 0: Only enable needed clock for register read or write operations. \\
|
||||
* 1: Register clock is always enabled for read and write operations. \\
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER UNIT0 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of unit0_op register
|
||||
* Read UNIT0 value to registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:29;
|
||||
/** timer_unit0_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* Represents UNIT0 value is synchronized and valid.
|
||||
*/
|
||||
uint32_t timer_unit0_value_valid:1;
|
||||
/** timer_unit0_update : WT; bitpos: [30]; default: 0;
|
||||
* Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value
|
||||
* to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\
|
||||
* 0: No effect\\
|
||||
* 1: Update timer UNIT0 \\
|
||||
*/
|
||||
uint32_t timer_unit0_update:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_op_reg_t;
|
||||
|
||||
/** Type of unit0_load_hi register
|
||||
* High 20 bits to be loaded to UNIT0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_load_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_hi_reg_t;
|
||||
|
||||
/** Type of unit0_load_lo register
|
||||
* Low 32 bits to be loaded to UNIT0
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT0, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_lo_reg_t;
|
||||
|
||||
/** Type of unit0_value_hi register
|
||||
* UNIT0 value, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents UNIT0 read value, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_value_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_value_hi_reg_t;
|
||||
|
||||
/** Type of unit0_value_lo register
|
||||
* UNIT0 value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents UNIT0 read value, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit0_value_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_value_lo_reg_t;
|
||||
|
||||
/** Type of unit0_load register
|
||||
* UNIT0 synchronization register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit0_load : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to reload the value of UNIT0, i.e., reloads the values of
|
||||
* SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. \\
|
||||
* 0: No effect \\
|
||||
* 1: Reload the value of UNIT0\\
|
||||
*/
|
||||
uint32_t timer_unit0_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit0_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER UNIT1 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of unit1_op register
|
||||
* Read UNIT1 value to registers
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:29;
|
||||
/** timer_unit1_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* Represents UNIT1 value is synchronized and valid.
|
||||
*/
|
||||
uint32_t timer_unit1_value_valid:1;
|
||||
/** timer_unit1_update : WT; bitpos: [30]; default: 0;
|
||||
* Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value
|
||||
* to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. \\
|
||||
* 0: No effect \\
|
||||
* 1: Update timer UNIT1\\
|
||||
*/
|
||||
uint32_t timer_unit1_update:1;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_op_reg_t;
|
||||
|
||||
/** Type of unit1_load_hi register
|
||||
* High 20 bits to be loaded to UNIT1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT1, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit1_load_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_hi_reg_t;
|
||||
|
||||
/** Type of unit1_load_lo register
|
||||
* Low 32 bits to be loaded to UNIT1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the value to be loaded to UNIT1, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit1_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_lo_reg_t;
|
||||
|
||||
/** Type of unit1_value_hi register
|
||||
* UNIT1 value, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents UNIT1 read value, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_unit1_value_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_value_hi_reg_t;
|
||||
|
||||
/** Type of unit1_value_lo register
|
||||
* UNIT1 value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents UNIT1 read value, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_unit1_value_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_value_lo_reg_t;
|
||||
|
||||
/** Type of unit1_load register
|
||||
* UNIT1 synchronization register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit1_load : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to reload the value of UNIT1, i.e., reload the values of
|
||||
* SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. \\
|
||||
* 0: No effect \\
|
||||
* 1: Reload the value of UNIT1\\
|
||||
*/
|
||||
uint32_t timer_unit1_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit1_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP0 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target0_hi register
|
||||
* Alarm value to be loaded to COMP0, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target0_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_target0_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_hi_reg_t;
|
||||
|
||||
/** Type of target0_lo register
|
||||
* Alarm value to be loaded to COMP0, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target0_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP0, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_target0_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_lo_reg_t;
|
||||
|
||||
/** Type of target0_conf register
|
||||
* Configure COMP0 alarm mode
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP0 alarm period.
|
||||
*/
|
||||
uint32_t target0_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target0_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Selects the two alarm modes for COMP0. \\
|
||||
* 0: Target mode\\
|
||||
* 1: Period mode\\
|
||||
*/
|
||||
uint32_t target0_period_mode:1;
|
||||
/** target0_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP0.\\
|
||||
* 0: Use the count value from UNIT$0\\
|
||||
* 1: Use the count value from UNIT$1\\
|
||||
*/
|
||||
uint32_t target0_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target0_conf_reg_t;
|
||||
|
||||
/** Type of comp0_load register
|
||||
* COMP0 synchronization register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp0_load : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP0.\\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP0 synchronization\\
|
||||
*/
|
||||
uint32_t timer_comp0_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp0_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP1 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target1_hi register
|
||||
* Alarm value to be loaded to COMP1, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target1_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP1, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_target1_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_hi_reg_t;
|
||||
|
||||
/** Type of target1_lo register
|
||||
* Alarm value to be loaded to COMP1, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target1_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP1, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_target1_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_lo_reg_t;
|
||||
|
||||
/** Type of target1_conf register
|
||||
* Configure COMP1 alarm mode
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP1 alarm period.
|
||||
*/
|
||||
uint32_t target1_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target1_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE.
|
||||
*/
|
||||
uint32_t target1_period_mode:1;
|
||||
/** target1_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP1. See details in
|
||||
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
|
||||
*/
|
||||
uint32_t target1_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target1_conf_reg_t;
|
||||
|
||||
/** Type of comp1_load register
|
||||
* COMP1 synchronization register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp1_load : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP1. \\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP1 synchronization\\
|
||||
*/
|
||||
uint32_t timer_comp1_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp1_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP2 CONTROL AND CONFIGURATION REGISTER */
|
||||
/** Type of target2_hi register
|
||||
* Alarm value to be loaded to COMP2, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target2_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP2, high 20 bits.
|
||||
*/
|
||||
uint32_t timer_target2_hi:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_hi_reg_t;
|
||||
|
||||
/** Type of target2_lo register
|
||||
* Alarm value to be loaded to COMP2, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_target2_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the alarm value to be loaded to COMP2, low 32 bits.
|
||||
*/
|
||||
uint32_t timer_target2_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_lo_reg_t;
|
||||
|
||||
/** Type of target2_conf register
|
||||
* Configure COMP2 alarm mode
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* Configures COMP2 alarm period.
|
||||
*/
|
||||
uint32_t target2_period:26;
|
||||
uint32_t reserved_26:4;
|
||||
/** target2_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Configures Configures the two alarm modes for COMP2. See details in
|
||||
* SYSTIMER_TARGET0_PERIOD_MODE.
|
||||
*/
|
||||
uint32_t target2_period_mode:1;
|
||||
/** target2_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* Chooses the counter value for comparison with COMP2. See details in
|
||||
* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
|
||||
*/
|
||||
uint32_t target2_timer_unit_sel:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target2_conf_reg_t;
|
||||
|
||||
/** Type of comp2_load register
|
||||
* COMP2 synchronization register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp2_load : WT; bitpos: [0]; default: 0;
|
||||
* Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm
|
||||
* value/period to COMP2.\\
|
||||
* 0: No effect \\
|
||||
* 1: Enable COMP2 synchronization\\
|
||||
*/
|
||||
uint32_t timer_comp2_load:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp2_load_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER INTERRUPT REGISTER */
|
||||
/** Type of int_ena register
|
||||
* Interrupt enable register of system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
uint32_t target0_int_ena:1;
|
||||
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
uint32_t target1_int_ena:1;
|
||||
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* Write 1 to enable SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
uint32_t target2_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* Interrupt raw register of system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
uint32_t target0_int_raw:1;
|
||||
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
uint32_t target1_int_raw:1;
|
||||
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status of SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
uint32_t target2_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Interrupt clear register of system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
uint32_t target0_int_clr:1;
|
||||
/** target1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
uint32_t target1_int_clr:1;
|
||||
/** target2_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to clear SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
uint32_t target2_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Interrupt status register of system timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET0_INT.
|
||||
*/
|
||||
uint32_t target0_int_st:1;
|
||||
/** target1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET1_INT.
|
||||
*/
|
||||
uint32_t target1_int_st:1;
|
||||
/** target2_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The interrupt status of SYSTIMER_TARGET2_INT.
|
||||
*/
|
||||
uint32_t target2_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_st_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP0 STATUS REGISTER */
|
||||
/** Type of real_target0_lo register
|
||||
* Actual target value of COMP0, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, low 32 bits.
|
||||
*/
|
||||
uint32_t target0_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target0_lo_reg_t;
|
||||
|
||||
/** Type of real_target0_hi register
|
||||
* Actual target value of COMP0, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP0, high 20 bits.
|
||||
*/
|
||||
uint32_t target0_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target0_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP1 STATUS REGISTER */
|
||||
/** Type of real_target1_lo register
|
||||
* Actual target value of COMP1, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP1, low 32 bits.
|
||||
*/
|
||||
uint32_t target1_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target1_lo_reg_t;
|
||||
|
||||
/** Type of real_target1_hi register
|
||||
* Actual target value of COMP1, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target1_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP1, high 20 bits.
|
||||
*/
|
||||
uint32_t target1_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target1_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: SYSTEM TIMER COMP2 STATUS REGISTER */
|
||||
/** Type of real_target2_lo register
|
||||
* Actual target value of COMP2, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the actual target value of COMP2, low 32 bits.
|
||||
*/
|
||||
uint32_t target2_lo_ro:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target2_lo_reg_t;
|
||||
|
||||
/** Type of real_target2_hi register
|
||||
* Actual target value of COMP2, high 20 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target2_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* Represents the actual target value of COMP2, high 20 bits.
|
||||
*/
|
||||
uint32_t target2_hi_ro:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_real_target2_hi_reg_t;
|
||||
|
||||
|
||||
/** Group: VERSION REGISTER */
|
||||
/** Type of date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 36774432;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_unit0_op_reg_t unit0_op;
|
||||
volatile systimer_unit1_op_reg_t unit1_op;
|
||||
volatile systimer_unit0_load_hi_reg_t unit0_load_hi;
|
||||
volatile systimer_unit0_load_lo_reg_t unit0_load_lo;
|
||||
volatile systimer_unit1_load_hi_reg_t unit1_load_hi;
|
||||
volatile systimer_unit1_load_lo_reg_t unit1_load_lo;
|
||||
volatile systimer_target0_hi_reg_t target0_hi;
|
||||
volatile systimer_target0_lo_reg_t target0_lo;
|
||||
volatile systimer_target1_hi_reg_t target1_hi;
|
||||
volatile systimer_target1_lo_reg_t target1_lo;
|
||||
volatile systimer_target2_hi_reg_t target2_hi;
|
||||
volatile systimer_target2_lo_reg_t target2_lo;
|
||||
volatile systimer_target0_conf_reg_t target0_conf;
|
||||
volatile systimer_target1_conf_reg_t target1_conf;
|
||||
volatile systimer_target2_conf_reg_t target2_conf;
|
||||
volatile systimer_unit0_value_hi_reg_t unit0_value_hi;
|
||||
volatile systimer_unit0_value_lo_reg_t unit0_value_lo;
|
||||
volatile systimer_unit1_value_hi_reg_t unit1_value_hi;
|
||||
volatile systimer_unit1_value_lo_reg_t unit1_value_lo;
|
||||
volatile systimer_comp0_load_reg_t comp0_load;
|
||||
volatile systimer_comp1_load_reg_t comp1_load;
|
||||
volatile systimer_comp2_load_reg_t comp2_load;
|
||||
volatile systimer_unit0_load_reg_t unit0_load;
|
||||
volatile systimer_unit1_load_reg_t unit1_load;
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
volatile systimer_int_st_reg_t int_st;
|
||||
volatile systimer_real_target0_lo_reg_t real_target0_lo;
|
||||
volatile systimer_real_target0_hi_reg_t real_target0_hi;
|
||||
volatile systimer_real_target1_lo_reg_t real_target1_lo;
|
||||
volatile systimer_real_target1_hi_reg_t real_target1_hi;
|
||||
volatile systimer_real_target2_lo_reg_t real_target2_lo;
|
||||
volatile systimer_real_target2_hi_reg_t real_target2_hi;
|
||||
uint32_t reserved_08c[28];
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
||||
extern systimer_dev_t SYSTIMER;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(systimer_dev_t) == 0x100, "Invalid size of systimer_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,753 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0)
|
||||
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
#define TIMG_T0_USE_XTAL (BIT(9))
|
||||
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
|
||||
#define TIMG_T0_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_T0_USE_XTAL_S 9
|
||||
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_EN (BIT(10))
|
||||
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
|
||||
#define TIMG_T0_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T0_ALARM_EN_S 10
|
||||
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 0 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T0_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
|
||||
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T0_DIVCNT_RST_S 12
|
||||
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 0 clock (T0_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T0_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
|
||||
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_S 13
|
||||
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 0 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
|
||||
#define TIMG_T0_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T0_AUTORELOAD_S 29
|
||||
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 0 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 0 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T0_INCREASE (BIT(30))
|
||||
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
|
||||
#define TIMG_T0_INCREASE_V 0x00000001U
|
||||
#define TIMG_T0_INCREASE_S 30
|
||||
/** TIMG_T0_EN : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer 0 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T0_EN (BIT(31))
|
||||
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
|
||||
#define TIMG_T0_EN_V 0x00000001U
|
||||
#define TIMG_T0_EN_S 31
|
||||
|
||||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
|
||||
#define TIMG_T0_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_S 0
|
||||
|
||||
/** TIMG_T0HI_REG register
|
||||
* Timer 0 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_HI 0x003FFFFFU
|
||||
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
|
||||
#define TIMG_T0_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_HI_S 0
|
||||
|
||||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T0_UPDATE (BIT(31))
|
||||
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
|
||||
#define TIMG_T0_UPDATE_V 0x00000001U
|
||||
#define TIMG_T0_UPDATE_S 31
|
||||
|
||||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer 0 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
|
||||
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer 0 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
|
||||
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer 0 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 0 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
|
||||
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer 0 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 0 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
|
||||
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 0 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T0_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
|
||||
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_S 0
|
||||
|
||||
/** TIMG_T1CONFIG_REG register
|
||||
* Timer 1 configuration register
|
||||
*/
|
||||
#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24)
|
||||
/** TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
#define TIMG_T1_USE_XTAL (BIT(9))
|
||||
#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S)
|
||||
#define TIMG_T1_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_T1_USE_XTAL_S 9
|
||||
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_EN (BIT(10))
|
||||
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
|
||||
#define TIMG_T1_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T1_ALARM_EN_S 10
|
||||
/** TIMG_T1_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 1 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T1_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T1_DIVCNT_RST_M (TIMG_T1_DIVCNT_RST_V << TIMG_T1_DIVCNT_RST_S)
|
||||
#define TIMG_T1_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T1_DIVCNT_RST_S 12
|
||||
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 1 clock (T1_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T1_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
|
||||
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_S 13
|
||||
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 1 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T1_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
|
||||
#define TIMG_T1_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T1_AUTORELOAD_S 29
|
||||
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 1 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 1 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T1_INCREASE (BIT(30))
|
||||
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
|
||||
#define TIMG_T1_INCREASE_V 0x00000001U
|
||||
#define TIMG_T1_INCREASE_S 30
|
||||
/** TIMG_T1_EN : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer 1 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T1_EN (BIT(31))
|
||||
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
|
||||
#define TIMG_T1_EN_V 0x00000001U
|
||||
#define TIMG_T1_EN_S 31
|
||||
|
||||
/** TIMG_T1LO_REG register
|
||||
* Timer 1 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28)
|
||||
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
|
||||
#define TIMG_T1_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_S 0
|
||||
|
||||
/** TIMG_T1HI_REG register
|
||||
* Timer 1 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c)
|
||||
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_HI 0x003FFFFFU
|
||||
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
|
||||
#define TIMG_T1_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_HI_S 0
|
||||
|
||||
/** TIMG_T1UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30)
|
||||
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T1_UPDATE (BIT(31))
|
||||
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
|
||||
#define TIMG_T1_UPDATE_V 0x00000001U
|
||||
#define TIMG_T1_UPDATE_S 31
|
||||
|
||||
/** TIMG_T1ALARMLO_REG register
|
||||
* Timer 1 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34)
|
||||
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
|
||||
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T1ALARMHI_REG register
|
||||
* Timer 1 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38)
|
||||
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
|
||||
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T1LOADLO_REG register
|
||||
* Timer 1 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c)
|
||||
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 1 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
|
||||
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T1LOADHI_REG register
|
||||
* Timer 1 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40)
|
||||
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 1 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
|
||||
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T1LOAD_REG register
|
||||
* Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44)
|
||||
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 1 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T1_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
|
||||
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_S 12
|
||||
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_S 13
|
||||
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
|
||||
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
|
||||
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
|
||||
* choose WDT clock:0-apb_clk, 1-xtal_clk.
|
||||
*/
|
||||
#define TIMG_WDT_USE_XTAL (BIT(21))
|
||||
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
|
||||
#define TIMG_WDT_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_WDT_USE_XTAL_S 21
|
||||
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_S 22
|
||||
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG3 0x00000003U
|
||||
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
|
||||
#define TIMG_WDT_STG3_V 0x00000003U
|
||||
#define TIMG_WDT_STG3_S 23
|
||||
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG2 0x00000003U
|
||||
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
|
||||
#define TIMG_WDT_STG2_V 0x00000003U
|
||||
#define TIMG_WDT_STG2_S 25
|
||||
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG1 0x00000003U
|
||||
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
|
||||
#define TIMG_WDT_STG1_V 0x00000003U
|
||||
#define TIMG_WDT_STG1_S 27
|
||||
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG0 0x00000003U
|
||||
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
|
||||
#define TIMG_WDT_STG0_V 0x00000003U
|
||||
#define TIMG_WDT_STG0_S 29
|
||||
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_EN (BIT(31))
|
||||
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
|
||||
#define TIMG_WDT_EN_V 0x00000001U
|
||||
#define TIMG_WDT_EN_S 31
|
||||
|
||||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c)
|
||||
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_WDT_DIVCNT_RST (BIT(0))
|
||||
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
|
||||
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_WDT_DIVCNT_RST_S 0
|
||||
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
|
||||
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
|
||||
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
|
||||
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
|
||||
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
|
||||
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
#define TIMG_WDT_FEED 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
|
||||
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_S 0
|
||||
|
||||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_WKEY 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
|
||||
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_S 0
|
||||
|
||||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
|
||||
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_CYCLING_S 12
|
||||
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
|
||||
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_S 13
|
||||
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
||||
#define TIMG_RTC_CALI_RDY_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_RDY_S 15
|
||||
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_MAX 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
||||
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_S 16
|
||||
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START (BIT(31))
|
||||
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
||||
#define TIMG_RTC_CALI_START_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_S 31
|
||||
|
||||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
||||
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
||||
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_S 7
|
||||
|
||||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ENA (BIT(0))
|
||||
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
||||
#define TIMG_T0_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T0_INT_ENA_S 0
|
||||
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ENA (BIT(1))
|
||||
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
|
||||
#define TIMG_T1_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T1_INT_ENA_S 1
|
||||
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ENA (BIT(2))
|
||||
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
||||
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ENA_S 2
|
||||
|
||||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_RAW (BIT(0))
|
||||
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
||||
#define TIMG_T0_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T0_INT_RAW_S 0
|
||||
/** TIMG_T1_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_RAW (BIT(1))
|
||||
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
|
||||
#define TIMG_T1_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T1_INT_RAW_S 1
|
||||
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_RAW (BIT(2))
|
||||
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
||||
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
||||
#define TIMG_WDT_INT_RAW_S 2
|
||||
|
||||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ST (BIT(0))
|
||||
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
||||
#define TIMG_T0_INT_ST_V 0x00000001U
|
||||
#define TIMG_T0_INT_ST_S 0
|
||||
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ST (BIT(1))
|
||||
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
|
||||
#define TIMG_T1_INT_ST_V 0x00000001U
|
||||
#define TIMG_T1_INT_ST_S 1
|
||||
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ST (BIT(2))
|
||||
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
||||
#define TIMG_WDT_INT_ST_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ST_S 2
|
||||
|
||||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_CLR (BIT(0))
|
||||
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
||||
#define TIMG_T0_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T0_INT_CLR_S 0
|
||||
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_CLR (BIT(1))
|
||||
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
|
||||
#define TIMG_T1_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T1_INT_CLR_S 1
|
||||
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_CLR (BIT(2))
|
||||
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
||||
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
||||
#define TIMG_WDT_INT_CLR_S 2
|
||||
|
||||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
||||
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
||||
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
||||
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
||||
|
||||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8)
|
||||
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
|
||||
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_S 0
|
||||
|
||||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc)
|
||||
/** TIMG_ETM_EN : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
#define TIMG_ETM_EN (BIT(28))
|
||||
#define TIMG_ETM_EN_M (TIMG_ETM_EN_V << TIMG_ETM_EN_S)
|
||||
#define TIMG_ETM_EN_V 0x00000001U
|
||||
#define TIMG_ETM_EN_S 28
|
||||
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
|
||||
* enable WDT's clock
|
||||
*/
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
|
||||
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
|
||||
* enable Timer $x's clock
|
||||
*/
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
|
||||
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
#define TIMG_CLK_EN (BIT(31))
|
||||
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
||||
#define TIMG_CLK_EN_V 0x00000001U
|
||||
#define TIMG_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,740 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: T0 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
uint32_t tx_use_xtal:1;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst:1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider:16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload:1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase:1;
|
||||
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: T1 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:9;
|
||||
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
uint32_t tx_use_xtal:1;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en:1;
|
||||
uint32_t reserved_11:1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst:1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider:16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload:1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase:1;
|
||||
/** tx_en : R/W/SS/SC; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_Tx_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TxUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi:22;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_Tx_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: WDT Control and configuration registers */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en:1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en:1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en:1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length:3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length:3;
|
||||
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
|
||||
* choose WDT clock:0-apb_clk, 1-xtal_clk.
|
||||
*/
|
||||
uint32_t wdt_use_xtal:1;
|
||||
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
uint32_t wdt_conf_update_en:1;
|
||||
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg3:2;
|
||||
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg2:2;
|
||||
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg1:2;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg0:2;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig0_reg_t;
|
||||
|
||||
/** Type of wdtconfig1 register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t wdt_divcnt_rst:1;
|
||||
uint32_t reserved_1:15;
|
||||
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
uint32_t wdt_clk_prescale:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig1_reg_t;
|
||||
|
||||
/** Type of wdtconfig2 register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig2_reg_t;
|
||||
|
||||
/** Type of wdtconfig3 register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig3_reg_t;
|
||||
|
||||
/** Type of wdtconfig4 register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig4_reg_t;
|
||||
|
||||
/** Type of wdtconfig5 register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig5_reg_t;
|
||||
|
||||
/** Type of wdtfeed register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
uint32_t wdt_feed:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtfeed_reg_t;
|
||||
|
||||
/** Type of wdtwprotect register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtwprotect_reg_t;
|
||||
|
||||
|
||||
/** Group: RTC CALI Control and configuration registers */
|
||||
/** Type of rtccalicfg register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:12;
|
||||
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
|
||||
* 0: one-shot frequency calculation,1: periodic frequency calculation,
|
||||
*/
|
||||
uint32_t rtc_cali_start_cycling:1;
|
||||
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 0;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
uint32_t rtc_cali_clk_sel:2;
|
||||
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
|
||||
* indicate one-shot frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_rdy:1;
|
||||
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
|
||||
* Configure the time to calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_max:15;
|
||||
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to start one-shot frequency calculation.
|
||||
*/
|
||||
uint32_t rtc_cali_start:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg_reg_t;
|
||||
|
||||
/** Type of rtccalicfg1 register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
|
||||
* indicate periodic frequency calculation is done.
|
||||
*/
|
||||
uint32_t rtc_cali_cycling_data_vld:1;
|
||||
uint32_t reserved_1:6;
|
||||
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
|
||||
* When one-shot or periodic frequency calculation is done, read this value to
|
||||
* calculate RTC slow clock's frequency.
|
||||
*/
|
||||
uint32_t rtc_cali_value:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg1_reg_t;
|
||||
|
||||
/** Type of rtccalicfg2 register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
uint32_t rtc_cali_timeout:1;
|
||||
uint32_t reserved_1:2;
|
||||
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_rst_cnt:4;
|
||||
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_thres:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg2_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_ena_timers register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_ena:1;
|
||||
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_ena:1;
|
||||
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_ena:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_ena_timers_reg_t;
|
||||
|
||||
/** Type of int_raw_timers register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_raw:1;
|
||||
/** t1_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_raw:1;
|
||||
/** wdt_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_raw:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_raw_timers_reg_t;
|
||||
|
||||
/** Type of int_st_timers register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_st:1;
|
||||
/** t1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_st:1;
|
||||
/** wdt_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_st:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_st_timers_reg_t;
|
||||
|
||||
/** Type of int_clr_timers register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_clr:1;
|
||||
/** t1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_clr:1;
|
||||
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_clr_timers_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of ntimers_date register
|
||||
* Timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ntimgs_date : R/W; bitpos: [27:0]; default: 35688770;
|
||||
* Timer version control register
|
||||
*/
|
||||
uint32_t ntimgs_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_ntimers_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock configuration registers */
|
||||
/** Type of regclk register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:28;
|
||||
/** etm_en : R/W; bitpos: [28]; default: 1;
|
||||
* enable timer's etm task and event
|
||||
*/
|
||||
uint32_t etm_en:1;
|
||||
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
|
||||
* enable WDT's clock
|
||||
*/
|
||||
uint32_t wdt_clk_is_active:1;
|
||||
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
|
||||
* enable Timer $x's clock
|
||||
*/
|
||||
uint32_t timer_clk_is_active:1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_regclk_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile timg_txconfig_reg_t config;
|
||||
volatile timg_txlo_reg_t lo;
|
||||
volatile timg_txhi_reg_t hi;
|
||||
volatile timg_txupdate_reg_t update;
|
||||
volatile timg_txalarmlo_reg_t alarmlo;
|
||||
volatile timg_txalarmhi_reg_t alarmhi;
|
||||
volatile timg_txloadlo_reg_t loadlo;
|
||||
volatile timg_txloadhi_reg_t loadhi;
|
||||
volatile timg_txload_reg_t load;
|
||||
} timg_hwtimer_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile timg_hwtimer_reg_t hw_timer[2];
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
||||
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
||||
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
||||
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
||||
volatile timg_wdtfeed_reg_t wdtfeed;
|
||||
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
||||
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
||||
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
||||
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
||||
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
||||
volatile timg_int_st_timers_reg_t int_st_timers;
|
||||
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
||||
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
||||
uint32_t reserved_084[29];
|
||||
volatile timg_ntimers_date_reg_t ntimers_date;
|
||||
volatile timg_regclk_reg_t regclk;
|
||||
} timg_dev_t;
|
||||
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
Plik diff jest za duży
Load Diff
|
|
@ -0,0 +1,980 @@
|
|||
/**
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Registers */
|
||||
/** Type of ep1 register
|
||||
* FIFO access for the CDC-ACM data IN and OUT endpoints.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
|
||||
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
|
||||
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
|
||||
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
|
||||
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
|
||||
* how many data is received, then read data from UART Rx FIFO.
|
||||
*/
|
||||
uint32_t rdwr_byte:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_ep1_reg_t;
|
||||
|
||||
/** Type of ep1_conf register
|
||||
* Configuration and control registers for the CDC-ACM FIFOs.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wr_done : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
|
||||
*/
|
||||
uint32_t wr_done:1;
|
||||
/** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
|
||||
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
|
||||
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
|
||||
* USB Host.
|
||||
*/
|
||||
uint32_t serial_in_ep_data_free:1;
|
||||
/** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
|
||||
* 1'b1: Indicate there is data in UART Rx FIFO.
|
||||
*/
|
||||
uint32_t serial_out_ep_data_avail:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_ep1_conf_reg_t;
|
||||
|
||||
/** Type of conf0 register
|
||||
* PHY hardware configuration.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** phy_sel : R/W; bitpos: [0]; default: 0;
|
||||
* Select internal/external PHY
|
||||
*/
|
||||
uint32_t phy_sel:1;
|
||||
/** exchg_pins_override : R/W; bitpos: [1]; default: 0;
|
||||
* Enable software control USB D+ D- exchange
|
||||
*/
|
||||
uint32_t exchg_pins_override:1;
|
||||
/** exchg_pins : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ D- exchange
|
||||
*/
|
||||
uint32_t exchg_pins:1;
|
||||
/** vrefh : R/W; bitpos: [4:3]; default: 0;
|
||||
* Control single-end input high threshold,1.76V to 2V, step 80mV
|
||||
*/
|
||||
uint32_t vrefh:2;
|
||||
/** vrefl : R/W; bitpos: [6:5]; default: 0;
|
||||
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
|
||||
*/
|
||||
uint32_t vrefl:2;
|
||||
/** vref_override : R/W; bitpos: [7]; default: 0;
|
||||
* Enable software control input threshold
|
||||
*/
|
||||
uint32_t vref_override:1;
|
||||
/** pad_pull_override : R/W; bitpos: [8]; default: 0;
|
||||
* Enable software control USB D+ D- pullup pulldown
|
||||
*/
|
||||
uint32_t pad_pull_override:1;
|
||||
/** dp_pullup : R/W; bitpos: [9]; default: 1;
|
||||
* Control USB D+ pull up.
|
||||
*/
|
||||
uint32_t dp_pullup:1;
|
||||
/** dp_pulldown : R/W; bitpos: [10]; default: 0;
|
||||
* Control USB D+ pull down.
|
||||
*/
|
||||
uint32_t dp_pulldown:1;
|
||||
/** dm_pullup : R/W; bitpos: [11]; default: 0;
|
||||
* Control USB D- pull up.
|
||||
*/
|
||||
uint32_t dm_pullup:1;
|
||||
/** dm_pulldown : R/W; bitpos: [12]; default: 0;
|
||||
* Control USB D- pull down.
|
||||
*/
|
||||
uint32_t dm_pulldown:1;
|
||||
/** pullup_value : R/W; bitpos: [13]; default: 0;
|
||||
* Control pull up value.
|
||||
*/
|
||||
uint32_t pullup_value:1;
|
||||
/** usb_pad_enable : R/W; bitpos: [14]; default: 1;
|
||||
* Enable USB pad function.
|
||||
*/
|
||||
uint32_t usb_pad_enable:1;
|
||||
/** usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
|
||||
* Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
|
||||
* disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
|
||||
* through GPIO Matrix.
|
||||
*/
|
||||
uint32_t usb_jtag_bridge_en:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_conf0_reg_t;
|
||||
|
||||
/** Type of test register
|
||||
* Registers used for debugging the PHY.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** test_enable : R/W; bitpos: [0]; default: 0;
|
||||
* Enable test of the USB pad
|
||||
*/
|
||||
uint32_t test_enable:1;
|
||||
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in test
|
||||
*/
|
||||
uint32_t test_usb_oe:1;
|
||||
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in test
|
||||
*/
|
||||
uint32_t test_tx_dp:1;
|
||||
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in test
|
||||
*/
|
||||
uint32_t test_tx_dm:1;
|
||||
/** test_rx_rcv : RO; bitpos: [4]; default: 1;
|
||||
* USB RCV value in test
|
||||
*/
|
||||
uint32_t test_rx_rcv:1;
|
||||
/** test_rx_dp : RO; bitpos: [5]; default: 1;
|
||||
* USB D+ rx value in test
|
||||
*/
|
||||
uint32_t test_rx_dp:1;
|
||||
/** test_rx_dm : RO; bitpos: [6]; default: 0;
|
||||
* USB D- rx value in test
|
||||
*/
|
||||
uint32_t test_rx_dm:1;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_test_reg_t;
|
||||
|
||||
/** Type of misc_conf register
|
||||
* Clock enable control
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** clk_en : R/W; bitpos: [0]; default: 0;
|
||||
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
|
||||
* registers.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_misc_conf_reg_t;
|
||||
|
||||
/** Type of mem_conf register
|
||||
* Memory power control
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usb_mem_pd : R/W; bitpos: [0]; default: 0;
|
||||
* 1: power down usb memory.
|
||||
*/
|
||||
uint32_t usb_mem_pd:1;
|
||||
/** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
|
||||
* 1: Force clock on for usb memory.
|
||||
*/
|
||||
uint32_t usb_mem_clk_en:1;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_mem_conf_reg_t;
|
||||
|
||||
/** Type of chip_rst register
|
||||
* CDC-ACM chip reset control.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rts : RO; bitpos: [0]; default: 0;
|
||||
* 1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
|
||||
*/
|
||||
uint32_t rts:1;
|
||||
/** dtr : RO; bitpos: [1]; default: 0;
|
||||
* 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
|
||||
*/
|
||||
uint32_t dtr:1;
|
||||
/** usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
|
||||
* Set this bit to disable chip reset from usb serial channel to reset chip.
|
||||
*/
|
||||
uint32_t usb_uart_chip_rst_dis:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_chip_rst_reg_t;
|
||||
|
||||
/** Type of get_line_code_w0 register
|
||||
* W0 of GET_LINE_CODING command.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
|
||||
* The value of dwDTERate set by software which is requested by GET_LINE_CODING
|
||||
* command.
|
||||
*/
|
||||
uint32_t get_dw_dte_rate:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_get_line_code_w0_reg_t;
|
||||
|
||||
/** Type of get_line_code_w1 register
|
||||
* W1 of GET_LINE_CODING command.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
|
||||
* The value of bCharFormat set by software which is requested by GET_LINE_CODING
|
||||
* command.
|
||||
*/
|
||||
uint32_t get_bdata_bits:8;
|
||||
/** get_bparity_type : R/W; bitpos: [15:8]; default: 0;
|
||||
* The value of bParityTpye set by software which is requested by GET_LINE_CODING
|
||||
* command.
|
||||
*/
|
||||
uint32_t get_bparity_type:8;
|
||||
/** get_bchar_format : R/W; bitpos: [23:16]; default: 0;
|
||||
* The value of bDataBits set by software which is requested by GET_LINE_CODING
|
||||
* command.
|
||||
*/
|
||||
uint32_t get_bchar_format:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_get_line_code_w1_reg_t;
|
||||
|
||||
/** Type of config_update register
|
||||
* Configuration registers' value update
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** config_update : WT; bitpos: [0]; default: 0;
|
||||
* Write 1 to this register would update the value of configure registers from APB
|
||||
* clock domain to 48MHz clock domain.
|
||||
*/
|
||||
uint32_t config_update:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_config_update_reg_t;
|
||||
|
||||
/** Type of ser_afifo_config register
|
||||
* Serial AFIFO configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
|
||||
* Write 1 to reset CDC_ACM IN async FIFO write clock domain.
|
||||
*/
|
||||
uint32_t serial_in_afifo_reset_wr:1;
|
||||
/** serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
|
||||
* Write 1 to reset CDC_ACM IN async FIFO read clock domain.
|
||||
*/
|
||||
uint32_t serial_in_afifo_reset_rd:1;
|
||||
/** serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
|
||||
* Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
|
||||
*/
|
||||
uint32_t serial_out_afifo_reset_wr:1;
|
||||
/** serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
|
||||
* Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
|
||||
*/
|
||||
uint32_t serial_out_afifo_reset_rd:1;
|
||||
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
|
||||
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
|
||||
*/
|
||||
uint32_t serial_out_afifo_rempty:1;
|
||||
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
|
||||
* CDC_ACM OUT IN async FIFO empty signal in write clock domain.
|
||||
*/
|
||||
uint32_t serial_in_afifo_wfull:1;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_ser_afifo_config_reg_t;
|
||||
|
||||
/** Type of serial_ep_timeout0 register
|
||||
* USB uart out endpoint timeout configuration.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** serial_timeout_en : R/W; bitpos: [0]; default: 0;
|
||||
* USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
|
||||
* is automatically cleared and reg_serial_timeout_status is asserted.
|
||||
*/
|
||||
uint32_t serial_timeout_en:1;
|
||||
/** serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* Serial out ep triggers a timeout event.
|
||||
*/
|
||||
uint32_t serial_timeout_status:1;
|
||||
/** serial_timeout_status_clr : WT; bitpos: [2]; default: 0;
|
||||
* Write 1 to clear reg_serial_timeout_status.
|
||||
*/
|
||||
uint32_t serial_timeout_status_clr:1;
|
||||
uint32_t reserved_3:29;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_serial_ep_timeout0_reg_t;
|
||||
|
||||
/** Type of serial_ep_timeout1 register
|
||||
* USB uart out endpoint timeout configuration.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768;
|
||||
* USB serial out ep timeout max threshold value, indicates the maximum time that
|
||||
* waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
|
||||
*/
|
||||
uint32_t serial_timeout_max:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_serial_ep_timeout1_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Registers */
|
||||
/** Type of int_raw register
|
||||
* Interrupt raw status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt bit turns to high level when flush cmd is received for IN
|
||||
* endpoint 2 of JTAG.
|
||||
*/
|
||||
uint32_t jtag_in_flush_int_raw:1;
|
||||
/** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt bit turns to high level when SOF frame is received.
|
||||
*/
|
||||
uint32_t sof_int_raw:1;
|
||||
/** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
|
||||
* one packet.
|
||||
*/
|
||||
uint32_t serial_out_recv_pkt_int_raw:1;
|
||||
/** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
|
||||
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
|
||||
*/
|
||||
uint32_t serial_in_empty_int_raw:1;
|
||||
/** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
* The raw interrupt bit turns to high level when pid error is detected.
|
||||
*/
|
||||
uint32_t pid_err_int_raw:1;
|
||||
/** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
* The raw interrupt bit turns to high level when CRC5 error is detected.
|
||||
*/
|
||||
uint32_t crc5_err_int_raw:1;
|
||||
/** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
* The raw interrupt bit turns to high level when CRC16 error is detected.
|
||||
*/
|
||||
uint32_t crc16_err_int_raw:1;
|
||||
/** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
|
||||
* The raw interrupt bit turns to high level when stuff error is detected.
|
||||
*/
|
||||
uint32_t stuff_err_int_raw:1;
|
||||
/** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
|
||||
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
|
||||
* received.
|
||||
*/
|
||||
uint32_t in_token_rec_in_ep1_int_raw:1;
|
||||
/** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
|
||||
* The raw interrupt bit turns to high level when usb bus reset is detected.
|
||||
*/
|
||||
uint32_t usb_bus_reset_int_raw:1;
|
||||
/** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
|
||||
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
|
||||
* zero palyload.
|
||||
*/
|
||||
uint32_t out_ep1_zero_payload_int_raw:1;
|
||||
/** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
|
||||
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
|
||||
* zero palyload.
|
||||
*/
|
||||
uint32_t out_ep2_zero_payload_int_raw:1;
|
||||
/** rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
|
||||
* The raw interrupt bit turns to high level when level of RTS from usb serial channel
|
||||
* is changed.
|
||||
*/
|
||||
uint32_t rts_chg_int_raw:1;
|
||||
/** dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
|
||||
* The raw interrupt bit turns to high level when level of DTR from usb serial channel
|
||||
* is changed.
|
||||
*/
|
||||
uint32_t dtr_chg_int_raw:1;
|
||||
/** get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
|
||||
* The raw interrupt bit turns to high level when level of GET LINE CODING request is
|
||||
* received.
|
||||
*/
|
||||
uint32_t get_line_code_int_raw:1;
|
||||
/** set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
|
||||
* The raw interrupt bit turns to high level when level of SET LINE CODING request is
|
||||
* received.
|
||||
*/
|
||||
uint32_t set_line_code_int_raw:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Interrupt status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
|
||||
*/
|
||||
uint32_t jtag_in_flush_int_st:1;
|
||||
/** sof_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
|
||||
*/
|
||||
uint32_t sof_int_st:1;
|
||||
/** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* interrupt.
|
||||
*/
|
||||
uint32_t serial_out_recv_pkt_int_st:1;
|
||||
/** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
|
||||
*/
|
||||
uint32_t serial_in_empty_int_st:1;
|
||||
/** pid_err_int_st : RO; bitpos: [4]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t pid_err_int_st:1;
|
||||
/** crc5_err_int_st : RO; bitpos: [5]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc5_err_int_st:1;
|
||||
/** crc16_err_int_st : RO; bitpos: [6]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc16_err_int_st:1;
|
||||
/** stuff_err_int_st : RO; bitpos: [7]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t stuff_err_int_st:1;
|
||||
/** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
|
||||
* interrupt.
|
||||
*/
|
||||
uint32_t in_token_rec_in_ep1_int_st:1;
|
||||
/** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
|
||||
*/
|
||||
uint32_t usb_bus_reset_int_st:1;
|
||||
/** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
uint32_t out_ep1_zero_payload_int_st:1;
|
||||
/** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
uint32_t out_ep2_zero_payload_int_st:1;
|
||||
/** rts_chg_int_st : RO; bitpos: [12]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t rts_chg_int_st:1;
|
||||
/** dtr_chg_int_st : RO; bitpos: [13]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t dtr_chg_int_st:1;
|
||||
/** get_line_code_int_st : RO; bitpos: [14]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t get_line_code_int_st:1;
|
||||
/** set_line_code_int_st : RO; bitpos: [15]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t set_line_code_int_st:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Interrupt enable status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
|
||||
*/
|
||||
uint32_t jtag_in_flush_int_ena:1;
|
||||
/** sof_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
|
||||
*/
|
||||
uint32_t sof_int_ena:1;
|
||||
/** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
|
||||
*/
|
||||
uint32_t serial_out_recv_pkt_int_ena:1;
|
||||
/** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
|
||||
*/
|
||||
uint32_t serial_in_empty_int_ena:1;
|
||||
/** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t pid_err_int_ena:1;
|
||||
/** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc5_err_int_ena:1;
|
||||
/** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc16_err_int_ena:1;
|
||||
/** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t stuff_err_int_ena:1;
|
||||
/** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
|
||||
*/
|
||||
uint32_t in_token_rec_in_ep1_int_ena:1;
|
||||
/** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
|
||||
*/
|
||||
uint32_t usb_bus_reset_int_ena:1;
|
||||
/** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
|
||||
*/
|
||||
uint32_t out_ep1_zero_payload_int_ena:1;
|
||||
/** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
|
||||
*/
|
||||
uint32_t out_ep2_zero_payload_int_ena:1;
|
||||
/** rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t rts_chg_int_ena:1;
|
||||
/** dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t dtr_chg_int_ena:1;
|
||||
/** get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t get_line_code_int_ena:1;
|
||||
/** set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t set_line_code_int_ena:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Interrupt clear status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
|
||||
*/
|
||||
uint32_t jtag_in_flush_int_clr:1;
|
||||
/** sof_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
|
||||
*/
|
||||
uint32_t sof_int_clr:1;
|
||||
/** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
|
||||
*/
|
||||
uint32_t serial_out_recv_pkt_int_clr:1;
|
||||
/** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
|
||||
*/
|
||||
uint32_t serial_in_empty_int_clr:1;
|
||||
/** pid_err_int_clr : WT; bitpos: [4]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t pid_err_int_clr:1;
|
||||
/** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc5_err_int_clr:1;
|
||||
/** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t crc16_err_int_clr:1;
|
||||
/** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
|
||||
*/
|
||||
uint32_t stuff_err_int_clr:1;
|
||||
/** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
|
||||
*/
|
||||
uint32_t in_token_rec_in_ep1_int_clr:1;
|
||||
/** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
|
||||
*/
|
||||
uint32_t usb_bus_reset_int_clr:1;
|
||||
/** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
|
||||
*/
|
||||
uint32_t out_ep1_zero_payload_int_clr:1;
|
||||
/** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
|
||||
*/
|
||||
uint32_t out_ep2_zero_payload_int_clr:1;
|
||||
/** rts_chg_int_clr : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t rts_chg_int_clr:1;
|
||||
/** dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
|
||||
*/
|
||||
uint32_t dtr_chg_int_clr:1;
|
||||
/** get_line_code_int_clr : WT; bitpos: [14]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t get_line_code_int_clr:1;
|
||||
/** set_line_code_int_clr : WT; bitpos: [15]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
|
||||
*/
|
||||
uint32_t set_line_code_int_clr:1;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Registers */
|
||||
/** Type of jfifo_st register
|
||||
* JTAG FIFO status and control registers.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
|
||||
* JTAT in fifo counter.
|
||||
*/
|
||||
uint32_t in_fifo_cnt:2;
|
||||
/** in_fifo_empty : RO; bitpos: [2]; default: 1;
|
||||
* 1: JTAG in fifo is empty.
|
||||
*/
|
||||
uint32_t in_fifo_empty:1;
|
||||
/** in_fifo_full : RO; bitpos: [3]; default: 0;
|
||||
* 1: JTAG in fifo is full.
|
||||
*/
|
||||
uint32_t in_fifo_full:1;
|
||||
/** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
|
||||
* JTAT out fifo counter.
|
||||
*/
|
||||
uint32_t out_fifo_cnt:2;
|
||||
/** out_fifo_empty : RO; bitpos: [6]; default: 1;
|
||||
* 1: JTAG out fifo is empty.
|
||||
*/
|
||||
uint32_t out_fifo_empty:1;
|
||||
/** out_fifo_full : RO; bitpos: [7]; default: 0;
|
||||
* 1: JTAG out fifo is full.
|
||||
*/
|
||||
uint32_t out_fifo_full:1;
|
||||
/** in_fifo_reset : R/W; bitpos: [8]; default: 0;
|
||||
* Write 1 to reset JTAG in fifo.
|
||||
*/
|
||||
uint32_t in_fifo_reset:1;
|
||||
/** out_fifo_reset : R/W; bitpos: [9]; default: 0;
|
||||
* Write 1 to reset JTAG out fifo.
|
||||
*/
|
||||
uint32_t out_fifo_reset:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_jfifo_st_reg_t;
|
||||
|
||||
/** Type of fram_num register
|
||||
* Last received SOF frame index register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sof_frame_index : RO; bitpos: [10:0]; default: 0;
|
||||
* Frame index of received SOF frame.
|
||||
*/
|
||||
uint32_t sof_frame_index:11;
|
||||
uint32_t reserved_11:21;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_fram_num_reg_t;
|
||||
|
||||
/** Type of in_ep0_st register
|
||||
* Control IN endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** in_ep0_state : RO; bitpos: [1:0]; default: 1;
|
||||
* State of IN Endpoint 0.
|
||||
*/
|
||||
uint32_t in_ep0_state:2;
|
||||
/** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of IN endpoint 0.
|
||||
*/
|
||||
uint32_t in_ep0_wr_addr:7;
|
||||
/** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of IN endpoint 0.
|
||||
*/
|
||||
uint32_t in_ep0_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_in_ep0_st_reg_t;
|
||||
|
||||
/** Type of in_ep1_st register
|
||||
* CDC-ACM IN endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** in_ep1_state : RO; bitpos: [1:0]; default: 1;
|
||||
* State of IN Endpoint 1.
|
||||
*/
|
||||
uint32_t in_ep1_state:2;
|
||||
/** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of IN endpoint 1.
|
||||
*/
|
||||
uint32_t in_ep1_wr_addr:7;
|
||||
/** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of IN endpoint 1.
|
||||
*/
|
||||
uint32_t in_ep1_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_in_ep1_st_reg_t;
|
||||
|
||||
/** Type of in_ep2_st register
|
||||
* CDC-ACM interrupt IN endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** in_ep2_state : RO; bitpos: [1:0]; default: 1;
|
||||
* State of IN Endpoint 2.
|
||||
*/
|
||||
uint32_t in_ep2_state:2;
|
||||
/** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of IN endpoint 2.
|
||||
*/
|
||||
uint32_t in_ep2_wr_addr:7;
|
||||
/** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of IN endpoint 2.
|
||||
*/
|
||||
uint32_t in_ep2_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_in_ep2_st_reg_t;
|
||||
|
||||
/** Type of in_ep3_st register
|
||||
* JTAG IN endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** in_ep3_state : RO; bitpos: [1:0]; default: 1;
|
||||
* State of IN Endpoint 3.
|
||||
*/
|
||||
uint32_t in_ep3_state:2;
|
||||
/** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of IN endpoint 3.
|
||||
*/
|
||||
uint32_t in_ep3_wr_addr:7;
|
||||
/** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of IN endpoint 3.
|
||||
*/
|
||||
uint32_t in_ep3_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_in_ep3_st_reg_t;
|
||||
|
||||
/** Type of out_ep0_st register
|
||||
* Control OUT endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** out_ep0_state : RO; bitpos: [1:0]; default: 0;
|
||||
* State of OUT Endpoint 0.
|
||||
*/
|
||||
uint32_t out_ep0_state:2;
|
||||
/** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
|
||||
*/
|
||||
uint32_t out_ep0_wr_addr:7;
|
||||
/** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of OUT endpoint 0.
|
||||
*/
|
||||
uint32_t out_ep0_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_out_ep0_st_reg_t;
|
||||
|
||||
/** Type of out_ep1_st register
|
||||
* CDC-ACM OUT endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** out_ep1_state : RO; bitpos: [1:0]; default: 0;
|
||||
* State of OUT Endpoint 1.
|
||||
*/
|
||||
uint32_t out_ep1_state:2;
|
||||
/** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
|
||||
*/
|
||||
uint32_t out_ep1_wr_addr:7;
|
||||
/** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of OUT endpoint 1.
|
||||
*/
|
||||
uint32_t out_ep1_rd_addr:7;
|
||||
/** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
|
||||
* Data count in OUT endpoint 1 when one packet is received.
|
||||
*/
|
||||
uint32_t out_ep1_rec_data_cnt:7;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_out_ep1_st_reg_t;
|
||||
|
||||
/** Type of out_ep2_st register
|
||||
* JTAG OUT endpoint status information.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** out_ep2_state : RO; bitpos: [1:0]; default: 0;
|
||||
* State of OUT Endpoint 2.
|
||||
*/
|
||||
uint32_t out_ep2_state:2;
|
||||
/** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
|
||||
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
|
||||
*/
|
||||
uint32_t out_ep2_wr_addr:7;
|
||||
/** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
|
||||
* Read data address of OUT endpoint 2.
|
||||
*/
|
||||
uint32_t out_ep2_rd_addr:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_out_ep2_st_reg_t;
|
||||
|
||||
/** Type of set_line_code_w0 register
|
||||
* W0 of SET_LINE_CODING command.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dw_dte_rate : RO; bitpos: [31:0]; default: 0;
|
||||
* The value of dwDTERate set by host through SET_LINE_CODING command.
|
||||
*/
|
||||
uint32_t dw_dte_rate:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_set_line_code_w0_reg_t;
|
||||
|
||||
/** Type of set_line_code_w1 register
|
||||
* W1 of SET_LINE_CODING command.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bchar_format : RO; bitpos: [7:0]; default: 0;
|
||||
* The value of bCharFormat set by host through SET_LINE_CODING command.
|
||||
*/
|
||||
uint32_t bchar_format:8;
|
||||
/** bparity_type : RO; bitpos: [15:8]; default: 0;
|
||||
* The value of bParityTpye set by host through SET_LINE_CODING command.
|
||||
*/
|
||||
uint32_t bparity_type:8;
|
||||
/** bdata_bits : RO; bitpos: [23:16]; default: 0;
|
||||
* The value of bDataBits set by host through SET_LINE_CODING command.
|
||||
*/
|
||||
uint32_t bdata_bits:8;
|
||||
uint32_t reserved_24:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_set_line_code_w1_reg_t;
|
||||
|
||||
/** Type of bus_reset_st register
|
||||
* USB Bus reset status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** usb_bus_reset_st : RO; bitpos: [0]; default: 1;
|
||||
* USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
|
||||
* reset is released.
|
||||
*/
|
||||
uint32_t usb_bus_reset_st:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_bus_reset_st_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Registers */
|
||||
/** Type of date register
|
||||
* Date register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 36770368;
|
||||
* register version.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_serial_jtag_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile usb_serial_jtag_ep1_reg_t ep1;
|
||||
volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
|
||||
volatile usb_serial_jtag_int_raw_reg_t int_raw;
|
||||
volatile usb_serial_jtag_int_st_reg_t int_st;
|
||||
volatile usb_serial_jtag_int_ena_reg_t int_ena;
|
||||
volatile usb_serial_jtag_int_clr_reg_t int_clr;
|
||||
volatile usb_serial_jtag_conf0_reg_t conf0;
|
||||
volatile usb_serial_jtag_test_reg_t test;
|
||||
volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
|
||||
volatile usb_serial_jtag_fram_num_reg_t fram_num;
|
||||
volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
|
||||
volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
|
||||
volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
|
||||
volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
|
||||
volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
|
||||
volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
|
||||
volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
|
||||
volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
|
||||
volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
|
||||
volatile usb_serial_jtag_chip_rst_reg_t chip_rst;
|
||||
volatile usb_serial_jtag_set_line_code_w0_reg_t set_line_code_w0;
|
||||
volatile usb_serial_jtag_set_line_code_w1_reg_t set_line_code_w1;
|
||||
volatile usb_serial_jtag_get_line_code_w0_reg_t get_line_code_w0;
|
||||
volatile usb_serial_jtag_get_line_code_w1_reg_t get_line_code_w1;
|
||||
volatile usb_serial_jtag_config_update_reg_t config_update;
|
||||
volatile usb_serial_jtag_ser_afifo_config_reg_t ser_afifo_config;
|
||||
volatile usb_serial_jtag_bus_reset_st_reg_t bus_reset_st;
|
||||
volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_ep_timeout0;
|
||||
volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_ep_timeout1;
|
||||
uint32_t reserved_074[3];
|
||||
volatile usb_serial_jtag_date_reg_t date;
|
||||
} usb_serial_jtag_dev_t;
|
||||
|
||||
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/interrupts.h"
|
||||
|
||||
const char *const esp_isr_names[] = {
|
||||
[0] = "WIFI_MAC",
|
||||
[1] = "WIFI_MAC_NMI",
|
||||
[2] = "WIFI_PWR",
|
||||
[3] = "WIFI_BB",
|
||||
[4] = "BT_MAC",
|
||||
[5] = "BT_BB",
|
||||
[6] = "BT_BB_NMI",
|
||||
[7] = "LP_TIMER",
|
||||
[8] = "COEX",
|
||||
[9] = "BLE_TIMER",
|
||||
[10] = "BLE_SEC",
|
||||
[11] = "I2C_MST",
|
||||
[12] = "ZB_MAC",
|
||||
[13] = "PMU",
|
||||
[14] = "EFUSE",
|
||||
[15] = "LP_RTC_TIMER",
|
||||
[16] = "LP_WDT",
|
||||
[17] = "LP_PERI_TIMEOUT",
|
||||
[18] = "LP_APM_M0",
|
||||
[19] = "CPU_FROM_CPU_0",
|
||||
[20] = "CPU_FROM_CPU_1",
|
||||
[21] = "CPU_FROM_CPU_2",
|
||||
[22] = "CPU_FROM_CPU_3",
|
||||
[23] = "ASSIST_DEBUG",
|
||||
[24] = "TRACE",
|
||||
[25] = "CACHE",
|
||||
[26] = "CPU_PERI_TIMEOUT",
|
||||
[27] = "GPIO_INTERRUPT_PRO",
|
||||
[28] = "GPIO_INTERRUPT_EXT",
|
||||
[29] = "PAU",
|
||||
[30] = "HP_PERI_TIMEOUT",
|
||||
[31] = "MODEM_PERI_TIMEOUT",
|
||||
[32] = "HP_APM_M0",
|
||||
[33] = "HP_APM_M1",
|
||||
[34] = "HP_APM_M2",
|
||||
[35] = "HP_APM_M3",
|
||||
[36] = "MSPI",
|
||||
[37] = "I2S1",
|
||||
[38] = "UART0",
|
||||
[39] = "UART1",
|
||||
[40] = "UART2",
|
||||
[41] = "LEDC",
|
||||
[42] = "USB",
|
||||
[43] = "I2C_EXT0",
|
||||
[44] = "TG0_T0",
|
||||
[45] = "TG0_T1",
|
||||
[46] = "TG0_WDT",
|
||||
[47] = "TG1_T0",
|
||||
[48] = "TG1_T1",
|
||||
[49] = "TG1_WDT",
|
||||
[50] = "SYSTIMER_TARGET0",
|
||||
[51] = "SYSTIMER_TARGET1",
|
||||
[52] = "SYSTIMER_TARGET2",
|
||||
[53] = "APB_ADC",
|
||||
[54] = "DMA_IN_CH0",
|
||||
[55] = "DMA_IN_CH1",
|
||||
[56] = "DMA_OUT_CH0",
|
||||
[57] = "DMA_OUT_CH1",
|
||||
[58] = "GPSPI2",
|
||||
[59] = "SHA",
|
||||
[60] = "ECC",
|
||||
[61] = "ECDSA",
|
||||
};
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
PROVIDE ( UART0 = 0x60000000 );
|
||||
PROVIDE ( UART1 = 0x60001000 );
|
||||
PROVIDE ( SPIMEM0 = 0x60002000 );
|
||||
PROVIDE ( SPIMEM1 = 0x60003000 );
|
||||
PROVIDE ( I2C = 0x60004000 );
|
||||
PROVIDE ( UART2 = 0x60006000 );
|
||||
PROVIDE ( LEDC = 0x60007000 );
|
||||
PROVIDE ( TIMERG0 = 0x60008000 );
|
||||
PROVIDE ( TIMERG1 = 0x60009000 );
|
||||
PROVIDE ( SYSTIMER = 0x6000A000 );
|
||||
PROVIDE ( I2S = 0x6000C000 );
|
||||
PROVIDE ( ADC = 0x6000E000 );
|
||||
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
|
||||
PROVIDE ( INTMTX = 0x60010000 );
|
||||
PROVIDE ( SOC_ETM = 0x60013000 );
|
||||
PROVIDE ( PVT_MONITOR = 0x60019000 );
|
||||
PROVIDE ( PSRAM_MEM_MONITOR = 0x6001A000 );
|
||||
PROVIDE ( GDMA = 0x60080000 );
|
||||
PROVIDE ( GPSPI2 = 0x60081000 );
|
||||
PROVIDE ( SHA = 0x60089000 );
|
||||
PROVIDE ( ECC = 0x6008B000 );
|
||||
PROVIDE ( ECDSA = 0x6008E000 );
|
||||
PROVIDE ( IO_MUX = 0x60090000 );
|
||||
PROVIDE ( GPIO = 0x60091000 );
|
||||
PROVIDE ( TCM_MEM_MONITOR = 0x60092000 );
|
||||
PROVIDE ( PAU = 0x60093000 );
|
||||
PROVIDE ( HP_SYSTEM = 0x60095000 );
|
||||
PROVIDE ( PCR = 0x60096000 );
|
||||
PROVIDE ( TEE = 0x60098000 );
|
||||
PROVIDE ( HP_APM = 0x60099000 );
|
||||
PROVIDE ( MISC = 0x6009F000 );
|
||||
PROVIDE ( MODEM0 = 0x600A0000 );
|
||||
PROVIDE ( MODEM1 = 0x600AC000 );
|
||||
PROVIDE ( MODEM_PWR0 = 0x600AD000 );
|
||||
PROVIDE ( MODEM_PWR1 = 0x600AF000 );
|
||||
PROVIDE ( PMU = 0x600B0000 );
|
||||
PROVIDE ( LP_CLKRST = 0x600B0400 );
|
||||
PROVIDE ( LP_TIMER = 0x600B0C00 );
|
||||
PROVIDE ( LP_AON = 0x600B1000 );
|
||||
PROVIDE ( LP_WDT = 0x600B1C00 );
|
||||
PROVIDE ( LPPERI = 0x600B2800 );
|
||||
PROVIDE ( LP_ANA = 0x600B2C00 );
|
||||
PROVIDE ( LP_TEE = 0x600B3400 );
|
||||
PROVIDE ( LP_APM = 0x600B3800 );
|
||||
PROVIDE ( LP_IO_MUX = 0x600B4000 );
|
||||
PROVIDE ( LP_GPIO = 0x600B4400 );
|
||||
PROVIDE ( EFUSE_AND_OTP_DEBUG0= 0x600B4800 );
|
||||
PROVIDE ( EFUSE_AND_OTP_DEBUG1= 0x600B4C00 );
|
||||
PROVIDE ( TRACE = 0x600C0000 );
|
||||
PROVIDE ( BUS_MONITOR = 0x600C2000 );
|
||||
PROVIDE ( INTPRI_REG = 0x600C5000 );
|
||||
PROVIDE ( CACHE_CFG = 0x600C8000 );
|
||||
Ładowanie…
Reference in New Issue