kopia lustrzana https://github.com/espressif/esp-idf
cpu_start: rename function to add core prefix for more clarity
rodzic
f441ce977a
commit
81e3eb45ca
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@ -137,7 +137,7 @@ static volatile bool s_resume_cores;
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// If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
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// If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
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bool g_spiram_ok = true;
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bool g_spiram_ok = true;
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static void intr_matrix_clear(void)
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static void core_intr_matrix_clear(void)
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{
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{
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uint32_t core_id = cpu_hal_get_core_id();
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uint32_t core_id = cpu_hal_get_core_id();
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@ -180,7 +180,7 @@ void IRAM_ATTR call_start_cpu1(void)
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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// Clear interrupt matrix for APP CPU core
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// Clear interrupt matrix for APP CPU core
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intr_matrix_clear();
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core_intr_matrix_clear();
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//Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
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//Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
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//has started, but it isn't active *on this CPU* yet.
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//has started, but it isn't active *on this CPU* yet.
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@ -528,7 +528,7 @@ void IRAM_ATTR call_start_cpu0(void)
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g_startup_time = esp_rtc_get_time_us();
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g_startup_time = esp_rtc_get_time_us();
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// Clear interrupt matrix for PRO CPU core
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// Clear interrupt matrix for PRO CPU core
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intr_matrix_clear();
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core_intr_matrix_clear();
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#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
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#ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
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#ifdef CONFIG_ESP_CONSOLE_UART
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#ifdef CONFIG_ESP_CONSOLE_UART
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