kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/eth_support_ip101g' into 'master'
support new Ethernet PHY (IP101) See merge request idf/esp-idf!4187pull/3010/head
commit
7fb3218a33
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@ -2,7 +2,8 @@ set(COMPONENT_SRCS "emac_dev.c"
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"emac_main.c"
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"eth_phy/phy_common.c"
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"eth_phy/phy_lan8720.c"
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"eth_phy/phy_tlk110.c")
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"eth_phy/phy_tlk110.c"
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"eth_phy/phy_ip101.c")
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set(COMPONENT_ADD_INCLUDEDIRS "include")
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set(COMPONENT_REQUIRES)
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@ -1,60 +1,55 @@
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menu Ethernet
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config DMA_RX_BUF_NUM
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int "Number of DMA RX buffers"
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range 3 20
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default 10
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help
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Number of DMA receive buffers. Each buffer is 1600 bytes.
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Buffers are allocated statically.
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Larger number of buffers increases throughput.
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If enable flow ctrl, the num must be above 9 .
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config DMA_RX_BUF_NUM
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int "Number of DMA RX buffers"
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range 3 20
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default 10
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help
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Number of DMA receive buffers. Each buffer is 1600 bytes.
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These buffers are allocated dynamically.
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More buffers will increase throughput.
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If flow ctrl is enabled, make sure this number is larger than 9.
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config DMA_TX_BUF_NUM
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int "Number of DMA TX buffers"
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range 3 20
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default 10
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help
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Number of DMA transmit buffers. Each buffer is 1600 bytes.
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Buffers are allocated statically.
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Larger number of buffers increases throughput.
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config DMA_TX_BUF_NUM
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int "Number of DMA TX buffers"
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range 3 20
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default 10
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help
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Number of DMA transmit buffers. Each buffer is 1600 bytes.
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These buffers are allocated dynamically.
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More buffers will increase throughput.
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config EMAC_L2_TO_L3_RX_BUF_MODE
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bool "Enable copy between Layer2 and Layer3"
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default y
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help
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If this options is selected, a copy of each received buffer will be created when
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passing it from the Ethernet MAC (L2) to the IP stack (L3). Otherwise, IP stack
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will receive pointers to the DMA buffers used by Ethernet MAC.
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config EMAC_L2_TO_L3_RX_BUF_MODE
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bool "Enable received buffers be copied to Layer3 from Layer2"
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default y
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help
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If this option is selected, a copy of each received buffer will be allocated from the heap
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before passing it to the IP Layer (L3).
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Which means, the total amount of received buffers is limited by the heap size.
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When Ethernet MAC doesn't have any unused buffers left, it will drop incoming
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packets (flow control may help with this problem, to some extent).
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If this option is not selected, IP layer only uses the pointers to the DMA buffers owned by Ethernet MAC.
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When Ethernet MAC doesn't have any available buffers left, it will drop the incoming packets.
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The buffers for the IP stack are allocated from the heap, so the total number of
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receive buffers is limited by the available heap size, if this option is selected.
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config EMAC_CHECK_LINK_PERIOD_MS
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int "Period (ms) of checking Ethernet linkup status"
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range 1000 5000
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default 2000
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help
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The emac driver uses an internal timer to check the Ethernet linkup status.
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Here you should choose a valid interval time.
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If unsure, choose n.
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config EMAC_TASK_PRIORITY
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int "EMAC_TASK_PRIORITY"
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default 20
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range 3 22
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help
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Priority of Ethernet MAC task.
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config EMAC_CHECK_LINK_PERIOD_MS
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int "Period(ms) of checking Ethernet linkup status"
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range 1000 5000
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default 2000
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help
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The emac driver uses an internal timer to check the ethernet linkup
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status. Here you should choose a valid the interval time.
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config EMAC_TASK_PRIORITY
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int "EMAC_TASK_PRIORITY"
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default 20
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range 3 22
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help
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Ethernet MAC task priority.
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config EMAC_TASK_STACK_SIZE
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int "Stack Size of EMAC Task"
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default 3072
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range 2000 8000
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help
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Stack Size of Ethernet MAC task.
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config EMAC_TASK_STACK_SIZE
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int "Stack Size of EMAC Task"
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default 3072
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range 2000 8000
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help
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Stack Size of Ethernet MAC task.
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endmenu
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@ -15,16 +15,13 @@
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#ifndef _EMAC_COMMON_H_
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#define _EMAC_COMMON_H_
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#include <stdint.h>
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#include "esp_err.h"
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#include "emac_dev.h"
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#include "esp_eth.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "esp_eth.h"
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#include "emac_dev.h"
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typedef uint32_t emac_sig_t;
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typedef uint32_t emac_par_t;
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@ -75,8 +72,8 @@ struct emac_config_data {
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eth_phy_get_duplex_mode_func emac_phy_get_duplex_mode;
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bool emac_flow_ctrl_enable;
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bool emac_flow_ctrl_partner_support;
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eth_phy_get_partner_pause_enable_func emac_phy_get_partner_pause_enable;
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eth_phy_power_enable_func emac_phy_power_enable;
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eth_phy_get_partner_pause_enable_func emac_phy_get_partner_pause_enable;
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eth_phy_power_enable_func emac_phy_power_enable;
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uint32_t reset_timeout_ms;
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};
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@ -107,17 +104,15 @@ struct emac_close_cmd {
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#define DMA_RX_BUF_NUM CONFIG_DMA_RX_BUF_NUM
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#define DMA_TX_BUF_NUM CONFIG_DMA_TX_BUF_NUM
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#define EMAC_TASK_PRIORITY CONFIG_EMAC_TASK_PRIORITY
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#define EMAC_TASK_STACK_SIZE CONFIG_EMAC_TASK_STACK_SIZE
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#define EMAC_TASK_STACK_SIZE CONFIG_EMAC_TASK_STACK_SIZE
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#define DMA_RX_BUF_SIZE 1600
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#define DMA_TX_BUF_SIZE 1600
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//rest buf num
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#define FLOW_CONTROL_HIGH_WATERMARK 3
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//used buf num
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#define FLOW_CONTROL_LOW_WATERMARK 6
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#define FLOW_CONTROL_LOW_WATERMARK 6
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#define PHY_LINK_CHECK_NUM 5
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#define PHY_LINK_CHECK_NUM 5
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#define EMAC_CMD_OK 0
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#define EMAC_CMD_FAIL -1
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@ -15,12 +15,12 @@
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#ifndef _EMAC_DESC_H_
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#define _EMAC_DESC_H_
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc/soc.h"
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#define REG_EMAC_DESC_BASE 0
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#define EMAC_DESC_TDES0_REG (REG_EMAC_DESC_BASE + 0x0000)
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#define EMAC_DESC_TX_OWN (BIT(31))
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@ -15,13 +15,13 @@
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#ifndef _EMAC_DEV_H_
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#define _EMAC_DEV_H_
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#include <stdint.h>
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#include "soc/emac_reg_v2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "esp_types.h"
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#include "soc/emac_reg_v2.h"
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#define EMAC_INTR_ENABLE_BIT (EMAC_DMAIN_TIE | EMAC_DMAIN_RIE | EMAC_DMAIN_RBUE | EMAC_DMAIN_NISE)
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struct dma_desc {
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@ -37,7 +37,7 @@ typedef struct dma_extended_desc {
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uint32_t desc5;
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uint32_t desc6;
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uint32_t desc7;
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}dma_extended_desc_t;
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} dma_extended_desc_t;
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void emac_enable_clk(bool enable);
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esp_err_t emac_reset(void);
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@ -1121,7 +1121,11 @@ esp_err_t esp_eth_init_internal(eth_config_t *config)
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REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_H_DIV_NUM, 0);
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REG_SET_FIELD(EMAC_EX_CLKOUT_CONF_REG, EMAC_EX_CLK_OUT_DIV_NUM, 0);
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if (emac_config.clock_mode == ETH_CLOCK_GPIO16_OUT) {
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if (emac_config.clock_mode == ETH_CLOCK_GPIO0_OUT) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);
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REG_WRITE(PIN_CTRL, 6);
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ESP_LOGD(TAG, "EMAC 50MHz clock output on GPIO0");
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} else if (emac_config.clock_mode == ETH_CLOCK_GPIO16_OUT) {
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO16_U, FUNC_GPIO16_EMAC_CLK_OUT);
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ESP_LOGD(TAG, "EMAC 50MHz clock output on GPIO16");
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} else if (emac_config.clock_mode == ETH_CLOCK_GPIO17_OUT) {
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@ -23,7 +23,6 @@ void phy_rmii_configure_data_interface_pins(void)
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{
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// CRS_DRV to GPIO27
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO27_U, FUNC_GPIO27_EMAC_RX_DV);
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// TXD0 to GPIO19
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO19_U, FUNC_GPIO19_EMAC_TXD0);
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// TX_EN to GPIO21
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@ -71,7 +70,7 @@ bool phy_mii_check_link_status(void)
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bool phy_mii_get_partner_pause_enable(void)
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{
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if((esp_eth_smi_read(MII_PHY_LINK_PARTNER_ABILITY_REG) & MII_PARTNER_PAUSE)) {
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if ((esp_eth_smi_read(MII_PHY_LINK_PARTNER_ABILITY_REG) & MII_PARTNER_PAUSE)) {
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ESP_LOGD(TAG, "phy_mii_get_partner_pause_enable(TRUE)");
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return true;
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} else {
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@ -0,0 +1,116 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
|
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// limitations under the License.
|
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#include "esp_log.h"
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#include "esp_eth.h"
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#include "eth_phy/phy_reg.h"
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#include "eth_phy/phy_ip101.h"
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#define IP101_PHY_ID1 0x243
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#define IP101_PHY_ID2 0xc54
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#define IP101_PHY_ID2_MASK 0xFFF0
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#define PHY_STATUS_REG (0x1e)
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#define DUPLEX_STATUS BIT(2)
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#define SPEED_STATUS BIT(1)
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static const char *TAG = "ip101";
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void phy_ip101_check_phy_init(void)
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{
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phy_ip101_dump_registers();
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esp_eth_smi_wait_set(MII_BASIC_MODE_STATUS_REG, MII_AUTO_NEGOTIATION_COMPLETE, 0);
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}
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eth_speed_mode_t phy_ip101_get_speed_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & SPEED_STATUS) == SPEED_STATUS) {
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ESP_LOGD(TAG, "phy_ip101_get_speed_mode(100)");
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return ETH_SPEED_MODE_100M;
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} else {
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ESP_LOGD(TAG, "phy_ip101_get_speed_mode(10)");
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return ETH_SPEED_MODE_10M;
|
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}
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}
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|
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eth_duplex_mode_t phy_ip101_get_duplex_mode(void)
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{
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if ((esp_eth_smi_read(PHY_STATUS_REG) & DUPLEX_STATUS) == DUPLEX_STATUS) {
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ESP_LOGD(TAG, "phy_ip101_get_duplex_mode(FULL)");
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return ETH_MODE_FULLDUPLEX;
|
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} else {
|
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ESP_LOGD(TAG, "phy_ip101_get_duplex_mode(HALF)");
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return ETH_MODE_HALFDUPLEX;
|
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}
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}
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|
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void phy_ip101_power_enable(bool enable)
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{
|
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if (enable) {
|
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uint32_t data = esp_eth_smi_read(MII_BASIC_MODE_CONTROL_REG);
|
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data |= MII_AUTO_NEGOTIATION_ENABLE | MII_RESTART_AUTO_NEGOTIATION;
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esp_eth_smi_write(MII_BASIC_MODE_CONTROL_REG, data);
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// TODO: only do this if config.flow_ctrl_enable == true
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phy_mii_enable_flow_ctrl();
|
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}
|
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}
|
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|
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esp_err_t phy_ip101_init(void)
|
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{
|
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esp_err_t res1, res2;
|
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ESP_LOGD(TAG, "phy_ip101_init()");
|
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phy_ip101_dump_registers();
|
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do {
|
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// Call esp_eth_smi_wait_value() with a timeout so it prints an error periodically
|
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res1 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_1_REG, IP101_PHY_ID1, UINT16_MAX, 1000);
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res2 = esp_eth_smi_wait_value(MII_PHY_IDENTIFIER_2_REG, IP101_PHY_ID2, IP101_PHY_ID2_MASK, 1000);
|
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} while (res1 != ESP_OK || res2 != ESP_OK);
|
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ets_delay_us(300);
|
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// TODO: only do this if config.flow_ctrl_enable == true
|
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phy_mii_enable_flow_ctrl();
|
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if (res1 == ESP_OK && res2 == ESP_OK) {
|
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return ESP_OK;
|
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} else {
|
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return ESP_ERR_TIMEOUT;
|
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}
|
||||
}
|
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|
||||
const eth_config_t phy_ip101_default_ethernet_config = {
|
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.phy_addr = 0x1,
|
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.mac_mode = ETH_MODE_RMII,
|
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.clock_mode = ETH_CLOCK_GPIO0_OUT,
|
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.flow_ctrl_enable = true,
|
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.phy_init = phy_ip101_init,
|
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.phy_check_init = phy_ip101_check_phy_init,
|
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.phy_check_link = phy_mii_check_link_status,
|
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.phy_get_speed_mode = phy_ip101_get_speed_mode,
|
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.phy_get_duplex_mode = phy_ip101_get_duplex_mode,
|
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.phy_get_partner_pause_enable = phy_mii_get_partner_pause_enable,
|
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.phy_power_enable = phy_ip101_power_enable,
|
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};
|
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|
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void phy_ip101_dump_registers()
|
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{
|
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ESP_LOGD(TAG, "IP101 Registers:");
|
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ESP_LOGD(TAG, "BCR 0x%04x", esp_eth_smi_read(0x0));
|
||||
ESP_LOGD(TAG, "BSR 0x%04x", esp_eth_smi_read(0x1));
|
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ESP_LOGD(TAG, "PHY1 0x%04x", esp_eth_smi_read(0x2));
|
||||
ESP_LOGD(TAG, "PHY2 0x%04x", esp_eth_smi_read(0x3));
|
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ESP_LOGD(TAG, "ANAR 0x%04x", esp_eth_smi_read(0x4));
|
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ESP_LOGD(TAG, "ANLPAR 0x%04x", esp_eth_smi_read(0x5));
|
||||
ESP_LOGD(TAG, "ANER 0x%04x", esp_eth_smi_read(0x6));
|
||||
ESP_LOGD(TAG, "PSCR 0x%04x", esp_eth_smi_read(0x16));
|
||||
ESP_LOGD(TAG, "ISR 0x%04x", esp_eth_smi_read(0x17));
|
||||
ESP_LOGD(TAG, "ICR 0x%04x", esp_eth_smi_read(0x18));
|
||||
ESP_LOGD(TAG, "CSSR 0x%04x", esp_eth_smi_read(0x30));
|
||||
}
|
|
@ -11,31 +11,25 @@
|
|||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_eth.h"
|
||||
|
||||
#include "eth_phy/phy_lan8720.h"
|
||||
#include "eth_phy/phy_reg.h"
|
||||
#include "eth_phy/phy_lan8720.h"
|
||||
|
||||
/* Value of MII_PHY_IDENTIFIER_REGs for Microchip LAN8720
|
||||
* (Except for bottom 4 bits of ID2, used for model revision)
|
||||
*/
|
||||
#define LAN8720_PHY_ID1 0x0007
|
||||
#define LAN8720_PHY_ID2 0xc0f0
|
||||
#define LAN8720_PHY_ID2_MASK 0xFFF0
|
||||
|
||||
/* LAN8720-specific registers */
|
||||
|
||||
#define PHY_SPECIAL_CONTROL_STATUS_REG (0x1f)
|
||||
#define AUTO_NEGOTIATION_DONE BIT(12)
|
||||
#define DUPLEX_INDICATION_FULL BIT(4)
|
||||
#define SPEED_INDICATION_100T BIT(3)
|
||||
#define SPEED_INDICATION_10T BIT(2)
|
||||
#define SPEED_DUPLEX_INDICATION_10T_HALF 0x04
|
||||
#define SPEED_DUPLEX_INDICATION_10T_FULL 0x14
|
||||
#define SPEED_DUPLEX_INDICATION_100T_HALF 0x08
|
||||
#define SPEED_DUPLEX_INDICATION_100T_FULL 0x18
|
||||
#define PHY_SPECIAL_CONTROL_STATUS_REG (0x1f)
|
||||
#define AUTO_NEGOTIATION_DONE BIT(12)
|
||||
#define DUPLEX_INDICATION_FULL BIT(4)
|
||||
#define SPEED_INDICATION_100T BIT(3)
|
||||
#define SPEED_INDICATION_10T BIT(2)
|
||||
#define SPEED_DUPLEX_INDICATION_10T_HALF 0x04
|
||||
#define SPEED_DUPLEX_INDICATION_10T_FULL 0x14
|
||||
#define SPEED_DUPLEX_INDICATION_100T_HALF 0x08
|
||||
#define SPEED_DUPLEX_INDICATION_100T_FULL 0x18
|
||||
|
||||
static const char *TAG = "lan8720";
|
||||
|
||||
|
@ -109,13 +103,9 @@ esp_err_t phy_lan8720_init(void)
|
|||
}
|
||||
|
||||
const eth_config_t phy_lan8720_default_ethernet_config = {
|
||||
// By default, the PHY address is 0 or 1 based on PHYAD0
|
||||
// pin. Can also be overriden in software. See datasheet
|
||||
// for defaults.
|
||||
.phy_addr = 0,
|
||||
.mac_mode = ETH_MODE_RMII,
|
||||
.clock_mode = ETH_CLOCK_GPIO0_IN,
|
||||
//Only FULLDUPLEX mode support flow ctrl now!
|
||||
.flow_ctrl_enable = true,
|
||||
.phy_init = phy_lan8720_init,
|
||||
.phy_check_init = phy_lan8720_check_phy_init,
|
||||
|
|
|
@ -11,45 +11,37 @@
|
|||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#include "esp_attr.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_eth.h"
|
||||
|
||||
#include "eth_phy/phy_tlk110.h"
|
||||
#include "eth_phy/phy_reg.h"
|
||||
#include "eth_phy/phy_tlk110.h"
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
/* Value of MII_PHY_IDENTIFIER_REG for TI TLK110,
|
||||
Excluding bottom 4 bytes of ID2, used for model revision
|
||||
*/
|
||||
#define TLK110_PHY_ID1 0x2000
|
||||
#define TLK110_PHY_ID2 0xa210
|
||||
#define TLK110_PHY_ID2_MASK 0xFFF0
|
||||
|
||||
/* TLK110-specific registers */
|
||||
#define SW_STRAP_CONTROL_REG (0x9)
|
||||
#define SW_STRAP_CONFIG_DONE BIT(15)
|
||||
#define AUTO_MDIX_ENABLE BIT(14)
|
||||
#define AUTO_NEGOTIATION_ENABLE BIT(13)
|
||||
#define AN_1 BIT(12)
|
||||
#define AN_0 BIT(11)
|
||||
#define LED_CFG BIT(10)
|
||||
#define RMII_ENHANCED_MODE BIT(9)
|
||||
#define SW_STRAP_CONTROL_REG (0x9)
|
||||
#define SW_STRAP_CONFIG_DONE BIT(15)
|
||||
#define AUTO_MDIX_ENABLE BIT(14)
|
||||
#define AUTO_NEGOTIATION_ENABLE BIT(13)
|
||||
#define AN_1 BIT(12)
|
||||
#define AN_0 BIT(11)
|
||||
#define LED_CFG BIT(10)
|
||||
#define RMII_ENHANCED_MODE BIT(9)
|
||||
|
||||
#define DEFAULT_STRAP_CONFIG (AUTO_MDIX_ENABLE|AUTO_NEGOTIATION_ENABLE|AN_1|AN_0|LED_CFG)
|
||||
#define DEFAULT_STRAP_CONFIG (AUTO_MDIX_ENABLE | AUTO_NEGOTIATION_ENABLE | AN_1 | AN_0 | LED_CFG)
|
||||
|
||||
#define PHY_STATUS_REG (0x10)
|
||||
#define AUTO_NEGOTIATION_STATUS BIT(4)
|
||||
#define DUPLEX_STATUS BIT(2)
|
||||
#define SPEED_STATUS BIT(1)
|
||||
#define PHY_STATUS_REG (0x10)
|
||||
#define AUTO_NEGOTIATION_STATUS BIT(4)
|
||||
#define DUPLEX_STATUS BIT(2)
|
||||
#define SPEED_STATUS BIT(1)
|
||||
|
||||
#define CABLE_DIAGNOSTIC_CONTROL_REG (0x1e)
|
||||
#define DIAGNOSTIC_DONE BIT(1)
|
||||
#define CABLE_DIAGNOSTIC_CONTROL_REG (0x1e)
|
||||
#define DIAGNOSTIC_DONE BIT(1)
|
||||
|
||||
#define PHY_RESET_CONTROL_REG (0x1f)
|
||||
#define SOFTWARE_RESET BIT(15)
|
||||
#define PHY_RESET_CONTROL_REG (0x1f)
|
||||
#define SOFTWARE_RESET BIT(15)
|
||||
|
||||
static const char *TAG = "tlk110";
|
||||
|
||||
|
@ -64,7 +56,7 @@ void phy_tlk110_check_phy_init(void)
|
|||
|
||||
eth_speed_mode_t phy_tlk110_get_speed_mode(void)
|
||||
{
|
||||
if ((esp_eth_smi_read(PHY_STATUS_REG) & SPEED_STATUS ) != SPEED_STATUS) {
|
||||
if ((esp_eth_smi_read(PHY_STATUS_REG) & SPEED_STATUS) != SPEED_STATUS) {
|
||||
ESP_LOGD(TAG, "phy_tlk110_get_speed_mode(100)");
|
||||
return ETH_SPEED_MODE_100M;
|
||||
} else {
|
||||
|
@ -75,7 +67,7 @@ eth_speed_mode_t phy_tlk110_get_speed_mode(void)
|
|||
|
||||
eth_duplex_mode_t phy_tlk110_get_duplex_mode(void)
|
||||
{
|
||||
if ((esp_eth_smi_read(PHY_STATUS_REG) & DUPLEX_STATUS ) == DUPLEX_STATUS) {
|
||||
if ((esp_eth_smi_read(PHY_STATUS_REG) & DUPLEX_STATUS) == DUPLEX_STATUS) {
|
||||
ESP_LOGD(TAG, "phy_tlk110_get_duplex_mode(FULL)");
|
||||
return ETH_MODE_FULLDUPLEX;
|
||||
} else {
|
||||
|
@ -122,12 +114,9 @@ esp_err_t phy_tlk110_init(void)
|
|||
}
|
||||
|
||||
const eth_config_t phy_tlk110_default_ethernet_config = {
|
||||
// PHY address configured by PHYADx pins. Default value of 0x1
|
||||
// is used if all pins are unconnected.
|
||||
.phy_addr = 0x1,
|
||||
.mac_mode = ETH_MODE_RMII,
|
||||
.clock_mode = ETH_CLOCK_GPIO0_IN,
|
||||
//Only FULLDUPLEX mode support flow ctrl now!
|
||||
.flow_ctrl_enable = true,
|
||||
.phy_init = phy_tlk110_init,
|
||||
.phy_check_init = phy_tlk110_check_phy_init,
|
||||
|
|
|
@ -15,68 +15,88 @@
|
|||
#ifndef __ESP_ETH_H__
|
||||
#define __ESP_ETH_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "esp_err.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "esp_types.h"
|
||||
#include "esp_err.h"
|
||||
|
||||
/**
|
||||
* @brief Ethernet interface mode
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_MODE_RMII = 0,
|
||||
ETH_MODE_MII,
|
||||
ETH_MODE_RMII = 0, /*!< RMII mode */
|
||||
ETH_MODE_MII, /*!< MII mode */
|
||||
} eth_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet clock mode
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_CLOCK_GPIO0_IN = 0,
|
||||
ETH_CLOCK_GPIO16_OUT = 2,
|
||||
ETH_CLOCK_GPIO17_OUT = 3
|
||||
ETH_CLOCK_GPIO0_IN = 0, /*!< RMII clock input to GPIO0 */
|
||||
ETH_CLOCK_GPIO0_OUT = 1, /*!< RMII clock output from GPIO0 */
|
||||
ETH_CLOCK_GPIO16_OUT = 2, /*!< RMII clock output from GPIO16 */
|
||||
ETH_CLOCK_GPIO17_OUT = 3 /*!< RMII clock output from GPIO17 */
|
||||
} eth_clock_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet Speed
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_SPEED_MODE_10M = 0,
|
||||
ETH_SPEED_MODE_100M,
|
||||
ETH_SPEED_MODE_10M = 0, /*!< Ethernet speed: 10Mbps */
|
||||
ETH_SPEED_MODE_100M, /*!< Ethernet speed: 100Mbps */
|
||||
} eth_speed_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet Duplex
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
ETH_MODE_HALFDUPLEX = 0,
|
||||
ETH_MODE_FULLDUPLEX,
|
||||
ETH_MODE_HALFDUPLEX = 0, /*!< Ethernet half duplex */
|
||||
ETH_MODE_FULLDUPLEX, /*!< Ethernet full duplex */
|
||||
} eth_duplex_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Ethernet PHY address
|
||||
*
|
||||
*/
|
||||
typedef enum {
|
||||
PHY0 = 0,
|
||||
PHY1,
|
||||
PHY2,
|
||||
PHY3,
|
||||
PHY4,
|
||||
PHY5,
|
||||
PHY6,
|
||||
PHY7,
|
||||
PHY8,
|
||||
PHY9,
|
||||
PHY10,
|
||||
PHY11,
|
||||
PHY12,
|
||||
PHY13,
|
||||
PHY14,
|
||||
PHY15,
|
||||
PHY16,
|
||||
PHY17,
|
||||
PHY18,
|
||||
PHY19,
|
||||
PHY20,
|
||||
PHY21,
|
||||
PHY22,
|
||||
PHY23,
|
||||
PHY24,
|
||||
PHY25,
|
||||
PHY26,
|
||||
PHY27,
|
||||
PHY28,
|
||||
PHY29,
|
||||
PHY30,
|
||||
PHY31,
|
||||
PHY0 = 0, /*!< PHY address 0 */
|
||||
PHY1, /*!< PHY address 1 */
|
||||
PHY2, /*!< PHY address 2 */
|
||||
PHY3, /*!< PHY address 3 */
|
||||
PHY4, /*!< PHY address 4 */
|
||||
PHY5, /*!< PHY address 5 */
|
||||
PHY6, /*!< PHY address 6 */
|
||||
PHY7, /*!< PHY address 7 */
|
||||
PHY8, /*!< PHY address 8 */
|
||||
PHY9, /*!< PHY address 9 */
|
||||
PHY10, /*!< PHY address 10 */
|
||||
PHY11, /*!< PHY address 11 */
|
||||
PHY12, /*!< PHY address 12 */
|
||||
PHY13, /*!< PHY address 13 */
|
||||
PHY14, /*!< PHY address 14 */
|
||||
PHY15, /*!< PHY address 15 */
|
||||
PHY16, /*!< PHY address 16 */
|
||||
PHY17, /*!< PHY address 17 */
|
||||
PHY18, /*!< PHY address 18 */
|
||||
PHY19, /*!< PHY address 19 */
|
||||
PHY20, /*!< PHY address 20 */
|
||||
PHY21, /*!< PHY address 21 */
|
||||
PHY22, /*!< PHY address 22 */
|
||||
PHY23, /*!< PHY address 23 */
|
||||
PHY24, /*!< PHY address 24 */
|
||||
PHY25, /*!< PHY address 25 */
|
||||
PHY26, /*!< PHY address 26 */
|
||||
PHY27, /*!< PHY address 27 */
|
||||
PHY28, /*!< PHY address 28 */
|
||||
PHY29, /*!< PHY address 29 */
|
||||
PHY30, /*!< PHY address 30 */
|
||||
PHY31 /*!< PHY address 31 */
|
||||
} eth_phy_base_t;
|
||||
|
||||
typedef bool (*eth_phy_check_link_func)(void);
|
||||
|
@ -94,15 +114,15 @@ typedef void (*eth_phy_power_enable_func)(bool enable);
|
|||
*
|
||||
*/
|
||||
typedef struct {
|
||||
eth_phy_base_t phy_addr; /*!< phy base addr (0~31) */
|
||||
eth_mode_t mac_mode; /*!< mac mode only support RMII now */
|
||||
eth_clock_mode_t clock_mode; /*!< external/internal clock mode selecton */
|
||||
eth_tcpip_input_func tcpip_input; /*!< tcpip input func */
|
||||
eth_phy_func phy_init; /*!< phy init func */
|
||||
eth_phy_check_link_func phy_check_link; /*!< phy check link func */
|
||||
eth_phy_check_init_func phy_check_init; /*!< phy check init func */
|
||||
eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */
|
||||
eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */
|
||||
eth_phy_base_t phy_addr; /*!< PHY address (0~31) */
|
||||
eth_mode_t mac_mode; /*!< MAC mode: only support RMII now */
|
||||
eth_clock_mode_t clock_mode; /*!< external/internal clock mode selection */
|
||||
eth_tcpip_input_func tcpip_input; /*!< tcpip input func */
|
||||
eth_phy_func phy_init; /*!< phy init func */
|
||||
eth_phy_check_link_func phy_check_link; /*!< phy check link func */
|
||||
eth_phy_check_init_func phy_check_init; /*!< phy check init func */
|
||||
eth_phy_get_speed_mode_func phy_get_speed_mode; /*!< phy check init func */
|
||||
eth_phy_get_duplex_mode_func phy_get_duplex_mode; /*!< phy check init func */
|
||||
eth_gpio_config_func gpio_config; /*!< gpio config func */
|
||||
bool flow_ctrl_enable; /*!< flag of flow ctrl enable */
|
||||
eth_phy_get_partner_pause_enable_func phy_get_partner_pause_enable; /*!< get partner pause enable */
|
||||
|
|
|
@ -20,38 +20,55 @@ extern "C" {
|
|||
|
||||
#include "esp_eth.h"
|
||||
|
||||
/** Common PHY-management functions.
|
||||
/**
|
||||
* @brief Common PHY-management functions.
|
||||
*
|
||||
* @note These are not enough to drive any particular Ethernet PHY.
|
||||
* They provide a common configuration structure and management functions.
|
||||
*
|
||||
*/
|
||||
|
||||
These are not enough to drive any particular Ethernet PHY, but they provide a common configuration structure and
|
||||
management functions.
|
||||
*/
|
||||
|
||||
/** Configure fixed pins for RMII data interface.
|
||||
|
||||
This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII
|
||||
data interface. These pins cannot be changed, and must be wired to
|
||||
ethernet functions.
|
||||
|
||||
This is not sufficient to fully configure the Ethernet PHY,
|
||||
MDIO configuration interface pins (such as SMI MDC, MDO, MDI)
|
||||
must also be configured correctly in the GPIO matrix.
|
||||
*/
|
||||
/**
|
||||
* @brief Configure fixed pins for RMII data interface.
|
||||
*
|
||||
* @note This configures GPIOs 0, 19, 22, 25, 26, 27 for use with RMII data interface.
|
||||
* These pins cannot be changed, and must be wired to ethernet functions.
|
||||
* This is not sufficient to fully configure the Ethernet PHY.
|
||||
* MDIO configuration interface pins (such as SMI MDC, MDO, MDI) must also be configured correctly in the GPIO matrix.
|
||||
*
|
||||
*/
|
||||
void phy_rmii_configure_data_interface_pins(void);
|
||||
|
||||
/** Configure variable pins for SMI (MDIO) ethernet functions.
|
||||
|
||||
Calling this function along with mii_configure_default_pins() will
|
||||
fully configure the GPIOs for the ethernet PHY.
|
||||
/**
|
||||
* @brief Configure variable pins for SMI ethernet functions.
|
||||
*
|
||||
* @param mdc_gpio MDC GPIO Pin number
|
||||
* @param mdio_gpio MDIO GPIO Pin number
|
||||
*
|
||||
* @note Calling this function along with mii_configure_default_pins() will fully configure the GPIOs for the ethernet PHY.
|
||||
*/
|
||||
void phy_rmii_smi_configure_pins(uint8_t mdc_gpio, uint8_t mdio_gpio);
|
||||
|
||||
|
||||
/** Enable flow control in standard PHY MII register.
|
||||
/**
|
||||
* @brief Enable flow control in standard PHY MII register.
|
||||
*
|
||||
*/
|
||||
void phy_mii_enable_flow_ctrl(void);
|
||||
|
||||
/**
|
||||
* @brief Check Ethernet link status via MII interface
|
||||
*
|
||||
* @return true Link is on
|
||||
* @return false Link is off
|
||||
*/
|
||||
bool phy_mii_check_link_status(void);
|
||||
|
||||
/**
|
||||
* @brief Check pause frame ability of partner via MII interface
|
||||
*
|
||||
* @return true Partner is able to process pause frame
|
||||
* @return false Partner can not process pause frame
|
||||
*/
|
||||
bool phy_mii_get_partner_pause_enable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
@ -0,0 +1,75 @@
|
|||
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "phy.h"
|
||||
|
||||
/**
|
||||
* @brief Dump IP101 PHY SMI configuration registers
|
||||
*
|
||||
*/
|
||||
void phy_ip101_dump_registers();
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_ip101_check_phy_init(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_ip101_get_speed_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_ip101_get_duplex_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_power_enable function
|
||||
*
|
||||
*/
|
||||
void phy_ip101_power_enable(bool);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_ip101_init(void);
|
||||
|
||||
/**
|
||||
* @brief Default IP101 PHY configuration
|
||||
*
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
*/
|
||||
extern const eth_config_t phy_ip101_default_ethernet_config;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -20,45 +20,53 @@ extern "C" {
|
|||
|
||||
#include "phy.h"
|
||||
|
||||
|
||||
/** @brief Dump all LAN8720 PHY SMI configuration registers
|
||||
/**
|
||||
* @brief Dump LAN8720 PHY SMI configuration registers
|
||||
*
|
||||
* @note These registers are dumped at 'debug' level, so output
|
||||
* may not be visible depending on default log levels.
|
||||
*/
|
||||
void phy_lan8720_dump_registers();
|
||||
|
||||
/** @brief Default LAN8720 phy_check_init function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_lan8720_check_phy_init(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_get_speed_mode function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_lan8720_get_speed_mode(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_get_duplex_mode function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_lan8720_get_duplex_mode(void);
|
||||
|
||||
/** @brief Default LAN8720 phy_power_enable function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_power_enable function
|
||||
*
|
||||
* @note This function may need to be replaced with a custom function
|
||||
* if the PHY has a GPIO to enable power or start a clock.
|
||||
*
|
||||
* Consult the ethernet example to see how this is done.
|
||||
*/
|
||||
void phy_lan8720_power_enable(bool);
|
||||
|
||||
/** @brief Default LAN8720 phy_init function.
|
||||
/**
|
||||
* @brief Default LAN8720 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_lan8720_init(void);
|
||||
|
||||
/** @brief Default LAN8720 PHY configuration
|
||||
/**
|
||||
* @brief Default LAN8720 PHY configuration
|
||||
*
|
||||
* This configuration is not suitable for use as-is, it will need
|
||||
* to be modified for your particular PHY hardware setup.
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
* Consult the Ethernet example to see how this is done.
|
||||
*/
|
||||
extern const eth_config_t phy_lan8720_default_ethernet_config;
|
||||
|
||||
|
|
|
@ -18,9 +18,10 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* This header contains register/bit masks for the standard
|
||||
PHY MII registers that should be supported by all PHY models.
|
||||
*/
|
||||
/**
|
||||
* @brief This header contains register/bit masks for the standard PHY MII registers that should be supported by all PHY models.
|
||||
*
|
||||
*/
|
||||
|
||||
#define MII_BASIC_MODE_CONTROL_REG (0x0)
|
||||
#define MII_SOFTWARE_RESET BIT(15)
|
||||
|
|
|
@ -20,44 +20,53 @@ extern "C" {
|
|||
|
||||
#include "phy.h"
|
||||
|
||||
/** @brief Dump all TLK110 PHY SMI configuration registers
|
||||
/**
|
||||
* @brief Dump TLK110 PHY SMI configuration registers
|
||||
*
|
||||
* @note These registers are dumped at 'debug' level, so output
|
||||
* may not be visible depending on default log levels.
|
||||
*/
|
||||
void phy_tlk110_dump_registers();
|
||||
|
||||
/** @brief Default TLK110 phy_check_init function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_check_init function
|
||||
*
|
||||
*/
|
||||
void phy_tlk110_check_phy_init(void);
|
||||
|
||||
/** @brief Default TLK110 phy_get_speed_mode function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_get_speed_mode function
|
||||
*
|
||||
* @return eth_speed_mode_t Ethernet speed mode
|
||||
*/
|
||||
eth_speed_mode_t phy_tlk110_get_speed_mode(void);
|
||||
|
||||
/** @brief Default TLK110 phy_get_duplex_mode function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_get_duplex_mode function
|
||||
*
|
||||
* @return eth_duplex_mode_t Ethernet duplex mode
|
||||
*/
|
||||
eth_duplex_mode_t phy_tlk110_get_duplex_mode(void);
|
||||
|
||||
/** @brief Default TLK110 phy_power_enable function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_power_enable function
|
||||
*
|
||||
* @note This function may need to be replaced with a custom function
|
||||
* if the PHY has a GPIO to enable power or start a clock.
|
||||
*
|
||||
* Consult the ethernet example to see how this is done.
|
||||
*/
|
||||
void phy_tlk110_power_enable(bool);
|
||||
|
||||
/** @brief Default TLK110 phy_init function.
|
||||
/**
|
||||
* @brief Default TLK110 phy_init function
|
||||
*
|
||||
* @return esp_err_t
|
||||
* - ESP_OK on success
|
||||
* - ESP_FAIL on error
|
||||
*/
|
||||
esp_err_t phy_tlk110_init(void);
|
||||
|
||||
/** @brief Default TLK110 PHY configuration
|
||||
/**
|
||||
* @brief Default TLK110 PHY configuration
|
||||
*
|
||||
* This configuration is not suitable for use as-is, it will need
|
||||
* to be modified for your particular PHY hardware setup.
|
||||
* @note This configuration is not suitable for use as-is,
|
||||
* it will need to be modified for your particular PHY hardware setup.
|
||||
*
|
||||
* Consult the Ethernet example to see how this is done.
|
||||
*/
|
||||
extern const eth_config_t phy_tlk110_default_ethernet_config;
|
||||
|
||||
|
|
|
@ -60,6 +60,7 @@ INPUT = \
|
|||
../../components/ethernet/include/eth_phy/phy.h \
|
||||
../../components/ethernet/include/eth_phy/phy_tlk110.h \
|
||||
../../components/ethernet/include/eth_phy/phy_lan8720.h \
|
||||
../../components/ethernet/include/eth_phy/phy_ip101.h \
|
||||
##
|
||||
## Peripherals - API Reference
|
||||
##
|
||||
|
|
|
@ -4,7 +4,8 @@ Ethernet
|
|||
Application Example
|
||||
-------------------
|
||||
|
||||
Ethernet example: :example:`ethernet/ethernet`.
|
||||
- Ethernet basic example: :example:`ethernet/ethernet`.
|
||||
- Ethernet iperf example: :example:`ethernet/iperf`.
|
||||
|
||||
PHY Interfaces
|
||||
--------------
|
||||
|
@ -16,12 +17,14 @@ Headers include a default configuration structure. These default configurations
|
|||
* :component_file:`ethernet/include/eth_phy/phy.h` (common)
|
||||
* :component_file:`ethernet/include/eth_phy/phy_tlk110.h`
|
||||
* :component_file:`ethernet/include/eth_phy/phy_lan8720.h`
|
||||
* :component_file:`ethernet/include/eth_phy/phy_ip101.h`
|
||||
|
||||
PHY Configuration Constants
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
.. doxygenvariable:: phy_tlk110_default_ethernet_config
|
||||
.. doxygenvariable:: phy_lan8720_default_ethernet_config
|
||||
.. doxygenvariable:: phy_ip101_default_ethernet_config
|
||||
|
||||
|
||||
API Reference - Ethernet
|
||||
|
@ -44,4 +47,8 @@ API Reference - PHY LAN8720
|
|||
|
||||
.. include:: /_build/inc/phy_lan8720.inc
|
||||
|
||||
API Reference - PHY IP101
|
||||
-------------------------
|
||||
|
||||
.. include:: /_build/inc/phy_ip101.inc
|
||||
|
||||
|
|
|
@ -1,92 +1,94 @@
|
|||
menu "Example Configuration"
|
||||
|
||||
choice PHY_MODEL
|
||||
prompt "Ethernet PHY"
|
||||
default CONFIG_PHY_TLK110
|
||||
help
|
||||
Select the PHY driver to use for the example.
|
||||
choice PHY_MODEL
|
||||
prompt "Ethernet PHY Device"
|
||||
default PHY_TLK110
|
||||
help
|
||||
Select the PHY driver to use for the example.
|
||||
config PHY_IP101
|
||||
bool "IP101"
|
||||
help
|
||||
IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver.
|
||||
Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it.
|
||||
config PHY_TLK110
|
||||
bool "TLK110"
|
||||
help
|
||||
TLK110 is an Industrial 10/100Mbps Ethernet Physical Layer Transceiver.
|
||||
Goto http://www.ti.com/product/TLK110 for information about it.
|
||||
config PHY_LAN8720
|
||||
bool "LAN8720"
|
||||
help
|
||||
LAN8720 is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support.
|
||||
Goto https://www.microchip.com/LAN8720A for more information about it.
|
||||
endchoice
|
||||
|
||||
config PHY_TLK110
|
||||
bool "TI TLK110 PHY"
|
||||
help
|
||||
Select this to use the TI TLK110 PHY
|
||||
config PHY_ADDRESS
|
||||
int "Ethernet PHY Address"
|
||||
default 31
|
||||
range 0 31
|
||||
help
|
||||
PHY Address of your PHY device. It dependens on your schematic design.
|
||||
|
||||
config PHY_LAN8720
|
||||
bool "Microchip LAN8720 PHY"
|
||||
help
|
||||
Select this to use the Microchip LAN8720 PHY
|
||||
choice PHY_CLOCK_MODE
|
||||
prompt "Ethernet PHY Clock Mode"
|
||||
default PHY_CLOCK_GPIO0_IN
|
||||
help
|
||||
Select external (input on GPIO0) or internal (output on GPIO0, GPIO16 or GPIO17) RMII clock.
|
||||
config PHY_CLOCK_GPIO0_IN
|
||||
bool "GPIO0 Input"
|
||||
help
|
||||
Input of 50MHz RMII clock on GPIO0.
|
||||
config PHY_CLOCK_GPIO0_OUT
|
||||
bool "GPIO0 Output"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO0.
|
||||
config PHY_CLOCK_GPIO16_OUT
|
||||
bool "GPIO16 Output"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO16.
|
||||
config PHY_CLOCK_GPIO17_OUT
|
||||
bool "GPIO17 Output (inverted)"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO17 (inverted signal).
|
||||
endchoice
|
||||
|
||||
endchoice
|
||||
config PHY_CLOCK_MODE
|
||||
int
|
||||
default 0 if PHY_CLOCK_GPIO0_IN
|
||||
default 1 if PHY_CLOCK_GPIO0_OUT
|
||||
default 2 if PHY_CLOCK_GPIO16_OUT
|
||||
default 3 if PHY_CLOCK_GPIO17_OUT
|
||||
|
||||
config PHY_USE_POWER_PIN
|
||||
bool "Use PHY Power (enable / disable) pin"
|
||||
default n
|
||||
help
|
||||
Use a GPIO "power pin" to power the PHY on/off during operation.
|
||||
When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
|
||||
So we need another GPIO to control the switch on / off of the RMII clock.
|
||||
|
||||
config PHY_ADDRESS
|
||||
int "PHY Address (0-31)"
|
||||
default 31
|
||||
range 0 31
|
||||
help
|
||||
Select the PHY Address (0-31) for the hardware configuration and PHY model.
|
||||
TLK110 default 31
|
||||
LAN8720 default 1 or 0
|
||||
if PHY_USE_POWER_PIN
|
||||
config PHY_POWER_PIN
|
||||
int "PHY Power GPIO"
|
||||
default 17
|
||||
range 0 33
|
||||
depends on PHY_USE_POWER_PIN
|
||||
help
|
||||
GPIO number to use for powering on/off the PHY.
|
||||
endif
|
||||
|
||||
config PHY_SMI_MDC_PIN
|
||||
int "SMI MDC Pin Number"
|
||||
default 23
|
||||
range 0 33
|
||||
help
|
||||
GPIO number used for SMI clock signal.
|
||||
|
||||
choice PHY_CLOCK_MODE
|
||||
prompt "EMAC clock mode"
|
||||
default PHY_CLOCK_GPIO0_IN
|
||||
help
|
||||
Select external (input on GPIO0) or internal (output on GPIO16 or GPIO17) clock
|
||||
|
||||
|
||||
config PHY_CLOCK_GPIO0_IN
|
||||
bool "GPIO0 input"
|
||||
help
|
||||
Input of 50MHz refclock on GPIO0
|
||||
|
||||
config PHY_CLOCK_GPIO16_OUT
|
||||
bool "GPIO16 output"
|
||||
help
|
||||
Output the internal 50MHz APLL clock on GPIO16
|
||||
|
||||
config PHY_CLOCK_GPIO17_OUT
|
||||
bool "GPIO17 output (inverted)"
|
||||
help
|
||||
Output the internal 50MHz APLL clock on GPIO17 (inverted signal)
|
||||
|
||||
endchoice
|
||||
|
||||
config PHY_CLOCK_MODE
|
||||
int
|
||||
default 0 if PHY_CLOCK_GPIO0_IN
|
||||
default 2 if PHY_CLOCK_GPIO16_OUT
|
||||
default 3 if PHY_CLOCK_GPIO17_OUT
|
||||
|
||||
|
||||
config PHY_USE_POWER_PIN
|
||||
bool "Use PHY Power (enable/disable) pin"
|
||||
default y
|
||||
help
|
||||
Use a GPIO "power pin" to power the PHY on/off during operation.
|
||||
Consult the example README for more details
|
||||
|
||||
config PHY_POWER_PIN
|
||||
int "PHY Power GPIO"
|
||||
default 17
|
||||
range 0 33
|
||||
depends on PHY_USE_POWER_PIN
|
||||
help
|
||||
GPIO number to use for powering on/off the PHY.
|
||||
|
||||
config PHY_SMI_MDC_PIN
|
||||
int "SMI MDC Pin"
|
||||
default 23
|
||||
range 0 33
|
||||
help
|
||||
GPIO number to use for SMI clock output MDC to PHY.
|
||||
|
||||
config PHY_SMI_MDIO_PIN
|
||||
int "SMI MDIO Pin"
|
||||
default 18
|
||||
range 0 33
|
||||
help
|
||||
GPIO number to use for SMI data pin MDIO to/from PHY.
|
||||
config PHY_SMI_MDIO_PIN
|
||||
int "SMI MDIO Pin Number"
|
||||
default 18
|
||||
range 0 33
|
||||
help
|
||||
GPIO number used for SMI data signal.
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -8,30 +8,27 @@
|
|||
*/
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
|
||||
#include "esp_system.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_event_loop.h"
|
||||
#include "esp_event.h"
|
||||
#include "esp_log.h"
|
||||
#include "esp_eth.h"
|
||||
|
||||
#include "rom/gpio.h"
|
||||
|
||||
#include "tcpip_adapter.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/periph_ctrl.h"
|
||||
|
||||
#ifdef CONFIG_PHY_LAN8720
|
||||
#if CONFIG_PHY_LAN8720
|
||||
#include "eth_phy/phy_lan8720.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_lan8720_default_ethernet_config
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_TLK110
|
||||
#elif CONFIG_PHY_TLK110
|
||||
#include "eth_phy/phy_tlk110.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_tlk110_default_ethernet_config
|
||||
#elif CONFIG_PHY_IP101
|
||||
#include "eth_phy/phy_ip101.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_ip101_default_ethernet_config
|
||||
#endif
|
||||
|
||||
static const char *TAG = "eth_example";
|
||||
|
|
|
@ -1,91 +1,106 @@
|
|||
menu "Example Configuration"
|
||||
|
||||
config STORE_HISTORY
|
||||
bool "Store command history in flash"
|
||||
default y
|
||||
help
|
||||
Linenoise line editing library provides functions to save and load
|
||||
command history. If this option is enabled, initalizes a FAT filesystem
|
||||
and uses it to store command history.
|
||||
config STORE_HISTORY
|
||||
bool "Store command history in flash"
|
||||
default y
|
||||
help
|
||||
Linenoise line editing library provides functions to save and load
|
||||
command history. If this option is enabled, initalizes a FAT filesystem
|
||||
and uses it to store command history.
|
||||
|
||||
menu "Etherent PHY Device"
|
||||
choice PHY_MODEL
|
||||
prompt "Ethernet PHY"
|
||||
default CONFIG_PHY_TLK110
|
||||
help
|
||||
Select the PHY driver to use for the example.
|
||||
config PHY_TLK110
|
||||
bool "TI TLK110 PHY"
|
||||
help
|
||||
Select this to use the TI TLK110 PHY
|
||||
config PHY_LAN8720
|
||||
bool "Microchip LAN8720 PHY"
|
||||
help
|
||||
Select this to use the Microchip LAN8720 PHY
|
||||
endchoice
|
||||
menu "Etherent PHY Device"
|
||||
choice PHY_MODEL
|
||||
prompt "Ethernet PHY Device"
|
||||
default PHY_TLK110
|
||||
help
|
||||
Select the PHY driver to use for the example.
|
||||
config PHY_IP101
|
||||
bool "IP101"
|
||||
help
|
||||
IP101 is a single port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver.
|
||||
Goto http://www.icplus.com.tw/pp-IP101G.html for more information about it.
|
||||
config PHY_TLK110
|
||||
bool "TLK110"
|
||||
help
|
||||
TLK110 is an Industrial 10/100Mbps Ethernet Physical Layer Transceiver.
|
||||
Goto http://www.ti.com/product/TLK110 for information about it.
|
||||
config PHY_LAN8720
|
||||
bool "LAN8720"
|
||||
help
|
||||
LAN8720 is a small footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support.
|
||||
Goto https://www.microchip.com/LAN8720A for more information about it.
|
||||
endchoice
|
||||
|
||||
config PHY_ADDRESS
|
||||
int "PHY Address (0-31)"
|
||||
default 31
|
||||
range 0 31
|
||||
help
|
||||
Set the PHY Address (0-31) for the hardware configuration.
|
||||
config PHY_ADDRESS
|
||||
int "Ethernet PHY Address"
|
||||
default 31
|
||||
range 0 31
|
||||
help
|
||||
PHY Address of your PHY device. It dependens on your schematic design.
|
||||
|
||||
choice PHY_CLOCK_MODE
|
||||
prompt "EMAC clock mode"
|
||||
default PHY_CLOCK_GPIO0_IN
|
||||
help
|
||||
Select external (input on GPIO0) or internal (output on GPIO16 or GPIO17) clock
|
||||
config PHY_CLOCK_GPIO0_IN
|
||||
bool "GPIO0 input"
|
||||
help
|
||||
Input of 50MHz refclock on GPIO0
|
||||
config PHY_CLOCK_GPIO16_OUT
|
||||
bool "GPIO16 output"
|
||||
help
|
||||
Output the internal 50MHz APLL clock on GPIO16
|
||||
config PHY_CLOCK_GPIO17_OUT
|
||||
bool "GPIO17 output (inverted)"
|
||||
help
|
||||
Output the internal 50MHz APLL clock on GPIO17 (inverted signal)
|
||||
endchoice
|
||||
choice PHY_CLOCK_MODE
|
||||
prompt "Ethernet PHY Clock Mode"
|
||||
default PHY_CLOCK_GPIO0_IN
|
||||
help
|
||||
Select external (input on GPIO0) or internal (output on GPIO0, GPIO16 or GPIO17) RMII clock.
|
||||
config PHY_CLOCK_GPIO0_IN
|
||||
bool "GPIO0 Input"
|
||||
help
|
||||
Input of 50MHz RMII clock on GPIO0.
|
||||
config PHY_CLOCK_GPIO0_OUT
|
||||
bool "GPIO0 Output"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO0.
|
||||
config PHY_CLOCK_GPIO16_OUT
|
||||
bool "GPIO16 Output"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO16.
|
||||
config PHY_CLOCK_GPIO17_OUT
|
||||
bool "GPIO17 Output (inverted)"
|
||||
help
|
||||
Output the internal 50MHz RMII clock on GPIO17 (inverted signal).
|
||||
endchoice
|
||||
|
||||
config PHY_CLOCK_MODE
|
||||
int
|
||||
default 0 if PHY_CLOCK_GPIO0_IN
|
||||
default 2 if PHY_CLOCK_GPIO16_OUT
|
||||
default 3 if PHY_CLOCK_GPIO17_OUT
|
||||
config PHY_CLOCK_MODE
|
||||
int
|
||||
default 0 if PHY_CLOCK_GPIO0_IN
|
||||
default 1 if PHY_CLOCK_GPIO0_OUT
|
||||
default 2 if PHY_CLOCK_GPIO16_OUT
|
||||
default 3 if PHY_CLOCK_GPIO17_OUT
|
||||
|
||||
config PHY_USE_POWER_PIN
|
||||
bool "Use PHY Power (enable/disable) pin"
|
||||
default y
|
||||
help
|
||||
Use a GPIO "power pin" to power the PHY on/off during operation.
|
||||
config PHY_USE_POWER_PIN
|
||||
bool "Use PHY Power (enable / disable) pin"
|
||||
default n
|
||||
help
|
||||
Use a GPIO "power pin" to power the PHY on/off during operation.
|
||||
When using GPIO0 to input RMII clock, the reset process will be interfered by this clock.
|
||||
So we need another GPIO to control the switch on / off of the RMII clock.
|
||||
|
||||
if PHY_USE_POWER_PIN
|
||||
config PHY_POWER_PIN
|
||||
int "PHY Power GPIO"
|
||||
default 17
|
||||
range 0 33
|
||||
help
|
||||
GPIO number to use for powering on/off the PHY.
|
||||
endif
|
||||
endmenu
|
||||
if PHY_USE_POWER_PIN
|
||||
config PHY_POWER_PIN
|
||||
int "PHY Power GPIO"
|
||||
default 17
|
||||
range 0 33
|
||||
depends on PHY_USE_POWER_PIN
|
||||
help
|
||||
GPIO number to use for powering on/off the PHY.
|
||||
endif
|
||||
endmenu
|
||||
|
||||
menu "Etherent SMI interface"
|
||||
config PHY_SMI_MDC_PIN
|
||||
int "SMI MDC Pin"
|
||||
default 23
|
||||
range 0 33
|
||||
help
|
||||
GPIO number to use for SMI clock output MDC to PHY.
|
||||
menu "Etherent SMI interface"
|
||||
config PHY_SMI_MDC_PIN
|
||||
int "SMI MDC Pin Number"
|
||||
default 23
|
||||
range 0 33
|
||||
help
|
||||
GPIO number used for SMI clock signal.
|
||||
|
||||
config PHY_SMI_MDIO_PIN
|
||||
int "SMI MDIO Pin"
|
||||
default 18
|
||||
range 0 33
|
||||
help
|
||||
GPIO number to use for SMI data pin MDIO to/from PHY.
|
||||
endmenu
|
||||
config PHY_SMI_MDIO_PIN
|
||||
int "SMI MDIO Pin Number"
|
||||
default 18
|
||||
range 0 33
|
||||
help
|
||||
GPIO number used for SMI data signal.
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -19,13 +19,15 @@
|
|||
#include "iperf.h"
|
||||
#include "sdkconfig.h"
|
||||
|
||||
#ifdef CONFIG_PHY_LAN8720
|
||||
#if CONFIG_PHY_LAN8720
|
||||
#include "eth_phy/phy_lan8720.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_lan8720_default_ethernet_config
|
||||
#endif
|
||||
#ifdef CONFIG_PHY_TLK110
|
||||
#elif CONFIG_PHY_TLK110
|
||||
#include "eth_phy/phy_tlk110.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_tlk110_default_ethernet_config
|
||||
#elif CONFIG_PHY_IP101
|
||||
#include "eth_phy/phy_ip101.h"
|
||||
#define DEFAULT_ETHERNET_PHY_CONFIG phy_ip101_default_ethernet_config
|
||||
#endif
|
||||
|
||||
static tcpip_adapter_ip_info_t ip;
|
||||
|
|
|
@ -46,7 +46,6 @@ IGNORE_DIRS = (
|
|||
os.path.join('components', 'esp_http_client'),
|
||||
os.path.join('components', 'esp_http_server'),
|
||||
os.path.join('components', 'esptool_py'),
|
||||
os.path.join('components', 'ethernet'),
|
||||
os.path.join('components', 'fatfs'),
|
||||
os.path.join('components', 'freemodbus'),
|
||||
os.path.join('components', 'freertos'),
|
||||
|
@ -73,8 +72,6 @@ IGNORE_DIRS = (
|
|||
os.path.join('examples', 'bluetooth', 'ble_throughput', 'throughput_client', 'main'),
|
||||
os.path.join('examples', 'bluetooth', 'ble_throughput', 'throughput_server', 'main'),
|
||||
os.path.join('examples', 'bluetooth', 'gatt_server', 'main'),
|
||||
os.path.join('examples', 'ethernet', 'ethernet', 'main'),
|
||||
os.path.join('examples', 'ethernet', 'iperf', 'main'),
|
||||
os.path.join('examples', 'get-started', 'blink', 'main'),
|
||||
os.path.join('examples', 'mesh', 'internal_communication', 'main'),
|
||||
os.path.join('examples', 'mesh', 'manual_networking', 'main'),
|
||||
|
|
Ładowanie…
Reference in New Issue