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Merge branch 'refactor/no_dac_on_esp32s3' into 'master' 

dac: added DAC support macro

Closes IDF-1777

See merge request espressif/esp-idf!13038
pull/6882/head
Michael (XIAO Xufeng) 2021-04-12 10:52:33 +00:00
rodzic 8cfcf6da7a 75dfd970b4
commit 7e06a60c0d
19 zmienionych plików z 13 dodań i 374 usunięć
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1
components/driver/CMakeLists.txt
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@ -55,7 +55,6 @@ endif()
if(${target} STREQUAL "esp32s3")
list(APPEND srcs "adc_common.c"
"dac_common.c"
"dedic_gpio.c"
"gdma.c"
"spi_slave_hd.c"

6
components/driver/adc_common.c
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@ -30,7 +30,7 @@
#include "hal/adc_types.h"
#include "hal/adc_hal.h"
#if SOC_DAC_PERIPH_NUM > 0
#if SOC_DAC_SUPPORTED
#include "driver/dac.h"
#include "hal/dac_hal.h"
#endif
@ -248,7 +248,9 @@ static void adc_rtc_chan_init(adc_unit_t adc_unit)
if (adc_unit & ADC_UNIT_1) {
/* Workaround: Disable the synchronization operation function of ADC1 and DAC.
If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage. */
#if SOC_DAC_SUPPORTED
dac_hal_rtc_sync_by_adc(false);
#endif
adc_hal_rtc_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT);
adc_hal_set_sar_clk_div(ADC_NUM_1, SOC_ADC_SAR_CLK_DIV_DEFAULT(ADC_NUM_1));
#ifdef CONFIG_IDF_TARGET_ESP32
@ -532,6 +534,7 @@ static inline void adc2_init(void)
static inline void adc2_dac_disable( adc2_channel_t channel)
{
#if SOC_DAC_SUPPORTED
#ifdef CONFIG_IDF_TARGET_ESP32
if ( channel == ADC2_CHANNEL_8 ) { // the same as DAC channel 1
dac_output_disable(DAC_CHANNEL_1);
@ -545,6 +548,7 @@ static inline void adc2_dac_disable( adc2_channel_t channel)
dac_output_disable(DAC_CHANNEL_2);
}
#endif
#endif // SOC_DAC_SUPPORTED
}
/**

80
components/driver/esp32s3/include/driver/dac.h
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@ -1,80 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#include "driver/dac_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
/**
* @brief DAC digital controller initialization.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_init(void);
/**
* @brief DAC digital controller deinitialization.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_deinit(void);
/**
* @brief Setting the DAC digital controller.
*
* @param cfg Pointer to digital controller paramter. See ``dac_digi_config_t``.
*
* @return
* - ESP_OK success
* - ESP_ERR_INVALID_ARG Parameter error
*/
esp_err_t dac_digi_controller_config(const dac_digi_config_t *cfg);
/**
* @brief DAC digital controller start output voltage.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_start(void);
/**
* @brief DAC digital controller stop output voltage.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_stop(void);
/**
* @brief Reset DAC digital controller FIFO.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_fifo_reset(void);
/**
* @brief Reset DAC digital controller.
* @return
* - ESP_OK success
*/
esp_err_t dac_digi_reset(void);
#ifdef __cplusplus
}
#endif

5
components/driver/test/test_dac.c
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@ -12,8 +12,9 @@
#include "nvs_flash.h"
#include "test_utils.h"
#include "driver/i2s.h"
#include "soc/soc_caps.h"
#if !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
#if SOC_DAC_SUPPORTED
#include "driver/dac.h"
#include "esp_adc_cal.h"
@ -182,4 +183,4 @@ TEST_CASE("esp32s2 adc2-dac with adc2 calibration", "[adc-dac]")
}
#endif
#endif // !DISABLED_FOR_TARGETS(ESP32C3) && !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
#endif // SOC_DAC_SUPPORTED

1
components/hal/CMakeLists.txt
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@ -70,7 +70,6 @@ if(NOT BOOTLOADER_BUILD)
if(${target} STREQUAL "esp32s3")
list(APPEND srcs
"dac_hal.c"
"gdma_hal.c"
"lcd_hal.c"
"pcnt_hal.c"

206
components/hal/esp32s3/include/hal/dac_ll.h
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@ -1,206 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*******************************************************************************
* NOTICE
* The ll is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdlib.h>
#include "soc/dac_periph.h"
#include "hal/dac_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* Power on dac module and start output voltage.
*
* @note Before powering up, make sure the DAC PAD is set to RTC PAD and floating status.
* @param channel DAC channel num.
*/
static inline void dac_ll_power_on(dac_channel_t channel)
{
RTCIO.pad_dac[channel].dac_xpd_force = 1;
RTCIO.pad_dac[channel].xpd_dac = 1;
}
/**
* Power done dac module and stop output voltage.
*
* @param channel DAC channel num.
*/
static inline void dac_ll_power_down(dac_channel_t channel)
{
RTCIO.pad_dac[channel].dac_xpd_force = 0;
RTCIO.pad_dac[channel].xpd_dac = 0;
}
/**
* Output voltage with value (8 bit).
*
* @param channel DAC channel num.
* @param value Output value. Value range: 0 ~ 255.
* The corresponding range of voltage is 0v ~ VDD3P3_RTC.
*/
static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value)
{
if (channel == DAC_CHANNEL_1) {
SENS.sar_dac_ctrl2.dac_cw_en1 = 0;
RTCIO.pad_dac[channel].dac = value;
} else if (channel == DAC_CHANNEL_2) {
SENS.sar_dac_ctrl2.dac_cw_en2 = 0;
RTCIO.pad_dac[channel].dac = value;
}
}
/**
* Enable/disable the synchronization operation function of ADC1 and DAC.
*
* @note If enabled(default), ADC RTC controller sampling will cause the DAC channel output voltage.
*
* @param enable Enable or disable adc and dac synchronization function.
*/
static inline void dac_ll_rtc_sync_by_adc(bool enable)
{
// SENS.sar_meas_ctrl2.sar1_dac_xpd_fsm = enable;
}
/************************************/
/* DAC cosine wave generator API's */
/************************************/
/**
* Enable cosine wave generator output.
*/
static inline void dac_ll_cw_generator_enable(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 1;
}
/**
* Disable cosine wave generator output.
*/
static inline void dac_ll_cw_generator_disable(void)
{
SENS.sar_dac_ctrl1.sw_tone_en = 0;
}
/**
* Enable the cosine wave generator of DAC channel.
*
* @param channel DAC channel num.
* @param enable
*/
static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
{
if (channel == DAC_CHANNEL_1) {
SENS.sar_dac_ctrl2.dac_cw_en1 = enable;
} else if (channel == DAC_CHANNEL_2) {
SENS.sar_dac_ctrl2.dac_cw_en2 = enable;
}
}
/**
* Set frequency of cosine wave generator output.
*
* @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error.
* @param freq_hz CW generator frequency. Range: 130(130Hz) ~ 55000(100KHz).
*/
static inline void dac_ll_cw_set_freq(uint32_t freq)
{
uint32_t sw_freq = freq * 0xFFFF / RTC_FAST_CLK_FREQ_APPROX;
SENS.sar_dac_ctrl1.sw_fstep = (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq;
}
/**
* Set the amplitude of the cosine wave generator output.
*
* @param channel DAC channel num.
* @param scale The multiple of the amplitude. The max amplitude is VDD3P3_RTC.
*/
static inline void dac_ll_cw_set_scale(dac_channel_t channel, dac_cw_scale_t scale)
{
if (channel == DAC_CHANNEL_1) {
SENS.sar_dac_ctrl2.dac_scale1 = scale;
} else if (channel == DAC_CHANNEL_2) {
SENS.sar_dac_ctrl2.dac_scale2 = scale;
}
}
/**
* Set the phase of the cosine wave generator output.
*
* @param channel DAC channel num.
* @param scale Phase value.
*/
static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cw_phase_t phase)
{
if (channel == DAC_CHANNEL_1) {
SENS.sar_dac_ctrl2.dac_inv1 = phase;
} else if (channel == DAC_CHANNEL_2) {
SENS.sar_dac_ctrl2.dac_inv2 = phase;
}
}
/**
* Set the voltage value of the DC component of the cosine wave generator output.
*
* @note The DC offset setting should be after phase setting.
* @note Unreasonable settings can cause the signal to be oversaturated.
* @param channel DAC channel num.
* @param offset DC value. Range: -128 ~ 127.
*/
static inline void dac_ll_cw_set_dc_offset(dac_channel_t channel, int8_t offset)
{
if (channel == DAC_CHANNEL_1) {
if (SENS.sar_dac_ctrl2.dac_inv1 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc1 = offset ? offset : (-128 - offset);
} else if (channel == DAC_CHANNEL_2) {
if (SENS.sar_dac_ctrl2.dac_inv2 == DAC_CW_PHASE_180) {
offset = 0 - offset;
}
SENS.sar_dac_ctrl2.dac_dc2 = offset ? offset : (-128 - offset);
}
}
/************************************/
/* DAC DMA API's */
/************************************/
/**
* Enable DAC output data from I2S DMA.
* I2S_CLK connect to DAC_CLK, I2S_DATA_OUT connect to DAC_DATA.
*/
static inline void dac_ll_dma_enable(void)
{
SENS.sar_dac_ctrl1.dac_dig_force = 1;
}
/**
* Disable DAC output data from I2S DMA.
*/
static inline void dac_ll_dma_disable(void)
{
SENS.sar_dac_ctrl1.dac_dig_force = 0;
}
#ifdef __cplusplus
}
#endif

1
components/soc/esp32/include/soc/soc_caps.h
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@ -60,6 +60,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_CAPS_ECO_VER_MAX 3
#define SOC_DAC_SUPPORTED 1
#define SOC_MCPWM_SUPPORTED 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_BT_SUPPORTED 1

1
components/soc/esp32c3/include/soc/soc.h
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@ -27,7 +27,6 @@
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_DMA_COPY_BASE 0x600c3000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_AES_BASE 0x6003a000

4
components/soc/esp32c3/include/soc/soc_caps.h
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@ -13,10 +13,6 @@
#define SOC_HMAC_SUPPORTED 1
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_PERIPH_NUM 0
#include "i2c_caps.h"
#include "mpu_caps.h"
#include "sigmadelta_caps.h"

2
components/soc/esp32s2/include/soc/soc_caps.h
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@ -37,6 +37,7 @@
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
#define SOC_DAC_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_CP_DMA_SUPPORTED 1
#define SOC_CPU_CORES_NUM 1
@ -87,7 +88,6 @@
/*-------------------------- DAC CAPS ----------------------------------------*/
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
/*-------------------------- GPIO CAPS ---------------------------------------*/

1
components/soc/esp32s3/CMakeLists.txt
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@ -1,6 +1,5 @@
set(srcs
"adc_periph.c"
"dac_periph.c"
"dedic_gpio_periph.c"
"gdma_periph.c"
"gpio_periph.c"

23
components/soc/esp32s3/dac_periph.c
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@ -1,23 +0,0 @@
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/dac_periph.h"
/*
Bunch of constants for DAC peripheral: GPIO number
*/
const dac_signal_conn_t dac_periph_signal = {
.dac_channel_io_num[0] = DAC_CHANNEL_1_GPIO_NUM,
.dac_channel_io_num[1] = DAC_CHANNEL_2_GPIO_NUM,
};

22
components/soc/esp32s3/include/soc/dac_caps.h
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@ -1,22 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_RTC_DAC_CAPS_H_
#define _SOC_RTC_DAC_CAPS_H_
#define SOC_DAC_PERIPH_NUM 2
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
#endif

24
components/soc/esp32s3/include/soc/dac_channel.h
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@ -1,24 +0,0 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_DAC_CHANNEL_H
#define _SOC_DAC_CHANNEL_H
#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1
#define DAC_CHANNEL_1_GPIO_NUM 17
#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2
#define DAC_CHANNEL_2_GPIO_NUM 18
#endif

1
components/soc/esp32s3/include/soc/soc.h
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@ -31,7 +31,6 @@
#define DR_REG_SYSTEM_BASE 0x600c0000
#define DR_REG_SENSITIVE_BASE 0x600c1000
#define DR_REG_INTERRUPT_BASE 0x600c2000
#define DR_REG_DMA_COPY_BASE 0x600c3000
#define DR_REG_EXTMEM_BASE 0x600c4000
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_ITAG_TABLE 0x600c6000

3
components/soc/esp32s3/include/soc/soc_caps.h
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@ -32,9 +32,6 @@
/*-------------------------- CPU CAPS ----------------------------------------*/
#include "cpu_caps.h"
/*-------------------------- DAC CAPS ----------------------------------------*/
#include "dac_caps.h"
/*-------------------------- GDMA CAPS ---------------------------------------*/
#include "gdma_caps.h"

2
docs/conf_common.py
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@ -207,7 +207,7 @@ conditional_include_dict = {'SOC_BT_SUPPORTED':BT_DOCS,
'SOC_DEDICATED_GPIO_SUPPORTED':DEDIC_GPIO_DOCS,
'SOC_SPIRAM_SUPPORTED':SPIRAM_DOCS,
'SOC_PCNT_SUPPORTED':PCNT_DOCS,
'SOC_DAC_PERIPH_NUM':DAC_DOCS,
'SOC_DAC_SUPPORTED':DAC_DOCS,
'SOC_TOUCH_SENSOR_NUM':TOUCH_SENSOR_DOCS,
'SOC_ULP_SUPPORTED':ULP_DOCS,
'SOC_RISCV_COPROC_SUPPORTED':RISCV_COPROC_DOCS,

2
docs/en/api-reference/peripherals/index.rst
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@ -8,7 +8,7 @@ Peripherals API
ADC <adc>
:SOC_DAC_PERIPH_NUM: DAC <dac>
:SOC_DAC_SUPPORTED: DAC <dac>
General Purpose Timer <timer>
GPIO (including RTC low power I/O) <gpio>
:SOC_DEDICATED_GPIO_SUPPORTED: Dedicated GPIO <dedic_gpio>

2
docs/zh_CN/api-reference/peripherals/index.rst
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@ -7,7 +7,7 @@
:maxdepth: 1
ADC <adc>
:SOC_DAC_PERIPH_NUM: DAC <dac>
:SOC_DAC_SUPPORTED: DAC <dac>
通用定时器 <timer>
GPIO (包括 RTC 低功耗 I/O) <gpio>
:SOC_DEDICATED_GPIO_SUPPORTED: 专用 GPIO <dedic_gpio>